[coreboot-gerrit] Patch set updated for coreboot: 841f50a baytrail: allow downstream use of SSE instructions
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Wed Feb 5 17:04:48 CET 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4881
-gerrit
commit 841f50ae16bb197d532fd9a74ac010a00cd008f1
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Oct 10 12:47:47 2013 -0500
baytrail: allow downstream use of SSE instructions
If a payload is compiled to use SSE instructions it will
fault with an undefined opcode because SSE instructions weren't
enabled. Therefore enable SSE instructions at runtime.
BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted with SSE enabled payload. No exceptions seen.
Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172642
Reviewed-by: Stefan Reinauer <reinauer at google.com>
---
src/soc/intel/baytrail/ramstage.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 10c030f..229e367 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -20,6 +20,7 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
+#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci_def.h>
@@ -109,6 +110,9 @@ void baytrail_init_pre_device(void)
fill_in_pattrs();
+ /* Allow for SSE instructions to be executed. */
+ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
+
/* Get GPIO initial states from mainboard */
config = mainboard_get_gpios();
setup_soc_gpios(config);
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