[coreboot-gerrit] Patch merged into coreboot/master: 61b4003 Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 61b4003d0a1fc4ef7cf1e69a352bf6137c1300de
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jan 6 11:06:26 2014 +0200

    Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
    
    This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
    set with values that are not power of 2. The region programmed
    as WB cacheable will include all of ROM_SIZE.
    
    Side-effects to consider:
    
    Memory region below flash may be tagged WRPROT cacheable. As an
    example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
    Since this can overlap CAR, we add an explicit test and fail
    on compile should this happen. To work around this problem, one
    needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
    define a smaller region for WB cache.
    
    With this change flash regions outside CBFS are also tagged WRPROT
    cacheable. This covers IFD and ME and sections ChromeOS may use.
    
    Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>


See http://review.coreboot.org/4625 for details.

-gerrit