[coreboot-gerrit] Patch set updated for coreboot: 7848434 jetway/j7f24: Rename to jetway/j7f2.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sat Jan 18 23:58:29 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4728
-gerrit
commit 7848434a83e7851c371ff132785ed8e828652ebc
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sat Jan 18 23:29:55 2014 +0100
jetway/j7f24: Rename to jetway/j7f2.
Original actually meant j7f[24] which without square brackets
became confusing. There is no such board as j7f24.
This is a prerequisite to adding j7f4* as cloned boards
Change-Id: Ia7708b13ac4141ef788183c7817fce1366919936
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/jetway/Kconfig | 6 +-
src/mainboard/jetway/j7f2/Kconfig | 26 ++++++++
src/mainboard/jetway/j7f2/cmos.layout | 74 ++++++++++++++++++++++
src/mainboard/jetway/j7f2/devicetree.cb | 62 ++++++++++++++++++
src/mainboard/jetway/j7f2/irq_tables.c | 54 ++++++++++++++++
src/mainboard/jetway/j7f2/romstage.c | 105 +++++++++++++++++++++++++++++++
src/mainboard/jetway/j7f24/Kconfig | 27 --------
src/mainboard/jetway/j7f24/cmos.layout | 74 ----------------------
src/mainboard/jetway/j7f24/devicetree.cb | 62 ------------------
src/mainboard/jetway/j7f24/irq_tables.c | 54 ----------------
src/mainboard/jetway/j7f24/romstage.c | 105 -------------------------------
11 files changed, 324 insertions(+), 325 deletions(-)
diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig
index 8023665..ff8fa97 100644
--- a/src/mainboard/jetway/Kconfig
+++ b/src/mainboard/jetway/Kconfig
@@ -3,14 +3,14 @@ if VENDOR_JETWAY
choice
prompt "Mainboard model"
-config BOARD_JETWAY_J7F24
- bool "J7F24"
+config BOARD_JETWAY_J7F2
+ bool "J7F2"
config BOARD_JETWAY_PA78VM5
bool "PA78VM5 (Fam10)"
endchoice
-source "src/mainboard/jetway/j7f24/Kconfig"
+source "src/mainboard/jetway/j7f2/Kconfig"
source "src/mainboard/jetway/pa78vm5/Kconfig"
config MAINBOARD_VENDOR
diff --git a/src/mainboard/jetway/j7f2/Kconfig b/src/mainboard/jetway/j7f2/Kconfig
new file mode 100644
index 0000000..2b024cc
--- /dev/null
+++ b/src/mainboard/jetway/j7f2/Kconfig
@@ -0,0 +1,26 @@
+if BOARD_JETWAY_J7F2
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_VIA_C7
+ select NORTHBRIDGE_VIA_CN700
+ select SOUTHBRIDGE_VIA_VT8237R
+ select SUPERIO_FINTEK_F71805F
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select BOARD_ROMSIZE_KB_512
+
+config MAINBOARD_DIR
+ string
+ default jetway/j7f2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "J7f2"
+
+config IRQ_SLOT_COUNT
+ int
+ default 10
+
+endif # BOARD_JETWAY_J7F2
diff --git a/src/mainboard/jetway/j7f2/cmos.layout b/src/mainboard/jetway/j7f2/cmos.layout
new file mode 100644
index 0000000..c1354a2
--- /dev/null
+++ b/src/mainboard/jetway/j7f2/cmos.layout
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
diff --git a/src/mainboard/jetway/j7f2/devicetree.cb b/src/mainboard/jetway/j7f2/devicetree.cb
new file mode 100644
index 0000000..3b99b9c
--- /dev/null
+++ b/src/mainboard/jetway/j7f2/devicetree.cb
@@ -0,0 +1,62 @@
+chip northbridge/via/cn700 # Northbridge
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ chip southbridge/via/vt8237r # Southbridge
+ # Enable both IDE channels.
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ # Both cables are 40pin.
+ register "ide0_80pin_cable" = "0"
+ register "ide1_80pin_cable" = "0"
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci a.0 on end # Firewire
+ device pci f.0 on end # SATA
+ device pci f.1 on end # IDE
+ device pci 10.0 on end # OHCI
+ device pci 10.1 on end # OHCI
+ device pci 10.2 on end # OHCI
+ device pci 10.3 on end # OHCI
+ device pci 10.4 on end # EHCI
+ device pci 11.0 on # Southbridge LPC
+ chip superio/fintek/f71805f # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+ end
+ end
+ device pci 11.5 on end # AC'97 audio
+ # device pci 11.6 off end # AC'97 Modem
+ device pci 12.0 on end # Ethernet
+ end
+ end
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/via/c7 # VIA C7
+ device lapic 0 on end # APIC
+ end
+ end
+end
diff --git a/src/mainboard/jetway/j7f2/irq_tables.c b/src/mainboard/jetway/j7f2/irq_tables.c
new file mode 100644
index 0000000..888cf48
--- /dev/null
+++ b/src/mainboard/jetway/j7f2/irq_tables.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x11 << 3) | 0x0, /* Interrupt router device */
+ 0x828, /* IRQs devoted exclusively to PCI usage */
+ 0x1106, /* Vendor */
+ 0x596, /* Device */
+ 0, /* Miniport data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x3e, /* Checksum */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
+ {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
+ {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
+ {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
+ {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
+ {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c
new file mode 100644
index 0000000..928fcef
--- /dev/null
+++ b/src/mainboard/jetway/j7f2/romstage.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "northbridge/via/cn700/raminit.h"
+#include "cpu/x86/bist.h"
+#include "drivers/pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "superio/fintek/f71805f/early_serial.c"
+#include <lib.h>
+#include <spd.h>
+
+#if CONFIG_TTYS0_BASE == 0x2f8
+#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
+#else
+#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1)
+#endif
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/via/cn700/raminit.c"
+
+static void enable_mainboard_devices(void)
+{
+ device_t dev;
+
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ if (dev == PCI_DEV_INVALID)
+ die("Southbridge not found!!!\n");
+
+ /* bit=0 means enable function (per CX700 datasheet)
+ * 5 16.1 USB 2
+ * 4 16.0 USB 1
+ * 3 15.0 SATA and PATA
+ * 2 16.2 USB 3
+ * 1 16.4 USB EHCI
+ */
+ pci_write_config8(dev, 0x50, 0x80);
+
+ /* bit=1 means enable internal function (per CX700 datasheet)
+ * 3 Internal RTC
+ * 2 Internal PS2 Mouse
+ * 1 Internal KBC Configuration
+ * 0 Internal Keyboard Controller
+ */
+ pci_write_config8(dev, 0x51, 0x1d);
+}
+
+static const struct mem_controller ctrl = {
+ .d0f0 = 0x0000,
+ .d0f2 = 0x2000,
+ .d0f3 = 0x3000,
+ .d0f4 = 0x4000,
+ .d0f7 = 0x7000,
+ .d1f0 = 0x8000,
+ .channel0 = { DIMM0 },
+};
+
+void main(unsigned long bist)
+{
+ /* Enable multifunction for northbridge. */
+ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
+
+ f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ enable_smbus();
+ smbus_fixup(&ctrl);
+
+ /* Halt if there was a built-in self test failure. */
+ report_bist_failure(bist);
+
+ enable_mainboard_devices();
+
+ ddr_ram_setup(&ctrl);
+}
diff --git a/src/mainboard/jetway/j7f24/Kconfig b/src/mainboard/jetway/j7f24/Kconfig
deleted file mode 100644
index fa17eba..0000000
--- a/src/mainboard/jetway/j7f24/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-# FIXME: There is no such board, "J7F24" is probably too generic and/or wrong.
-if BOARD_JETWAY_J7F24
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select ARCH_X86
- select CPU_VIA_C7
- select NORTHBRIDGE_VIA_CN700
- select SOUTHBRIDGE_VIA_VT8237R
- select SUPERIO_FINTEK_F71805F
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select BOARD_ROMSIZE_KB_512
-
-config MAINBOARD_DIR
- string
- default jetway/j7f24
-
-config MAINBOARD_PART_NUMBER
- string
- default "J7f24"
-
-config IRQ_SLOT_COUNT
- int
- default 10
-
-endif # BOARD_JETWAY_J7F24
diff --git a/src/mainboard/jetway/j7f24/cmos.layout b/src/mainboard/jetway/j7f24/cmos.layout
deleted file mode 100644
index c1354a2..0000000
--- a/src/mainboard/jetway/j7f24/cmos.layout
+++ /dev/null
@@ -1,74 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
-
-
diff --git a/src/mainboard/jetway/j7f24/devicetree.cb b/src/mainboard/jetway/j7f24/devicetree.cb
deleted file mode 100644
index 3b99b9c..0000000
--- a/src/mainboard/jetway/j7f24/devicetree.cb
+++ /dev/null
@@ -1,62 +0,0 @@
-chip northbridge/via/cn700 # Northbridge
- device domain 0 on # PCI domain
- device pci 0.0 on end # AGP Bridge
- device pci 0.1 on end # Error Reporting
- device pci 0.2 on end # Host Bus Control
- device pci 0.3 on end # Memory Controller
- device pci 0.4 on end # Power Management
- device pci 0.7 on end # V-Link Controller
- device pci 1.0 on end # PCI Bridge
- chip southbridge/via/vt8237r # Southbridge
- # Enable both IDE channels.
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- # Both cables are 40pin.
- register "ide0_80pin_cable" = "0"
- register "ide1_80pin_cable" = "0"
- register "fn_ctrl_lo" = "0x80"
- register "fn_ctrl_hi" = "0x1d"
- device pci a.0 on end # Firewire
- device pci f.0 on end # SATA
- device pci f.1 on end # IDE
- device pci 10.0 on end # OHCI
- device pci 10.1 on end # OHCI
- device pci 10.2 on end # OHCI
- device pci 10.3 on end # OHCI
- device pci 10.4 on end # EHCI
- device pci 11.0 on # Southbridge LPC
- chip superio/fintek/f71805f # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0xec00
- end
- end
- end
- device pci 11.5 on end # AC'97 audio
- # device pci 11.6 off end # AC'97 Modem
- device pci 12.0 on end # Ethernet
- end
- end
- device cpu_cluster 0 on # APIC cluster
- chip cpu/via/c7 # VIA C7
- device lapic 0 on end # APIC
- end
- end
-end
diff --git a/src/mainboard/jetway/j7f24/irq_tables.c b/src/mainboard/jetway/j7f24/irq_tables.c
deleted file mode 100644
index 888cf48..0000000
--- a/src/mainboard/jetway/j7f24/irq_tables.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- (0x11 << 3) | 0x0, /* Interrupt router device */
- 0x828, /* IRQs devoted exclusively to PCI usage */
- 0x1106, /* Vendor */
- 0x596, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x3e, /* Checksum */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
- {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
- {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
- {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
- {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
- {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
- {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
- {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
- {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
deleted file mode 100644
index 928fcef..0000000
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <console/console.h>
-#include "northbridge/via/cn700/raminit.h"
-#include "cpu/x86/bist.h"
-#include "drivers/pc80/udelay_io.c"
-#include "lib/delay.c"
-#include "southbridge/via/vt8237r/early_smbus.c"
-#include "superio/fintek/f71805f/early_serial.c"
-#include <lib.h>
-#include <spd.h>
-
-#if CONFIG_TTYS0_BASE == 0x2f8
-#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
-#else
-#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1)
-#endif
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/via/cn700/raminit.c"
-
-static void enable_mainboard_devices(void)
-{
- device_t dev;
-
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID)
- die("Southbridge not found!!!\n");
-
- /* bit=0 means enable function (per CX700 datasheet)
- * 5 16.1 USB 2
- * 4 16.0 USB 1
- * 3 15.0 SATA and PATA
- * 2 16.2 USB 3
- * 1 16.4 USB EHCI
- */
- pci_write_config8(dev, 0x50, 0x80);
-
- /* bit=1 means enable internal function (per CX700 datasheet)
- * 3 Internal RTC
- * 2 Internal PS2 Mouse
- * 1 Internal KBC Configuration
- * 0 Internal Keyboard Controller
- */
- pci_write_config8(dev, 0x51, 0x1d);
-}
-
-static const struct mem_controller ctrl = {
- .d0f0 = 0x0000,
- .d0f2 = 0x2000,
- .d0f3 = 0x3000,
- .d0f4 = 0x4000,
- .d0f7 = 0x7000,
- .d1f0 = 0x8000,
- .channel0 = { DIMM0 },
-};
-
-void main(unsigned long bist)
-{
- /* Enable multifunction for northbridge. */
- pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
-
- f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- enable_smbus();
- smbus_fixup(&ctrl);
-
- /* Halt if there was a built-in self test failure. */
- report_bist_failure(bist);
-
- enable_mainboard_devices();
-
- ddr_ram_setup(&ctrl);
-}
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