[coreboot-gerrit] New patch to review for coreboot: 40cb83d amd/cache_as_ram: Control flow in cache_as_ram_inc.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sun Jan 26 02:51:32 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4812
-gerrit
commit 40cb83d6d90bc12bcfede0fd65e26422a5a678bb
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Fri Jan 24 08:24:44 2014 +0100
amd/cache_as_ram: Control flow in cache_as_ram_inc.
Current stack copying and stack switching isn't really necessarry.
Change-Id: I61ff60121f0cc49cf45c9aff301e1a4672ea4048
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/cpu/amd/car/cache_as_ram.inc | 16 +++++--------
src/cpu/amd/car/post_cache_as_ram.c | 26 ++++++----------------
src/include/lib.h | 1 -
src/mainboard/advansus/a785e-i/romstage.c | 2 --
src/mainboard/amd/bimini_fam10/romstage.c | 2 --
src/mainboard/amd/dbm690t/romstage.c | 1 -
src/mainboard/amd/mahogany/romstage.c | 1 -
src/mainboard/amd/mahogany_fam10/romstage.c | 2 --
src/mainboard/amd/pistachio/romstage.c | 1 -
src/mainboard/amd/serengeti_cheetah/romstage.c | 1 -
.../amd/serengeti_cheetah_fam10/romstage.c | 2 --
src/mainboard/amd/tilapia_fam10/romstage.c | 2 --
src/mainboard/arima/hdama/romstage.c | 1 -
src/mainboard/asrock/939a785gmh/romstage.c | 1 -
src/mainboard/asus/a8n_e/romstage.c | 1 -
src/mainboard/asus/a8v-e_deluxe/romstage.c | 1 -
src/mainboard/asus/a8v-e_se/romstage.c | 1 -
src/mainboard/asus/k8v-x/romstage.c | 1 -
src/mainboard/asus/m2n-e/romstage.c | 1 -
src/mainboard/asus/m2v-mx_se/romstage.c | 1 -
src/mainboard/asus/m2v/romstage.c | 1 -
src/mainboard/asus/m4a78-em/romstage.c | 2 --
src/mainboard/asus/m4a785-m/romstage.c | 2 --
src/mainboard/asus/m5a88-v/romstage.c | 2 --
src/mainboard/avalue/eax-785e/romstage.c | 2 --
src/mainboard/broadcom/blast/romstage.c | 1 -
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 1 -
src/mainboard/gigabyte/m57sli/romstage.c | 1 -
src/mainboard/gigabyte/ma785gm/romstage.c | 2 --
src/mainboard/gigabyte/ma785gmt/romstage.c | 2 --
src/mainboard/gigabyte/ma78gm/romstage.c | 2 --
src/mainboard/hp/dl145_g1/romstage.c | 1 -
src/mainboard/hp/dl145_g3/romstage.c | 1 -
src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 -
src/mainboard/ibm/e325/romstage.c | 1 -
src/mainboard/ibm/e326/romstage.c | 1 -
src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 --
src/mainboard/iwill/dk8_htx/romstage.c | 1 -
src/mainboard/iwill/dk8s2/romstage.c | 1 -
src/mainboard/iwill/dk8x/romstage.c | 1 -
src/mainboard/jetway/pa78vm5/romstage.c | 2 --
src/mainboard/kontron/kt690/romstage.c | 1 -
src/mainboard/msi/ms7135/romstage.c | 1 -
src/mainboard/msi/ms7260/romstage.c | 1 -
src/mainboard/msi/ms9185/romstage.c | 1 -
src/mainboard/msi/ms9282/romstage.c | 1 -
src/mainboard/msi/ms9652_fam10/romstage.c | 2 --
src/mainboard/newisys/khepri/romstage.c | 1 -
src/mainboard/nvidia/l1_2pvv/romstage.c | 1 -
src/mainboard/siemens/sitemp_g1p1/romstage.c | 1 -
src/mainboard/sunw/ultra40/romstage.c | 1 -
src/mainboard/supermicro/h8dme/romstage.c | 1 -
src/mainboard/supermicro/h8dmr/romstage.c | 1 -
src/mainboard/supermicro/h8dmr_fam10/romstage.c | 3 ---
src/mainboard/supermicro/h8qme_fam10/romstage.c | 3 ---
src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 --
src/mainboard/technexion/tim5690/romstage.c | 1 -
src/mainboard/technexion/tim8690/romstage.c | 1 -
src/mainboard/tyan/s2850/romstage.c | 1 -
src/mainboard/tyan/s2875/romstage.c | 1 -
src/mainboard/tyan/s2880/romstage.c | 1 -
src/mainboard/tyan/s2881/romstage.c | 1 -
src/mainboard/tyan/s2882/romstage.c | 1 -
src/mainboard/tyan/s2885/romstage.c | 1 -
src/mainboard/tyan/s2891/romstage.c | 1 -
src/mainboard/tyan/s2892/romstage.c | 1 -
src/mainboard/tyan/s2895/romstage.c | 1 -
src/mainboard/tyan/s2912/romstage.c | 1 -
src/mainboard/tyan/s2912_fam10/romstage.c | 2 --
src/mainboard/tyan/s4880/romstage.c | 1 -
src/mainboard/tyan/s4882/romstage.c | 1 -
src/mainboard/winent/mb6047/romstage.c | 1 -
72 files changed, 12 insertions(+), 121 deletions(-)
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 8f0abce..7cb77a9 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -415,20 +415,14 @@ CAR_FAM10_ap_out:
pushl %eax /* BIST */
call cache_as_ram_main
- /* We will not go back. */
+ call cache_as_ram_finalize
- post_code(0xaf) /* Should never see this POST code. */
+ movl $((CONFIG_RAMTOP - 1) & ~0xf), %esp
+ call cache_as_ram_new_stack
- .globl cache_as_ram_switch_stack
+ /* We will not go back. */
-cache_as_ram_switch_stack:
- /* Return address. */
- popl %eax
- /* Resume memory. */
- popl %eax
- subl $(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp
- pushl %eax
- call cache_as_ram_new_stack
+ post_code(0xaf) /* Should never see this POST code. */
all_mtrr_msrs:
/* fixed MTRR MSRs */
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index f74f915..d3c8039 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -13,8 +13,9 @@ static inline void print_debug_pcar(const char *strval, uint32_t val)
printk(BIOS_DEBUG, "%s%08x\n", strval, val);
}
-/* from linux kernel 2.6.32 asm/string_32.h */
+#if CONFIG_HAVE_ACPI_RESUME
+/* from linux kernel 2.6.32 asm/string_32.h */
static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes)
{
int d0, d1, d2;
@@ -29,8 +30,6 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi
: "memory", "cc");
}
-#if CONFIG_HAVE_ACPI_RESUME
-
static inline void *backup_resume(void) {
void *resume_backup_memory;
int suspend = acpi_is_wakeup_early();
@@ -75,9 +74,9 @@ static void vErrata343(void)
#endif
}
-void cache_as_ram_switch_stack(void *resume_backup_memory);
+void *cache_as_ram_finalize(void);
-void post_cache_as_ram(void)
+void *cache_as_ram_finalize(void)
{
void *resume_backup_memory = NULL;
#if 1
@@ -92,30 +91,19 @@ void post_cache_as_ram(void)
}
#endif
- /* copy data from cache as ram to
- ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
- */
-#if CONFIG_RAMTOP <= 0x100000
- #error "You need to set CONFIG_RAMTOP greater than 1M"
-#endif
-
#if CONFIG_HAVE_ACPI_RESUME
resume_backup_memory = backup_resume();
#endif
- print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
-
- /* from here don't store more data in CAR */
vErrata343();
- memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
- cache_as_ram_switch_stack(resume_backup_memory);
+ return resume_backup_memory;
}
-void
+void __attribute__ ((regparm(1)))
cache_as_ram_new_stack (void *resume_backup_memory);
-void
+void __attribute__ ((regparm(1)))
cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused)))
{
/* We can put data to stack again */
diff --git a/src/include/lib.h b/src/include/lib.h
index bfa68e2..ebbdfa6 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -56,7 +56,6 @@ void cache_as_ram_main(void);
#else
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
#endif
-void post_cache_as_ram(void);
/* Defined in src/lib/hexdump.c */
void hexdump(const void *memory, size_t length);
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index c1366d5..4677244 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -215,8 +215,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 9f930e8..90b7840 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -219,8 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb800_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 74b6d1b..3321289 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -151,5 +151,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_before_pci_init();
sb600_before_pci_init();
- post_cache_as_ram();
}
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index b77d4b5..ee9118f 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -151,5 +151,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- post_cache_as_ram();
}
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 06deb18..9fbabcd 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -212,8 +212,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 2971072..55b0777 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -161,5 +161,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_before_pci_init();
sb600_before_pci_init();
- post_cache_as_ram();
}
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index b103389..a445e04 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -233,5 +233,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index bb7d5d3..7312ec2 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -323,8 +323,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 30e56d4..ff2366b 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -212,8 +212,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c
index 3c7eb58..914a7c1 100644
--- a/src/mainboard/arima/hdama/romstage.c
+++ b/src/mainboard/arima/hdama/romstage.c
@@ -118,5 +118,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl);
- post_cache_as_ram();
}
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index edc5830..50d8617 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -218,5 +218,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- post_cache_as_ram();
}
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 29f425a..10d12f9 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -150,5 +150,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram();
}
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 453c4c5..983fb0c 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -214,5 +214,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram();
}
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index a899bef..81549eb 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -216,5 +216,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram();
}
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 4fe1016..ce1fbbd 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -208,5 +208,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
smbus_write_byte(0x4a, 0x03, 0x04 | mask);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram();
}
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index 2f3baf6..b42decf 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -163,5 +163,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
/* BSP switch stack to RAM and copy sysinfo RAM now. */
- post_cache_as_ram();
}
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index ef0ce87..49a6f68 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -186,5 +186,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram();
}
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 1ca145d..6a8d509 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -284,5 +284,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram();
}
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 18c6f18..031e645 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -213,8 +213,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 660ab0f..91b6cf6 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -213,8 +213,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index af8e5fa..c7b7770 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -214,8 +214,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 8d4e4b2..b07c1c5 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -215,8 +215,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index fcdac69..9138782 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -144,5 +144,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram();
}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 4d215ae..2566a7d 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -198,5 +198,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
sis_init_stage2();
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 77eae09..717e6b3 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -200,5 +200,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index ecee35b..d6424da 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -208,8 +208,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index ecee35b..d6424da 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -208,8 +208,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index bd9011e..d8f65c1 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -211,8 +211,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 67ce9c1..848f215 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -159,5 +159,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
//dump_pci_devices();
- post_cache_as_ram();
}
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 0d8e9d2..445c122 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -210,5 +210,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram();
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 8e109c5..5287150 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -210,7 +210,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bcm5785_early_setup();
- post_cache_as_ram();
}
/**
diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c
index b44668a..720a300 100644
--- a/src/mainboard/ibm/e325/romstage.c
+++ b/src/mainboard/ibm/e325/romstage.c
@@ -115,5 +115,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
}
diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index c703b7a..c384121 100644
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -115,5 +115,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
}
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index e5e2c57..09360d3 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -214,8 +214,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 070fb07..6e26904 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -158,5 +158,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 7c8d4a5..103d97b 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -159,5 +159,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index b5a1d71..f99b9da 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -159,5 +159,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index b8fa48e..6bdb167 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -219,8 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 52e54d4..e4821ef 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -155,5 +155,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_before_pci_init();
sb600_before_pci_init();
- post_cache_as_ram();
}
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index ebe2526..d44dcd6 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -167,5 +167,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl);
- post_cache_as_ram();
}
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 947de0b..0ff610c 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -198,5 +198,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
/* bsp switch stack to RAM and copy sysinfo RAM now. */
- post_cache_as_ram();
}
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 2cb38a4..a208e30 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -225,5 +225,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
- post_cache_as_ram();
}
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 7f8d0e7..4310166 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -183,5 +183,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram();
}
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index b21fb02..e7eb762 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -232,8 +232,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
raminit_amdmct(sysinfo);
post_code(0x41);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index 652104a..a019993 100644
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -127,5 +127,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram();
}
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index d6ee6c6..be4bedd 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -189,5 +189,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index cdab764..e3c0cc0 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -200,6 +200,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
__WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n");
#endif
- post_cache_as_ram();
}
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index 7c112da..bbc1504 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -148,5 +148,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl);
- post_cache_as_ram();
}
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index df5e2c8..aa58975 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -265,5 +265,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 8ed7e6d..1dc9492 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -185,5 +185,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 3f6ea70..bd7e725 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -229,9 +229,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
-
- post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
- post_code(0x42); // Should never see this post code.
}
/**
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index cca464c..2c4a02e 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -279,9 +279,6 @@ post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
-
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x42); // Should never see this post code.
}
/**
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index e6ce5a8..a8ba010 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 42c2599..8ea5ac8 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -166,5 +166,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_before_pci_init();
sb600_before_pci_init();
- post_cache_as_ram();
}
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 22a1212..6faae73 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -152,5 +152,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs690_before_pci_init();
sb600_before_pci_init();
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index 301f81c..67ad063 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -101,5 +101,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 7c9f93a..aa39899 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -110,5 +110,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index 13cc01e..078aa77 100644
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -111,5 +111,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index dad2b6b..af3f782 100644
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -120,5 +120,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index 13cc01e..078aa77 100644
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -111,5 +111,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index a2dc990..2f480d5 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -116,5 +116,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index aa0385b..313abfa 100644
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -142,5 +142,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
index 5d6ff2a..a7db4ac 100644
--- a/src/mainboard/tyan/s2892/romstage.c
+++ b/src/mainboard/tyan/s2892/romstage.c
@@ -123,5 +123,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl);
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index 4f0e552..324a231 100644
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -151,5 +151,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(nodes, ctrl);
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index e4a1c65..9a7e319 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -188,5 +188,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 9c86157..af50237 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -229,8 +229,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
raminit_amdmct(sysinfo);
post_code(0x41);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
}
/**
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 2b6470c..07afee4 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -158,5 +158,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
}
diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index 60dbdf8..030a3e2 100644
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -146,5 +146,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(nodes, ctrl);
- post_cache_as_ram();
}
diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c
index b180ef7..46a3757 100644
--- a/src/mainboard/winent/mb6047/romstage.c
+++ b/src/mainboard/winent/mb6047/romstage.c
@@ -145,5 +145,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram();
}
More information about the coreboot-gerrit
mailing list