[coreboot-gerrit] Patch set updated for coreboot: 9a20a81 superio/fintek: Add initial support for Fintek F71869AD.

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Sun Jan 26 05:16:17 CET 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4784

-gerrit

commit 9a20a811ab2f40c8ddc79ee9f85b1da8618ad642
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Thu Jan 23 22:12:25 2014 +1100

    superio/fintek: Add initial support for Fintek F71869AD.
    
    See gerrit comment for Fintek F71869AD data-sheet.
    
    Change-Id: I41f1ee20517dd179a4dee914ab7f6332739e326e
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/superio/fintek/Kconfig                         |  2 +
 src/superio/fintek/Makefile.inc                    |  1 +
 src/superio/fintek/f71869ad/Makefile.inc           | 22 +++++
 src/superio/fintek/f71869ad/chip.h                 | 32 ++++++++
 src/superio/fintek/f71869ad/f71869ad.h             | 37 +++++++++
 .../fintek/f71869ad/f71869ad_early_serial.c        | 68 ++++++++++++++++
 src/superio/fintek/f71869ad/superio.c              | 95 ++++++++++++++++++++++
 7 files changed, 257 insertions(+)

diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig
index 67d2847..938494a 100644
--- a/src/superio/fintek/Kconfig
+++ b/src/superio/fintek/Kconfig
@@ -23,6 +23,8 @@ config SUPERIO_FINTEK_F71859
 	bool
 config SUPERIO_FINTEK_F71863FG
 	bool
+config SUPERIO_FINTEK_F71869AD
+	bool
 config SUPERIO_FINTEK_F71872
 	bool
 config SUPERIO_FINTEK_F71889
diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc
index 036bb2d..541a893 100644
--- a/src/superio/fintek/Makefile.inc
+++ b/src/superio/fintek/Makefile.inc
@@ -20,6 +20,7 @@
 subdirs-y += f71805f
 subdirs-y += f71859
 subdirs-y += f71863fg
+subdirs-y += f71869ad
 subdirs-y += f71872
 subdirs-y += f71889
 subdirs-y += f81865f
diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc
new file mode 100644
index 0000000..b8550d5
--- /dev/null
+++ b/src/superio/fintek/f71869ad/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_early_serial.c
+ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c
diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h
new file mode 100644
index 0000000..d032dd2
--- /dev/null
+++ b/src/superio/fintek/f71869ad/chip.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F71869AD_CHIPH_H
+#define SUPERIO_FINTEK_F71869AD_CHIPH_H
+
+#include <pc80/keyboard.h>
+#include <device/device.h>
+#include <uart8250.h>
+
+struct superio_fintek_f71869ad_config {
+	struct pc_keyboard keyboard;
+};
+
+#endif /* SUPERIO_FINTEK_F71869AD_CHIPH_H */
diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h
new file mode 100644
index 0000000..abc0260
--- /dev/null
+++ b/src/superio/fintek/f71869ad/f71869ad.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F71869AD_F71869AD_H
+#define SUPERIO_FINTEK_F71869AD_F71869AD_H
+
+/* Logical Device Numbers (LDN). */
+#define F71869AD_FDC    0x00	/* Floppy */
+#define F71869AD_SP1    0x01	/* UART1 */
+#define F71869AD_SP2    0x02	/* UART2 */
+#define F71869AD_PP     0x03	/* Parallel port */
+#define F71869AD_HWM    0x04	/* Hardware monitor */
+#define F71869AD_KBC    0x05	/* PS/2 keyboard and mouse */
+#define F71869AD_GPIO   0x06	/* General Purpose I/O (GPIO) */
+#define F71869AD_BSEL   0x07	/* BSEL */
+#define F71869AD_PME    0x0a	/* Power Management Events (PME) and ACPI */
+
+void f71869ad_enable_serial(device_t dev, u16 iobase);
+
+#endif /* SUPERIO_FINTEK_F71869AD_F71869AD_H */
diff --git a/src/superio/fintek/f71869ad/f71869ad_early_serial.c b/src/superio/fintek/f71869ad/f71869ad_early_serial.c
new file mode 100644
index 0000000..8518400
--- /dev/null
+++ b/src/superio/fintek/f71869ad/f71869ad_early_serial.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Pre-RAM driver for the Fintek F71869AD Super I/O chip.
+ *
+ * Derived from p.34 in vendor data-sheet:
+ *
+ * - default index port : 0x4E
+ * - default data  port : 0x4F
+ *
+ * - enable  configuration : 0x87
+ * - disable configuration : 0xAA
+ *
+ */
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include "f71869ad.h"
+
+/*
+ * Enable configuration: pass entry key '0x87' into index port dev.
+ */
+static void pnp_enter_conf_state(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0x87, port);
+	outb(0x87, port);
+}
+
+/*
+ * Disable configuration: pass exit key '0xAA' into index port dev.
+ */
+static void pnp_exit_conf_state(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0xaa, port);
+}
+
+/*
+ * Bring up early serial debugging output before the RAM is initialized.
+ */
+void f71869ad_enable_serial(device_t dev, u16 iobase)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c
new file mode 100644
index 0000000..c20aff9
--- /dev/null
+++ b/src/superio/fintek/f71869ad/superio.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include <uart8250.h>
+
+#include "chip.h"
+#include "f71869ad.h"
+
+static void f71869ad_init(device_t dev)
+{
+	struct superio_fintek_f71869ad_config *conf = dev->chip_info;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	/* TODO: Might potentially need code for HWM or FDC etc. */
+	case F71869AD_KBC:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		pc_keyboard_init(&conf->keyboard);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_alt_enable,
+	.init             = f71869ad_init,
+	.ops_pnp_mode     = &pnp_conf_mode_8787_aa,
+};
+
+/*
+ * io_info contains the mask 0x07f8. Given 16 register, each 8 bits wide of a
+ * logical device we need a mask of the following form:
+ *
+ *  MSB                 LSB
+ *    v                 v
+ * 0x[15..11][10..3][2..0]
+ *    ------  ^^^^^  ^^^^
+ *    null      |      |
+ *              |      +------ Register index
+ *              |
+ *              +------------- Compare against base address and
+ *                             asserts a chip_select on match.
+ *
+ *  i.e., 0x07F8 = [00000][11111111][000]
+ *
+ * XXX: verify flags and masks are correct.
+ */
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, F71869AD_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71869AD_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71869AD_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71869AD_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71869AD_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, F71869AD_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
+	{ &ops, F71869AD_GPIO, },
+	{ &ops, F71869AD_BSEL,  PNP_IO0, {0x07f8, 0}, },
+	{ &ops, F71869AD_PME, },
+};
+
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_fintek_f71869ad_ops = {
+	CHIP_NAME("Fintek F71869AD Super I/O")
+	.enable_dev = enable_dev
+};



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