[coreboot-gerrit] New patch to review for coreboot: a6d2eb5 baytrail: add audio clock workaround for LPE

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4928

-gerrit

commit a6d2eb58fad0a78fee2731953cfa5114c8a6ef4e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Nov 1 14:36:03 2013 -0500

    baytrail: add audio clock workaround for LPE
    
    Apparently the LPE device needs a 25MHz clock. Provide
    the work around to enable this clock.
    
    BUG=chrome-os-partner:23791
    BRANCH=None
    TEST=Built and booted. Confirmed setting being applied.
    
    Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175493
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/baytrail/Makefile.inc |  1 +
 src/soc/intel/baytrail/lpe.c        | 53 +++++++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index ed2764c..ab4bc89 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -35,6 +35,7 @@ ramstage-y += southcluster.c
 ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
 ramstage-y += sata.c
 ramstage-y += acpi.c
+ramstage-y += lpe.c
 
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
new file mode 100644
index 0000000..e422ff6
--- /dev/null
+++ b/src/soc/intel/baytrail/lpe.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#include <baytrail/iosf.h>
+#include <baytrail/ramstage.h>
+
+static void lpe_init(device_t dev)
+{
+	uint32_t reg;
+
+	/* Work around for Audio Clock. */
+	reg = iosf_ccu_read(PLT_CLK_CTRL_3);
+	reg &= ~0xff;
+	reg |= PLT_CLK_CTRL_25MHZ_FREQ | PLT_CLK_CTRL_SELECT_FREQ;
+	iosf_ccu_write(PLT_CLK_CTRL_3, reg);
+}
+
+static const struct device_operations device_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= NULL,
+	.init			= lpe_init,
+	.enable			= NULL,
+	.scan_bus		= NULL,
+	.ops_pci		= &soc_pci_ops,
+};
+
+static const struct pci_driver southcluster __pci_driver = {
+	.ops		= &device_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.device		= LPE_DEVID,
+};