[coreboot-gerrit] New patch to review for coreboot: 0fc9572 baytrail: Set PMC PTPS register correctly

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5056

-gerrit

commit 0fc9572e8458ee032ae05bc89f33eeb621d35404
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 20 11:58:58 2014 -0800

    baytrail: Set PMC PTPS register correctly
    
    I messed up in setting this register, it should be using Tj_max-Temp
    which in the default case works out to be 90-90=0.
    
    This was apparently heavly throttling the CPU at idle temps.
    
    BUG=chrome-os-partner:17279
    BRANCH=baytrail
    TEST=build and boot on rambi, run graphics_WebGLPerformance test
    
    Change-Id: I4338280cf50db84dc44313d6fb6771ea5af21dad
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/183280
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Commit-Queue: Aaron Durbin <adurbin at chromium.org>
    Tested-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/baytrail/dptf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c
index 184f694..044a807 100644
--- a/src/soc/intel/baytrail/dptf.c
+++ b/src/soc/intel/baytrail/dptf.c
@@ -30,7 +30,7 @@ static const struct reg_script dptf_init_settings[] = {
 	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000),
 	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004),
 	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004),
-	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 90 << 24), /* Tj_max=90C */
+	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000),
 	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029),
 	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029),
 	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029),