[coreboot-gerrit] Patch set updated for coreboot: 598bdd7 baytrail: Fix _CRS to build with new IASL

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4988

-gerrit

commit 598bdd76126cfd2414c5ddac55e376feb7104adf
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Dec 4 18:34:11 2013 -0800

    baytrail: Fix _CRS to build with new IASL
    
    The new IASL is complaining about the PCI memory region not
    having consistent base/end/length values because they are
    placeholder that are fixed up in the method before returning.
    
    Put in some more valid placeholder values to make it happy.
    
    BUG=chromium:311294
    BRANCH=none
    TEST=build and boot with IASL 20130117 on rambi
    
    Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178864
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie at google.com>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/baytrail/acpi/southcluster.asl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 7760869..49349c4 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -160,8 +160,8 @@ Method (_CRS, 0, Serialized)
 		// PCI Memory Region (Top of memory-0xfeafffff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
-				0x00000000, 0x00000000, 0xfeafffff, 0x00000000,
-				0x00000000,,, PMEM)
+				0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
+				0x00100000,,, PMEM)
 
 		// TPM Area (0xfed40000-0xfed44fff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,