[coreboot-gerrit] New patch to review for coreboot: 09bab5d intel/fsp_baytrail: remove sole use of reg_script
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Wed Jul 16 19:48:12 CEST 2014
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6297
-gerrit
commit 09bab5d106a3c28b9468cfd404b17bce251784a9
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Wed Jul 16 19:30:18 2014 +0200
intel/fsp_baytrail: remove sole use of reg_script
It's a baytrail specific API that snuck in, removing
sole non-FSP-baytrail use.
Change-Id: Iece1ec6c97172680c874ef9de7b90a8d5d5357af
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/include/cpu/x86/msr.h | 17 +++++++++++++++++
src/soc/intel/fsp_baytrail/cpu.c | 17 +++++------------
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 40926df..6cba326 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -17,6 +17,8 @@ static void wrmsr(unsigned long index, msr_t msr)
#else
+#include <stdint.h>
+
typedef struct msr_struct
{
unsigned lo;
@@ -59,6 +61,21 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms
);
}
+static inline void rmw_msr(unsigned index, u64 mask, u64 value)
+{
+ msr_t tmp = rdmsr(index);
+ tmp.lo &= mask;
+ tmp.hi &= mask >> 32;
+ tmp.lo |= value;
+ tmp.hi |= value >> 32;
+ wrmsr(index, tmp);
+}
+
+static inline void or_msr(unsigned index, u64 value)
+{
+ rmw_msr(index, ~0, value);
+}
+
#endif /* __ROMCC__ */
#endif /* CPU_X86_MSR_H */
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index f260880..52c1020 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -29,7 +29,6 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
-#include <reg_script.h>
#include <baytrail/msr.h>
#include <baytrail/pattrs.h>
@@ -58,16 +57,6 @@ static int adjust_apic_id(int index, int apic_id)
return 2 * index;
}
-/* Core level MSRs */
-const struct reg_script core_msr_script[] = {
- /* Dynamic L2 shrink enable and threshold */
- REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),
- /* Disable C1E */
- REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
- REG_MSR_OR(MSR_POWER_MISC, 0x44),
- REG_SCRIPT_END
-};
-
void baytrail_init_cpus(device_t dev)
{
struct bus *cpu_bus = dev->link_list;
@@ -103,7 +92,11 @@ static void baytrail_core_init(device_t cpu)
enable_turbo();
/* Set core MSRs */
- reg_script_run(core_msr_script);
+ /* Dynamic L2 shrink enable and threshold */
+ rmw_msr(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),
+ /* Disable C1E */
+ rmw_msr(MSR_POWER_CTL, ~0x2, 0),
+ or_msr(MSR_POWER_MISC, 0x44),
/* Set this core to max frequency ratio */
set_max_freq();
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