[coreboot-gerrit] New patch to review for coreboot: d4fd4d6 amd/dinar & torpedo: Remove a trailing whitespace
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Tue Jul 22 18:59:39 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6322
-gerrit
commit d4fd4d6d2652e6509894935fe044e77da6dcd7dd
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Tue Jul 22 18:59:55 2014 +0200
amd/dinar & torpedo: Remove a trailing whitespace
Change-Id: I4ac14c4f511eb6d56480e5167ce98b861cbed775
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/amd/dinar/agesawrapper.h | 6 +++---
src/mainboard/amd/dinar/buildOpts.c | 18 +++++++++---------
src/mainboard/amd/dinar/platform_cfg.h | 4 ++--
src/mainboard/amd/torpedo/agesawrapper.h | 6 +++---
4 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h
index 70cf4f6..e4cbfa9 100644
--- a/src/mainboard/amd/dinar/agesawrapper.h
+++ b/src/mainboard/amd/dinar/agesawrapper.h
@@ -57,9 +57,9 @@
#define R_SB_ACPI_PM_CONTROL 0x04
#define R_SB_ACPI_EVENT_STATUS 0x20
#define R_SB_ACPI_EVENT_ENABLE 0x24
-#define B_PWR_BTN_STATUS BIT8
-#define B_WAKEUP_STATUS BIT15
-#define B_SCI_EN BIT0
+#define B_PWR_BTN_STATUS BIT8
+#define B_WAKEUP_STATUS BIT15
+#define B_SCI_EN BIT0
#define SB_PM_INDEX_PORT 0xCD6
#define SB_PM_DATA_PORT 0xCD7
#define SB_PMIOA_REG24 0x24 // AcpiMmioEn
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 958764e..ffbec1f 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -42,15 +42,15 @@
* coreboot enable -Wundef option, so we should make sure we have all contanstand defined
*/
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h
index 94f4f0c..0aa3743 100644
--- a/src/mainboard/amd/dinar/platform_cfg.h
+++ b/src/mainboard/amd/dinar/platform_cfg.h
@@ -31,13 +31,13 @@
* Enable check for PCIe endpoint to be ready for PCI enumeration.
*
*/
-//#define EPREADY_WORKAROUND_DISABLED
+//#define EPREADY_WORKAROUND_DISABLED
/**
* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
*
*/
-#define IOMMU_SUPPORT_DISABLE //TODO: enable it
+#define IOMMU_SUPPORT_DISABLE //TODO: enable it
/**
* Disable server PCIe hotplug support.
diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h
index 5ca4cfa..1ec933c 100644
--- a/src/mainboard/amd/torpedo/agesawrapper.h
+++ b/src/mainboard/amd/torpedo/agesawrapper.h
@@ -56,9 +56,9 @@
#define R_SB_ACPI_PM_CONTROL 0x04
#define R_SB_ACPI_EVENT_STATUS 0x20
#define R_SB_ACPI_EVENT_ENABLE 0x24
-#define B_PWR_BTN_STATUS BIT8
-#define B_WAKEUP_STATUS BIT15
-#define B_SCI_EN BIT0
+#define B_PWR_BTN_STATUS BIT8
+#define B_WAKEUP_STATUS BIT15
+#define B_SCI_EN BIT0
#define SB_PM_INDEX_PORT 0xCD6
#define SB_PM_DATA_PORT 0xCD7
#define SB_PMIOA_REG24 0x24 // AcpiMmioEn
More information about the coreboot-gerrit
mailing list