[coreboot-gerrit] New patch to review for coreboot: 99d552c southbridge/intel/lynxpoint: Remove a trailing whitespace
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Tue Jul 22 19:53:27 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6342
-gerrit
commit 99d552cf2085ff27e8d5405e0697d97823f03909
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Tue Jul 22 19:53:54 2014 +0200
southbridge/intel/lynxpoint: Remove a trailing whitespace
Change-Id: If6fdfbcde9e5b6d3167f082b55cc0c6617c5d6a0
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/southbridge/intel/lynxpoint/hda_verb.h | 6 +-
src/southbridge/intel/lynxpoint/me.h | 202 ++++++++---------
src/southbridge/intel/lynxpoint/pch.h | 338 ++++++++++++++---------------
3 files changed, 273 insertions(+), 273 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h
index 8b3d27e..b0e9d9f 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.h
+++ b/src/southbridge/intel/lynxpoint/hda_verb.h
@@ -22,13 +22,13 @@
#define HDA_GCAP_REG 0x00
#define HDA_GCTL_REG 0x08
-#define HDA_GCTL_CRST (1 << 0)
+#define HDA_GCTL_CRST (1 << 0)
#define HDA_STATESTS_REG 0x0e
#define HDA_IC_REG 0x60
#define HDA_IR_REG 0x64
#define HDA_ICII_REG 0x68
-#define HDA_ICII_BUSY (1 << 0)
-#define HDA_ICII_VALID (1 << 1)
+#define HDA_ICII_BUSY (1 << 0)
+#define HDA_ICII_VALID (1 << 1)
int hda_codec_detect(u32 base);
int hda_codec_write(u32 base, u32 size, const u32 *data);
diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
index a72778b..c63c866 100644
--- a/src/southbridge/intel/lynxpoint/me.h
+++ b/src/southbridge/intel/lynxpoint/me.h
@@ -34,37 +34,37 @@
#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
#define PCI_ME_HFS 0x40
-#define ME_HFS_CWS_RESET 0
-#define ME_HFS_CWS_INIT 1
-#define ME_HFS_CWS_REC 2
-#define ME_HFS_CWS_NORMAL 5
-#define ME_HFS_CWS_WAIT 6
-#define ME_HFS_CWS_TRANS 7
-#define ME_HFS_CWS_INVALID 8
-#define ME_HFS_STATE_PREBOOT 0
-#define ME_HFS_STATE_M0_UMA 1
-#define ME_HFS_STATE_M3 4
-#define ME_HFS_STATE_M0 5
-#define ME_HFS_STATE_BRINGUP 6
-#define ME_HFS_STATE_ERROR 7
-#define ME_HFS_ERROR_NONE 0
-#define ME_HFS_ERROR_UNCAT 1
-#define ME_HFS_ERROR_IMAGE 3
-#define ME_HFS_ERROR_DEBUG 4
-#define ME_HFS_MODE_NORMAL 0
-#define ME_HFS_MODE_DEBUG 2
-#define ME_HFS_MODE_DIS 3
-#define ME_HFS_MODE_OVER_JMPR 4
-#define ME_HFS_MODE_OVER_MEI 5
-#define ME_HFS_BIOS_DRAM_ACK 1
-#define ME_HFS_ACK_NO_DID 0
-#define ME_HFS_ACK_RESET 1
-#define ME_HFS_ACK_PWR_CYCLE 2
-#define ME_HFS_ACK_S3 3
-#define ME_HFS_ACK_S4 4
-#define ME_HFS_ACK_S5 5
-#define ME_HFS_ACK_GBL_RESET 6
-#define ME_HFS_ACK_CONTINUE 7
+#define ME_HFS_CWS_RESET 0
+#define ME_HFS_CWS_INIT 1
+#define ME_HFS_CWS_REC 2
+#define ME_HFS_CWS_NORMAL 5
+#define ME_HFS_CWS_WAIT 6
+#define ME_HFS_CWS_TRANS 7
+#define ME_HFS_CWS_INVALID 8
+#define ME_HFS_STATE_PREBOOT 0
+#define ME_HFS_STATE_M0_UMA 1
+#define ME_HFS_STATE_M3 4
+#define ME_HFS_STATE_M0 5
+#define ME_HFS_STATE_BRINGUP 6
+#define ME_HFS_STATE_ERROR 7
+#define ME_HFS_ERROR_NONE 0
+#define ME_HFS_ERROR_UNCAT 1
+#define ME_HFS_ERROR_IMAGE 3
+#define ME_HFS_ERROR_DEBUG 4
+#define ME_HFS_MODE_NORMAL 0
+#define ME_HFS_MODE_DEBUG 2
+#define ME_HFS_MODE_DIS 3
+#define ME_HFS_MODE_OVER_JMPR 4
+#define ME_HFS_MODE_OVER_MEI 5
+#define ME_HFS_BIOS_DRAM_ACK 1
+#define ME_HFS_ACK_NO_DID 0
+#define ME_HFS_ACK_RESET 1
+#define ME_HFS_ACK_PWR_CYCLE 2
+#define ME_HFS_ACK_S3 3
+#define ME_HFS_ACK_S4 4
+#define ME_HFS_ACK_S5 5
+#define ME_HFS_ACK_GBL_RESET 6
+#define ME_HFS_ACK_CONTINUE 7
struct me_hfs {
u32 working_state: 4;
@@ -93,11 +93,11 @@ struct me_uma {
} __attribute__ ((packed));
#define PCI_ME_H_GS 0x4c
-#define ME_INIT_DONE 1
-#define ME_INIT_STATUS_SUCCESS 0
-#define ME_INIT_STATUS_NOMEM 1
-#define ME_INIT_STATUS_ERROR 2
-#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
+#define ME_INIT_DONE 1
+#define ME_INIT_STATUS_SUCCESS 0
+#define ME_INIT_STATUS_NOMEM 1
+#define ME_INIT_STATUS_ERROR 2
+#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
struct me_did {
u32 uma_base: 16;
@@ -113,73 +113,73 @@ struct me_did {
*/
#define PCI_ME_HFS2 0x48
/* Infrastructure Progress Values */
-#define ME_HFS2_PHASE_ROM 0
-#define ME_HFS2_PHASE_BUP 1
-#define ME_HFS2_PHASE_UKERNEL 2
-#define ME_HFS2_PHASE_POLICY 3
-#define ME_HFS2_PHASE_MODULE_LOAD 4
-#define ME_HFS2_PHASE_UNKNOWN 5
-#define ME_HFS2_PHASE_HOST_COMM 6
+#define ME_HFS2_PHASE_ROM 0
+#define ME_HFS2_PHASE_BUP 1
+#define ME_HFS2_PHASE_UKERNEL 2
+#define ME_HFS2_PHASE_POLICY 3
+#define ME_HFS2_PHASE_MODULE_LOAD 4
+#define ME_HFS2_PHASE_UNKNOWN 5
+#define ME_HFS2_PHASE_HOST_COMM 6
/* Current State - Based on Infra Progress values. */
/* ROM State */
-#define ME_HFS2_STATE_ROM_BEGIN 0
-#define ME_HFS2_STATE_ROM_DISABLE 6
+#define ME_HFS2_STATE_ROM_BEGIN 0
+#define ME_HFS2_STATE_ROM_DISABLE 6
/* BUP State */
-#define ME_HFS2_STATE_BUP_INIT 0
-#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
-#define ME_HFS2_STATE_BUP_FLOW_DET 4
-#define ME_HFS2_STATE_BUP_VSCC_ERR 8
-#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
-#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
-#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
-#define ME_HFS2_STATE_BUP_M3 0x11
-#define ME_HFS2_STATE_BUP_M0 0x12
-#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
-#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
-#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
-#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
-#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c
-#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f
-#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
-#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
-#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
-#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
-#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
-#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
-#define ME_HFS2_STATE_BUP_M0_CLK 0x26
-#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
-#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28
-#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
+#define ME_HFS2_STATE_BUP_INIT 0
+#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
+#define ME_HFS2_STATE_BUP_FLOW_DET 4
+#define ME_HFS2_STATE_BUP_VSCC_ERR 8
+#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
+#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
+#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
+#define ME_HFS2_STATE_BUP_M3 0x11
+#define ME_HFS2_STATE_BUP_M0 0x12
+#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
+#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
+#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
+#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
+#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c
+#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f
+#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
+#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
+#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
+#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
+#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
+#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
+#define ME_HFS2_STATE_BUP_M0_CLK 0x26
+#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
+#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28
+#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
/* Policy Module State */
-#define ME_HFS2_STATE_POLICY_ENTRY 0
-#define ME_HFS2_STATE_POLICY_RCVD_S3 3
-#define ME_HFS2_STATE_POLICY_RCVD_S4 4
-#define ME_HFS2_STATE_POLICY_RCVD_S5 5
-#define ME_HFS2_STATE_POLICY_RCVD_UPD 6
-#define ME_HFS2_STATE_POLICY_RCVD_PCR 7
-#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8
-#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
-#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
-#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb
-#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
-#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
-#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe
-#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
-#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
+#define ME_HFS2_STATE_POLICY_ENTRY 0
+#define ME_HFS2_STATE_POLICY_RCVD_S3 3
+#define ME_HFS2_STATE_POLICY_RCVD_S4 4
+#define ME_HFS2_STATE_POLICY_RCVD_S5 5
+#define ME_HFS2_STATE_POLICY_RCVD_UPD 6
+#define ME_HFS2_STATE_POLICY_RCVD_PCR 7
+#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8
+#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
+#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
+#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb
+#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
+#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
+#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe
+#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
+#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
/* Current PM Event Values */
-#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
-#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
-#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
-#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
-#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
-#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
-#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
-#define ME_HFS2_PMEVENT_S0MO_SXM3 7
-#define ME_HFS2_PMEVENT_SXM3_S0M0 8
-#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
-#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
-#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
-#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
+#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
+#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
+#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
+#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
+#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
+#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
+#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
+#define ME_HFS2_PMEVENT_S0MO_SXM3 7
+#define ME_HFS2_PMEVENT_SXM3_S0M0 8
+#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
+#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
+#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
+#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
struct me_hfs2 {
u32 bist_in_progress: 1;
@@ -199,11 +199,11 @@ struct me_hfs2 {
} __attribute__ ((packed));
#define PCI_ME_H_GS2 0x70
-#define PCI_ME_MBP_GIVE_UP 0x01
+#define PCI_ME_MBP_GIVE_UP 0x01
#define PCI_ME_HERES 0xbc
-#define PCI_ME_EXT_SHA1 0x00
-#define PCI_ME_EXT_SHA256 0x02
+#define PCI_ME_EXT_SHA1 0x00
+#define PCI_ME_EXT_SHA256 0x02
#define PCI_ME_HER(x) (0xc0+(4*(x)))
struct me_heres {
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 9b5cb6f..2614126 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -98,13 +98,13 @@ void usb_xhci_route_all(void);
/* State Machine configuration. */
#define RCBA_REG_SIZE_MASK 0x8000
-#define RCBA_REG_SIZE_16 0x8000
-#define RCBA_REG_SIZE_32 0x0000
+#define RCBA_REG_SIZE_16 0x8000
+#define RCBA_REG_SIZE_32 0x0000
#define RCBA_COMMAND_MASK 0x000f
-#define RCBA_COMMAND_SET 0x0001
-#define RCBA_COMMAND_READ 0x0002
-#define RCBA_COMMAND_RMW 0x0003
-#define RCBA_COMMAND_END 0x0007
+#define RCBA_COMMAND_SET 0x0001
+#define RCBA_COMMAND_READ 0x0002
+#define RCBA_COMMAND_RMW 0x0003
+#define RCBA_COMMAND_END 0x0007
#define RCBA_ENCODE_COMMAND(command_, reg_, mask_, or_value_) \
{ .command = command_, \
@@ -231,13 +231,13 @@ void pch_enable_lpc(void);
#define SECSTS 0x1e
#define INTR 0x3c
#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
/* Power Management Control and Status */
#define PCH_PCS 0x84
-#define PCH_PCS_PS_D3HOT 3
+#define PCH_PCS_PS_D3HOT 3
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
@@ -253,8 +253,8 @@ void pch_enable_lpc(void);
#define GEN_PMCON_2 0xa2
#define GEN_PMCON_3 0xa4
#define PMIR 0xac
-#define PMIR_CF9LOCK (1 << 31)
-#define PMIR_CF9GR (1 << 20)
+#define PMIR_CF9LOCK (1 << 31)
+#define PMIR_CF9GR (1 << 20)
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)
@@ -263,7 +263,7 @@ void pch_enable_lpc(void);
#define PMBASE 0x40
#define ACPI_CNTL 0x44
-#define ACPI_EN (1 << 7)
+#define ACPI_EN (1 << 7)
#define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
@@ -280,16 +280,16 @@ void pch_enable_lpc(void);
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
#define LPC_EN 0x82 /* LPC IF Enables Register */
-#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
-#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
-#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
-#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
-#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
-#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
-#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
-#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
-#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
-#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
@@ -302,48 +302,48 @@ void pch_enable_lpc(void);
#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
#define INTR_LN 0x3c
#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
-#define IDE_DECODE_ENABLE (1 << 15)
-#define IDE_SITRE (1 << 14)
-#define IDE_ISP_5_CLOCKS (0 << 12)
-#define IDE_ISP_4_CLOCKS (1 << 12)
-#define IDE_ISP_3_CLOCKS (2 << 12)
-#define IDE_RCT_4_CLOCKS (0 << 8)
-#define IDE_RCT_3_CLOCKS (1 << 8)
-#define IDE_RCT_2_CLOCKS (2 << 8)
-#define IDE_RCT_1_CLOCKS (3 << 8)
-#define IDE_DTE1 (1 << 7)
-#define IDE_PPE1 (1 << 6)
-#define IDE_IE1 (1 << 5)
-#define IDE_TIME1 (1 << 4)
-#define IDE_DTE0 (1 << 3)
-#define IDE_PPE0 (1 << 2)
-#define IDE_IE0 (1 << 1)
-#define IDE_TIME0 (1 << 0)
+#define IDE_DECODE_ENABLE (1 << 15)
+#define IDE_SITRE (1 << 14)
+#define IDE_ISP_5_CLOCKS (0 << 12)
+#define IDE_ISP_4_CLOCKS (1 << 12)
+#define IDE_ISP_3_CLOCKS (2 << 12)
+#define IDE_RCT_4_CLOCKS (0 << 8)
+#define IDE_RCT_3_CLOCKS (1 << 8)
+#define IDE_RCT_2_CLOCKS (2 << 8)
+#define IDE_RCT_1_CLOCKS (3 << 8)
+#define IDE_DTE1 (1 << 7)
+#define IDE_PPE1 (1 << 6)
+#define IDE_IE1 (1 << 5)
+#define IDE_TIME1 (1 << 4)
+#define IDE_DTE0 (1 << 3)
+#define IDE_PPE0 (1 << 2)
+#define IDE_IE0 (1 << 1)
+#define IDE_TIME0 (1 << 0)
#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
-#define IDE_SSDE1 (1 << 3)
-#define IDE_SSDE0 (1 << 2)
-#define IDE_PSDE1 (1 << 1)
-#define IDE_PSDE0 (1 << 0)
+#define IDE_SSDE1 (1 << 3)
+#define IDE_SSDE0 (1 << 2)
+#define IDE_PSDE1 (1 << 1)
+#define IDE_PSDE0 (1 << 0)
#define IDE_SDMA_TIM 0x4a
#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
-#define SIG_MODE_SEC_NORMAL (0 << 18)
-#define SIG_MODE_SEC_TRISTATE (1 << 18)
-#define SIG_MODE_SEC_DRIVELOW (2 << 18)
-#define SIG_MODE_PRI_NORMAL (0 << 16)
-#define SIG_MODE_PRI_TRISTATE (1 << 16)
-#define SIG_MODE_PRI_DRIVELOW (2 << 16)
-#define FAST_SCB1 (1 << 15)
-#define FAST_SCB0 (1 << 14)
-#define FAST_PCB1 (1 << 13)
-#define FAST_PCB0 (1 << 12)
-#define SCB1 (1 << 3)
-#define SCB0 (1 << 2)
-#define PCB1 (1 << 1)
-#define PCB0 (1 << 0)
+#define SIG_MODE_SEC_NORMAL (0 << 18)
+#define SIG_MODE_SEC_TRISTATE (1 << 18)
+#define SIG_MODE_SEC_DRIVELOW (2 << 18)
+#define SIG_MODE_PRI_NORMAL (0 << 16)
+#define SIG_MODE_PRI_TRISTATE (1 << 16)
+#define SIG_MODE_PRI_DRIVELOW (2 << 16)
+#define FAST_SCB1 (1 << 15)
+#define FAST_SCB0 (1 << 14)
+#define FAST_PCB1 (1 << 13)
+#define FAST_PCB0 (1 << 12)
+#define SCB1 (1 << 3)
+#define SCB0 (1 << 2)
+#define PCB1 (1 << 1)
+#define PCB0 (1 << 0)
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
@@ -363,62 +363,62 @@ void pch_enable_lpc(void);
/* EHCI PCI Registers */
#define EHCI_PWR_CTL_STS 0x54
-#define PWR_CTL_SET_MASK 0x3
-#define PWR_CTL_SET_D0 0x0
-#define PWR_CTL_SET_D3 0x3
-#define PWR_CTL_ENABLE_PME (1 << 8)
-#define PWR_CTL_STATUS_PME (1 << 15)
+#define PWR_CTL_SET_MASK 0x3
+#define PWR_CTL_SET_D0 0x0
+#define PWR_CTL_SET_D3 0x3
+#define PWR_CTL_ENABLE_PME (1 << 8)
+#define PWR_CTL_STATUS_PME (1 << 15)
/* EHCI Memory Registers */
#define EHCI_USB_CMD 0x20
-#define EHCI_USB_CMD_RUN (1 << 0)
-#define EHCI_USB_CMD_PSE (1 << 4)
-#define EHCI_USB_CMD_ASE (1 << 5)
+#define EHCI_USB_CMD_RUN (1 << 0)
+#define EHCI_USB_CMD_PSE (1 << 4)
+#define EHCI_USB_CMD_ASE (1 << 5)
#define EHCI_PORTSC(port) (0x64 + (port * 4))
-#define EHCI_PORTSC_ENABLED (1 << 2)
-#define EHCI_PORTSC_SUSPEND (1 << 7)
+#define EHCI_PORTSC_ENABLED (1 << 2)
+#define EHCI_PORTSC_SUSPEND (1 << 7)
/* XHCI PCI Registers */
#define XHCI_PWR_CTL_STS 0x74
#define XHCI_USB2PR 0xd0
#define XHCI_USB2PRM 0xd4
-#define XHCI_USB2PR_HCSEL 0x7fff
+#define XHCI_USB2PR_HCSEL 0x7fff
#define XHCI_USB3PR 0xd8
-#define XHCI_USB3PR_SSEN 0x3f
+#define XHCI_USB3PR_SSEN 0x3f
#define XHCI_USB3PRM 0xdc
#define XHCI_USB3FUS 0xe0
-#define XHCI_USB3FUS_SS_MASK 3
-#define XHCI_USB3FUS_SS_SHIFT 3
+#define XHCI_USB3FUS_SS_MASK 3
+#define XHCI_USB3FUS_SS_SHIFT 3
#define XHCI_USB3PDO 0xe8
/* XHCI Memory Registers */
#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + (port * 0x10))
-#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
-#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
-#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
-#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
-#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
-#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
-#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
-#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
-#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
-#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
-#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
-#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
-#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
+#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
+#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
+#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
+#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
+#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
+#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
+#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
+#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
+#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
+#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
+#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
+#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
+#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
/* Serial IO IOBP Registers */
#define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */
-#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5)
-#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4)
+#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5)
+#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4)
#define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */
-#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13)
+#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13)
#define SIO_IOBP_GPIODF 0xcb000154
-#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4)
-#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3)
-#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2)
-#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1)
-#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0)
+#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4)
+#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3)
+#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2)
+#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1)
+#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0)
#define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */
#define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */
#define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */
@@ -428,11 +428,11 @@ void pch_enable_lpc(void);
#define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */
#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8))
/* PORTCTRL 2-8 have the same layout */
-#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21)
-#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20)
-#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18)
-#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2)
-#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1)
+#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21)
+#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20)
+#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18)
+#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2)
+#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1)
#define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */
#define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */
#define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */
@@ -441,7 +441,7 @@ void pch_enable_lpc(void);
#define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */
#define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */
#define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */
-#define SIO_IOBP_FUNCDIS_DIS (1 << 8)
+#define SIO_IOBP_FUNCDIS_DIS (1 << 8)
/* Serial IO Devices */
#define SIO_ID_SDMA 0 /* D21:F0 */
@@ -454,19 +454,19 @@ void pch_enable_lpc(void);
#define SIO_ID_SDIO 7 /* D23:F0 */
#define SIO_REG_PPR_CLOCK 0x800
-#define SIO_REG_PPR_CLOCK_EN (1 << 0)
+#define SIO_REG_PPR_CLOCK_EN (1 << 0)
#define SIO_REG_PPR_RST 0x804
-#define SIO_REG_PPR_RST_ASSERT 0x3
+#define SIO_REG_PPR_RST_ASSERT 0x3
#define SIO_REG_PPR_GEN 0x808
-#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2)
-#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3)
-#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3)
+#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2)
+#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3)
+#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3)
#define SIO_REG_AUTO_LTR 0x814
#define SIO_REG_SDIO_PPR_GEN 0x1008
#define SIO_REG_SDIO_PPR_SW_LTR 0x1010
#define SIO_REG_SDIO_PPR_CMD12 0x3c
-#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30)
+#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30)
#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
@@ -601,13 +601,13 @@ void pch_enable_lpc(void);
#define IOBPIRI 0x2330
#define IOBPD 0x2334
#define IOBPS 0x2338
-#define IOBPS_READY 0x0001
-#define IOBPS_TX_MASK 0x0006
-#define IOBPS_MASK 0xff00
-#define IOBPS_READ 0x0600
-#define IOBPS_WRITE 0x0700
+#define IOBPS_READY 0x0001
+#define IOBPS_TX_MASK 0x0006
+#define IOBPS_MASK 0xff00
+#define IOBPS_READ 0x0600
+#define IOBPS_WRITE 0x0700
#define IOBPU 0x233a
-#define IOBPU_MAGIC 0xf000
+#define IOBPU_MAGIC 0xf000
#define D31IP 0x3100 /* 32bit */
#define D31IP_TTIP 24 /* Thermal Throttle Pin */
@@ -696,31 +696,31 @@ void pch_enable_lpc(void);
/* ICH7 PMBASE */
#define PM1_STS 0x00
-#define WAK_STS (1 << 15)
-#define PCIEXPWAK_STS (1 << 14)
-#define PRBTNOR_STS (1 << 11)
-#define RTC_STS (1 << 10)
-#define PWRBTN_STS (1 << 8)
-#define GBL_STS (1 << 5)
-#define BM_STS (1 << 4)
-#define TMROF_STS (1 << 0)
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
#define PM1_EN 0x02
-#define PCIEXPWAK_DIS (1 << 14)
-#define RTC_EN (1 << 10)
-#define PWRBTN_EN (1 << 8)
-#define GBL_EN (1 << 5)
-#define TMROF_EN (1 << 0)
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
-#define GBL_RLS (1 << 2)
-#define BM_RLD (1 << 1)
-#define SCI_EN (1 << 0)
+#define SLP_EN (1 << 13)
+#define SLP_TYP (7 << 10)
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
#define PM1_TMR 0x08
#define PROC_CNT 0x10
#define LV2 0x14
@@ -728,35 +728,35 @@ void pch_enable_lpc(void);
#define LV4 0x16
#define PM2_CNT 0x50 // mobile only
#define GPE0_STS 0x20
-#define PME_B0_STS (1 << 13)
-#define PME_STS (1 << 11)
-#define BATLOW_STS (1 << 10)
-#define PCI_EXP_STS (1 << 9)
-#define RI_STS (1 << 8)
-#define SMB_WAK_STS (1 << 7)
-#define TCOSCI_STS (1 << 6)
-#define SWGPE_STS (1 << 2)
-#define HOT_PLUG_STS (1 << 1)
+#define PME_B0_STS (1 << 13)
+#define PME_STS (1 << 11)
+#define BATLOW_STS (1 << 10)
+#define PCI_EXP_STS (1 << 9)
+#define RI_STS (1 << 8)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
#define GPE0_STS_2 0x24
#define GPE0_EN 0x28
-#define PME_B0_EN (1 << 13)
-#define PME_EN (1 << 11)
-#define TCOSCI_EN (1 << 6)
+#define PME_B0_EN (1 << 13)
+#define PME_EN (1 << 11)
+#define TCOSCI_EN (1 << 6)
#define GPE0_EN_2 0x2c
#define SMI_EN 0x30
-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define MCSMI_EN (1 << 11) // Trap microcontroller range access
-#define BIOS_RLS (1 << 7) // asserts SCI on bit set
-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
-#define EOS (1 << 1) // End of SMI (deassert SMI#)
-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
+#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
+#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define MCSMI_EN (1 << 11) // Trap microcontroller range access
+#define BIOS_RLS (1 << 7) // asserts SCI on bit set
+#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
+#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
+#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
+#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
+#define EOS (1 << 1) // End of SMI (deassert SMI#)
+#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
#define SMI_STS 0x34
#define ALT_GP_SMI_EN 0x38
#define ALT_GP_SMI_STS 0x3a
@@ -765,7 +765,7 @@ void pch_enable_lpc(void);
#define SS_CNT 0x50
#define C3_RES 0x54
#define TCO1_STS 0x64
-#define DMISCI_STS (1 << 9)
+#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
#define ALT_GP_SMI_EN2 0x5c
#define ALT_GP_SMI_STS2 0x5e
@@ -832,16 +832,16 @@ void pch_enable_lpc(void);
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */
-#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
-#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
-#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
-#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
+#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
+#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
+#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
+#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */
-#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
-#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
-#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
-#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
-#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
+#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
+#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
+#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
+#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
+#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
#define SPIBAR_FADDR 0x3808 /* SPI flash address */
#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
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