[coreboot-gerrit] Patch set updated for coreboot: a47b41e southbridge/amd: Remove a trailing whitespace
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Tue Jul 22 23:12:20 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6334
-gerrit
commit a47b41e9c32abe422e290589f00c4fd8fadc51e4
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Tue Jul 22 23:12:38 2014 +0200
southbridge/amd: Remove a trailing whitespace
Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/southbridge/amd/agesa/hudson/early_setup.c | 4 +-
src/southbridge/amd/agesa/hudson/smbus.c | 4 +-
src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 8 +--
src/southbridge/amd/cimx/sb900/SbPlatform.h | 76 +++++++++++++-------------
src/southbridge/amd/sb800/early_setup.c | 4 +-
src/southbridge/amd/sb800/smbus.c | 4 +-
6 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index d8fdc27..039df20 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef _HUDSON_EARLY_SETUP_C_
-#define _HUDSON_EARLY_SETUP_C_
+#ifndef _HUDSON_EARLY_SETUP_C_
+#define _HUDSON_EARLY_SETUP_C_
#include <stdint.h>
#include <arch/io.h>
diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c
index 0c04158..519c85d 100644
--- a/src/southbridge/amd/agesa/hudson/smbus.c
+++ b/src/southbridge/amd/agesa/hudson/smbus.c
@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef _HUDSON_SMBUS_C_
-#define _HUDSON_SMBUS_C_
+#ifndef _HUDSON_SMBUS_C_
+#define _HUDSON_SMBUS_C_
#include <io.h>
#include <stdint.h>
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index ea3f719..b26d429 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -21,8 +21,8 @@
*
*/
-#ifndef _AMD_SBPLATFORM_H_
-#define _AMD_SBPLATFORM_H_
+#ifndef _AMD_SBPLATFORM_H_
+#define _AMD_SBPLATFORM_H_
#include <stddef.h>
@@ -162,7 +162,7 @@ typedef union _PCI_ADDR {
#include <spi-generic.h>
#endif
-#define BIOSRAM_INDEX 0xcd4
-#define BIOSRAM_DATA 0xcd5
+#define BIOSRAM_INDEX 0xcd4
+#define BIOSRAM_DATA 0xcd5
#endif // _AMD_SBPLATFORM_H_
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 176ad87..6371bcd 100644
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -21,8 +21,8 @@
*
*/
-#ifndef _AMD_SBPLATFORM_H_
-#define _AMD_SBPLATFORM_H_
+#ifndef _AMD_SBPLATFORM_H_
+#define _AMD_SBPLATFORM_H_
#include <stddef.h>
@@ -107,48 +107,48 @@ typedef union _PCI_ADDR {
* FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
* FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
*/
-#define SB_CIMx_PARAMETER 0x02
+#define SB_CIMx_PARAMETER 0x02
// Generic
-#define cimSpreadSpectrumDefault TRUE
+#define cimSpreadSpectrumDefault TRUE
#define cimSpreadSpectrumTypeDefault 0x00 // Normal
-#define cimHpetTimerDefault TRUE
-#define cimHpetMsiDisDefault FALSE // Enable
-#define cimIrConfigDefault 0x00 // Disable
-#define cimSpiFastReadEnableDefault 0x00 // Disable
-#define cimSpiFastReadSpeedDefault 0x00 // NULL
+#define cimHpetTimerDefault TRUE
+#define cimHpetMsiDisDefault FALSE // Enable
+#define cimIrConfigDefault 0x00 // Disable
+#define cimSpiFastReadEnableDefault 0x00 // Disable
+#define cimSpiFastReadSpeedDefault 0x00 // NULL
// GPP/AB Controller
-#define cimNbSbGen2Default TRUE
-#define cimAlinkPhyPllPowerDownDefault TRUE
-#define cimResetCpuOnSyncFloodDefault TRUE
-#define cimGppGen2Default FALSE
-#define cimGppMemWrImproveDefault TRUE
-#define cimGppPortAspmDefault FALSE
-#define cimGppLaneReversalDefault FALSE
-#define cimGppPhyPllPowerDownDefault TRUE
+#define cimNbSbGen2Default TRUE
+#define cimAlinkPhyPllPowerDownDefault TRUE
+#define cimResetCpuOnSyncFloodDefault TRUE
+#define cimGppGen2Default FALSE
+#define cimGppMemWrImproveDefault TRUE
+#define cimGppPortAspmDefault FALSE
+#define cimGppLaneReversalDefault FALSE
+#define cimGppPhyPllPowerDownDefault TRUE
// USB Controller
-#define cimUsbPhyPowerDownDefault FALSE
+#define cimUsbPhyPowerDownDefault FALSE
// GEC Controller
-#define cimSBGecDebugBusDefault FALSE
-#define cimSBGecPwrDefault 0x03
+#define cimSBGecDebugBusDefault FALSE
+#define cimSBGecPwrDefault 0x03
// Sata Controller
-#define cimSataSetMaxGen2Default 0x00
-#define cimSATARefClkSelDefault 0x10
-#define cimSATARefDivSelDefault 0x80
-#define cimSataAggrLinkPmCapDefault TRUE
-#define cimSataPortMultCapDefault TRUE
-#define cimSataPscCapDefault 0x00 // Enable
-#define cimSataSscCapDefault 0x00 // Enable
-#define cimSataFisBasedSwitchingDefault FALSE
-#define cimSataCccSupportDefault FALSE
-#define cimSataClkAutoOffDefault FALSE
-#define cimNativepciesupportDefault FALSE
+#define cimSataSetMaxGen2Default 0x00
+#define cimSATARefClkSelDefault 0x10
+#define cimSATARefDivSelDefault 0x80
+#define cimSataAggrLinkPmCapDefault TRUE
+#define cimSataPortMultCapDefault TRUE
+#define cimSataPscCapDefault 0x00 // Enable
+#define cimSataSscCapDefault 0x00 // Enable
+#define cimSataFisBasedSwitchingDefault FALSE
+#define cimSataCccSupportDefault FALSE
+#define cimSataClkAutoOffDefault FALSE
+#define cimNativepciesupportDefault FALSE
// Fusion Related
-#define cimAcDcMsgDefault FALSE
-#define cimTimerTickTrackDefault FALSE
-#define cimClockInterruptTagDefault FALSE
-#define cimOhciTrafficHandingDefault FALSE
-#define cimEhciTrafficHandingDefault FALSE
-#define cimFusionMsgCMultiCoreDefault FALSE
-#define cimFusionMsgCStageDefault FALSE
+#define cimAcDcMsgDefault FALSE
+#define cimTimerTickTrackDefault FALSE
+#define cimClockInterruptTagDefault FALSE
+#define cimOhciTrafficHandingDefault FALSE
+#define cimEhciTrafficHandingDefault FALSE
+#define cimFusionMsgCMultiCoreDefault FALSE
+#define cimFusionMsgCStageDefault FALSE
#endif // _AMD_SBPLATFORM_H_
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index ef0548c..5244490 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef _SB800_EARLY_SETUP_C_
-#define _SB800_EARLY_SETUP_C_
+#ifndef _SB800_EARLY_SETUP_C_
+#define _SB800_EARLY_SETUP_C_
#include <reset.h>
#include <arch/acpi.h>
diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c
index c1a9ded..5c4152a 100644
--- a/src/southbridge/amd/sb800/smbus.c
+++ b/src/southbridge/amd/sb800/smbus.c
@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef _SB800_SMBUS_C_
-#define _SB800_SMBUS_C_
+#ifndef _SB800_SMBUS_C_
+#define _SB800_SMBUS_C_
#include "smbus.h"
More information about the coreboot-gerrit
mailing list