[coreboot-gerrit] New patch to review for coreboot: eec1071 mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Sat Jul 26 01:36:52 CEST 2014
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6371
-gerrit
commit eec10713a74e4cbf867273f64ab79a18627ca557
Author: Martin Roth <gaumless at gmail.com>
Date: Wed May 21 14:23:12 2014 -0600
mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000
Add the Mohon Peak CRB.
Updates to come.
Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed
Signed-off-by: Martin Roth <gaumless at gmail.com>
---
src/mainboard/intel/Kconfig | 3 +
src/mainboard/intel/mohonpeak/Kconfig | 99 +++++++++
src/mainboard/intel/mohonpeak/Makefile.inc | 20 ++
src/mainboard/intel/mohonpeak/acpi/ec.asl | 0
src/mainboard/intel/mohonpeak/acpi/mainboard.asl | 28 +++
src/mainboard/intel/mohonpeak/acpi/platform.asl | 65 ++++++
src/mainboard/intel/mohonpeak/acpi/superio.asl | 0
src/mainboard/intel/mohonpeak/acpi/thermal.asl | 0
src/mainboard/intel/mohonpeak/acpi/video.asl | 0
src/mainboard/intel/mohonpeak/acpi_tables.c | 262 +++++++++++++++++++++++
src/mainboard/intel/mohonpeak/cmos.layout | 141 ++++++++++++
src/mainboard/intel/mohonpeak/devicetree.cb | 68 ++++++
src/mainboard/intel/mohonpeak/dsdt.asl | 53 +++++
src/mainboard/intel/mohonpeak/fadt.c | 42 ++++
src/mainboard/intel/mohonpeak/gpio.h | 178 +++++++++++++++
src/mainboard/intel/mohonpeak/irq_tables.c | 68 ++++++
src/mainboard/intel/mohonpeak/irqroute.c | 23 ++
src/mainboard/intel/mohonpeak/irqroute.h | 68 ++++++
src/mainboard/intel/mohonpeak/mainboard.c | 50 +++++
src/mainboard/intel/mohonpeak/romstage.c | 95 ++++++++
src/mainboard/intel/mohonpeak/thermal.h | 33 +++
21 files changed, 1296 insertions(+)
diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index 4940c54..4f1ff4c 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -17,6 +17,8 @@ config BOARD_INTEL_EMERALDLAKE2
bool "Emerald Lake 2 CRB"
config BOARD_INTEL_JARRELL
bool "Jarrell (SE7520JR2)"
+config BOARD_INTEL_MOHONPEAK
+ bool "Mohon Peak CRB"
config BOARD_INTEL_MTARVON
bool "3100 devkit (Mt. Arvon)"
config BOARD_INTEL_TRUXTON
@@ -38,6 +40,7 @@ source "src/mainboard/intel/eagleheights/Kconfig"
source "src/mainboard/intel/emeraldlake2/Kconfig"
source "src/mainboard/intel/baskingridge/Kconfig"
source "src/mainboard/intel/jarrell/Kconfig"
+source "src/mainboard/intel/mohonpeak/Kconfig"
source "src/mainboard/intel/mtarvon/Kconfig"
source "src/mainboard/intel/truxton/Kconfig"
source "src/mainboard/intel/xe7501devkit/Kconfig"
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
new file mode 100644
index 0000000..4632c7f
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/Kconfig
@@ -0,0 +1,99 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_INTEL_MOHONPEAK
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_FSP_RANGELEY
+ select SOUTHBRIDGE_INTEL_FSP_RANGELEY
+ select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select MMCONF_SUPPORT
+ select POST_IO
+ select DEFAULT_POST_DEVICE_LPC
+ select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
+
+config MAINBOARD_DIR
+ string
+ default intel/mohonpeak
+
+config INCLUDE_ME
+ bool
+ default n
+
+config LOCK_MANAGEMENT_ENGINE
+ bool
+ default n
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Mohon Peak CRB"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 16
+
+config CACHE_ROM_SIZE_OVERRIDE
+ hex
+ default 0x800000
+
+config FSP_FILE
+ string
+ default "../intel/fsp/rangeley/FvFsp.bin"
+
+config CBFS_SIZE
+ hex
+ default 0x00200000
+
+config DRIVERS_PS2_KEYBOARD
+ bool
+ default n
+
+config CONSOLE_POST
+ bool
+ default y
+
+config ENABLE_FSP_FAST_BOOT
+ bool
+ depends on HAVE_FSP_BIN
+ default y
+
+config VIRTUAL_ROM_SIZE
+ hex
+ depends on ENABLE_FSP_FAST_BOOT
+ default 0x400000
+
+config FSP_PACKAGE_DEFAULT
+ bool "Configure defaults for the Intel FSP package"
+ default n
+
+config UART_FOR_CONSOLE
+ int
+ default 1
+ help
+ The Mohon Peak board uses com2 (2f8) for the serial console.
+
+endif # BOARD_INTEL_MOHONPEAK
diff --git a/src/mainboard/intel/mohonpeak/Makefile.inc b/src/mainboard/intel/mohonpeak/Makefile.inc
new file mode 100644
index 0000000..8f999cc
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Sage Electronics Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += irqroute.c
diff --git a/src/mainboard/intel/mohonpeak/acpi/ec.asl b/src/mainboard/intel/mohonpeak/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
new file mode 100644
index 0000000..6b15331
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x05})
+}
diff --git a/src/mainboard/intel/mohonpeak/acpi/platform.asl b/src/mainboard/intel/mohonpeak/acpi/platform.asl
new file mode 100644
index 0000000..aab7603
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/acpi/platform.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/intel/mohonpeak/acpi/superio.asl b/src/mainboard/intel/mohonpeak/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/intel/mohonpeak/acpi/thermal.asl b/src/mainboard/intel/mohonpeak/acpi/thermal.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/intel/mohonpeak/acpi/video.asl b/src/mainboard/intel/mohonpeak/acpi/video.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/intel/mohonpeak/acpi_tables.c b/src/mainboard/intel/mohonpeak/acpi_tables.c
new file mode 100644
index 0000000..52e1af7
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/acpi_tables.c
@@ -0,0 +1,262 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include "northbridge/intel/fsp_rangeley/northbridge.h"
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/fsp_rangeley/nvs.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ gnvs_ = gnvs;
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /*
+ * Enable Front USB ports in S5 by default
+ * to be consistent with back port behavior
+ */
+ gnvs->s5u0 = 1;
+ gnvs->s5u1 = 1;
+
+ /* CBMEM TOC */
+ gnvs->cmem = (u32)get_cbmem_toc();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ u32 lens, bmbound;
+ char pscope[] = "\\_SB.PCI0";
+
+ bmbound = sideband_read(B_UNIT, BMBOUND);
+ lens = acpigen_write_scope(pscope);
+ lens += acpigen_write_name_dword("BMBD", bmbound);
+ generate_cpu_entries();
+ acpigen_patch_len(lens - 1);
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* And tell SMI about it */
+#if CONFIG_HAVE_SMI_HANDLER
+ smm_setup_structures((void *)current, NULL, NULL);
+#endif
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout
new file mode 100644
index 0000000..16ae12f
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/cmos.layout
@@ -0,0 +1,141 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+#save timestamps in pre-ram boot areas
+1719 64 h 0 timestamp_value1
+1783 64 h 0 timestamp_value2
+1847 64 h 0 timestamp_value3
+1911 64 h 0 timestamp_value4
+1975 64 h 0 timestamp_value5
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/intel/mohonpeak/devicetree.cb b/src/mainboard/intel/mohonpeak/devicetree.cb
new file mode 100644
index 0000000..ee688b7
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/devicetree.cb
@@ -0,0 +1,68 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Sage Electronic Engineering, LLC.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/intel/fsp_rangeley
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/fsp_model_406dx
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
+ register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
+ register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 1.0 on end # PCIe Port #1
+ device pci 2.0 on end # PCIe Port #2
+ device pci 3.0 on end # PCIe Port #3
+ device pci 4.0 on end # PCIe Port #4
+ chip southbridge/intel/fsp_rangeley # Rangeley SB
+
+ register "ide_legacy_combined" = "0x0"
+ register "sata_ahci" = "0x1"
+ register "sata_port_map" = "0x0f"
+
+ register "fadt_pm_profile" = "PM_DESKTOP"
+ register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
+
+ device pci 0b.0 on end # IQIA
+ device pci 0e.0 on end # RAS
+ device pci 13.0 on end # SMBus 1
+ device pci 14.0 on end # GbE 0
+ device pci 14.1 on end # GbE 1
+ device pci 14.2 on end # GbE 2
+ device pci 14.3 on end # GbE 3
+ device pci 16.0 on end # USB EHCI
+ device pci 17.0 on end # SATA 2.0
+ device pci 18.0 on end # SATA 3.0
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.3 on end # SMBus 0
+ end
+ end
+end
diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl
new file mode 100644
index 0000000..297a2b3
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Include debug methods
+ #include <arch/x86/acpi/debug.asl>
+
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl>
+
+ #include "acpi/thermal.asl"
+
+ #include <cpu/intel/fsp_model_406dx/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl>
+ #include <southbridge/intel/fsp_rangeley/acpi/soc.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/mohonpeak/fadt.c b/src/mainboard/intel/mohonpeak/fadt.c
new file mode 100644
index 0000000..0aadac6
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/fadt.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <southbridge/intel/fsp_rangeley/soc.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_fill_in_fadt(fadt,facs,dsdt);
+
+#define PLATFORM_HAS_FADT_CUSTOMIZATIONS 0
+
+
+ /*
+ * Platform specific customizations go here.
+ * Update the #define above if customizations are added.
+ */
+
+
+#if PLATFORM_HAS_FADT_CUSTOMIZATIONS
+ header->checksum = 0;
+ header->checksum =
+ acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+#endif
+
+}
diff --git a/src/mainboard/intel/mohonpeak/gpio.h b/src/mainboard/intel/mohonpeak/gpio.h
new file mode 100644
index 0000000..f1315aa
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/gpio.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef MOHONPEAK_GPIO_H
+#define MOHONPEAK_GPIO_H
+
+#include "southbridge/intel/fsp_rangeley/gpio.h"
+
+/* Core GPIO */
+const struct soc_gpio soc_gpio_mode = {
+ .gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */
+ .gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */
+};
+
+const struct soc_gpio soc_gpio_direction = {
+ .gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */
+ .gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */
+};
+
+const struct soc_gpio soc_gpio_level = {
+};
+
+const struct soc_gpio soc_gpio_tpe = {
+};
+
+const struct soc_gpio soc_gpio_tne = {
+};
+
+const struct soc_gpio soc_gpio_ts = {
+};
+
+/* Keep the CFIO struct in register order, not gpio order. */
+const struct soc_cfio soc_cfio_core[] = {
+ { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_28 */
+ { 0x8000, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_27 */
+ { 0x8500, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_26 */
+ { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_21 */
+ { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_22 */
+ { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_23 */
+ { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_25 */
+ { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_24 */
+ { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_19 */
+ { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_20 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_18 */
+ { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_17 */
+ { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_7 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_4 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_5 */
+ { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_6 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_1 */
+ { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_2 */
+ { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_3 */
+ { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_0 */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_10 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_13 */
+ { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_14 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_11 */
+ { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_8 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_9 */
+ { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_12 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_29 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_30 */
+ { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_15 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_16 */
+};
+
+/* SUS GPIO */
+const struct soc_gpio soc_gpio_sus_mode = {
+ .gpio2 = GPIO_MODE_GPIO,
+};
+
+const struct soc_gpio soc_gpio_sus_direction = {
+ .gpio2 = GPIO_DIR_INPUT,
+};
+
+const struct soc_gpio soc_gpio_sus_level = {
+};
+
+const struct soc_gpio soc_gpio_sus_tpe = {
+};
+
+const struct soc_gpio soc_gpio_sus_tne = {
+};
+
+const struct soc_gpio soc_gpio_sus_ts = {
+};
+
+const struct soc_gpio soc_gpio_sus_we = {
+};
+
+
+/* Keep the CFIO struct in register order, not gpio order. */
+const struct soc_cfio soc_cfio_sus[] = {
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_21 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_20 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_19 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_22 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_17 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_18 */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_14 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_13 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_15 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_16 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_25 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_24 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_26 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_27 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_23 */
+ { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_2 */
+ { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_1 */
+ { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_7 */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_3 */
+ { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_0 */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_12 */
+ { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_6 */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_10 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_9 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_8 */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_4 */
+ { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_11 */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
+ { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_5 */
+};
+
+const struct soc_gpio_map gpio_map = {
+ .core = {
+ .mode = &soc_gpio_mode,
+ .direction = &soc_gpio_direction,
+ .level = &soc_gpio_level,
+ .tpe = &soc_gpio_tpe,
+ .tne = &soc_gpio_tne,
+ .ts = &soc_gpio_ts,
+ .cfio_init = &soc_cfio_core[0],
+ .cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio),
+ },
+ .sus = {
+ .mode = &soc_gpio_sus_mode,
+ .direction = &soc_gpio_sus_direction,
+ .level = &soc_gpio_sus_level,
+ .tpe = &soc_gpio_sus_tpe,
+ .tne = &soc_gpio_sus_tne,
+ .ts = &soc_gpio_sus_ts,
+ .we = &soc_gpio_sus_we,
+ .cfio_init = &soc_cfio_sus[0],
+ .cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio),
+ },
+};
+
+#endif
diff --git a/src/mainboard/intel/mohonpeak/irq_tables.c b/src/mainboard/intel/mohonpeak/irq_tables.c
new file mode 100755
index 0000000..eeb0dc6
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/irq_tables.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2013, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+#define PIRQA 0x08
+#define PIRQB 0x09
+#define PIRQC 0x0a
+#define PIRQD 0x0b
+#define PIRQE 0x0c
+#define PIRQF 0x0d
+#define PIRQG 0x0e
+#define PIRQH 0x0f
+
+#define PCI_IRQS 0xDCF0
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x0F1C, /* Device */
+ 0, /* miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x86, /* u8 checksum. */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
+ {0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
+ {0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
+ {0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
+ {0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
+ {0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
+ {0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
+ {0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
+ {0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
+
diff --git a/src/mainboard/intel/mohonpeak/irqroute.c b/src/mainboard/intel/mohonpeak/irqroute.c
new file mode 100644
index 0000000..ee8cbb9
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/irqroute.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/intel/mohonpeak/irqroute.h b/src/mainboard/intel/mohonpeak/irqroute.h
new file mode 100644
index 0000000..0e71a88
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/irqroute.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <southbridge/intel/fsp_rangeley/irq.h>
+#include <southbridge/intel/fsp_rangeley/pci_devs.h>
+
+/*
+ * IR01h PCIe INT(ABCD) - PIRQ ABCD
+ * IR02h PCIe INT(ABCD) - PIRQ ABCD
+ * IR03h PCIe INT(ABCD) - PIRQ ABCD
+ * IR04h PCIe INT(ABCD) - PIRQ ABCD
+ * IR0Bh IQIA INT(ABCD) - PIRQ EFGH
+ * IR0Eh RAS INT(A) - PIRQ A
+ * IR13h SMBUS1 INT(A) - PIRQ B
+ * IR15h GBE INT(A) - PIRQ CDEF
+ * IR1Dh EHCI INT(A) - PIRQ G
+ * IR13h SATA2.0 INT(A) - PIRQ H
+ * IR13h SATA3.0 INT(A) - PIRQ A
+ * IR1Fh LPC INT(ABCD) - PIRQ HGBC
+ */
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV, E, F, G, H), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \
+ PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \
+ PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \
+ PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
+
+/*
+ * Route each PIRQ[A-H] to a PIC IRQ[0-15]
+ * Reserved: 0, 1, 2, 8, 13
+ * PS2 keyboard: 12
+ * ACPI/SCI: 9
+ * Floppy: 6
+ */
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, 10), \
+ PIRQ_PIC(B, 11), \
+ PIRQ_PIC(C, 10), \
+ PIRQ_PIC(D, 11), \
+ PIRQ_PIC(E, 14), \
+ PIRQ_PIC(F, 15), \
+ PIRQ_PIC(G, 14), \
+ PIRQ_PIC(H, 15)
diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c
new file mode 100644
index 0000000..0274e16
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/mainboard.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <southbridge/intel/fsp_rangeley/soc.h>
+
+/*
+ * mainboard_enable is executed as first thing after enumerate_buses().
+ * This is the earliest point to add customization.
+ */
+static void mainboard_enable(device_t dev)
+{
+
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c
new file mode 100644
index 0000000..73e5467
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/romstage.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <drivers/intel/fsp/fsp_util.h>
+#include <northbridge/intel/fsp_rangeley/northbridge.h>
+#include <southbridge/intel/fsp_rangeley/soc.h>
+#include <southbridge/intel/fsp_rangeley/gpio.h>
+#include <southbridge/intel/fsp_rangeley/romstage.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+
+static void interrupt_routing_config(void)
+{
+ u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf;
+
+ /*
+ * Initialize Interrupt Routings for each device in ilb_base_address.
+ * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F.
+ * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23.
+ * This should match devicetree and the ACPI IRQ routing/
+ */
+ write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */
+ write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */
+ write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */
+ write16(ilb_base + ILB_IR03, 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */
+ write16(ilb_base + ILB_IR04, 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */
+ write16(ilb_base + ILB_IR20, 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */
+ write16(ilb_base + ILB_IR22, 0x0007); /* IR16h IR(A) - PIRQ(H) */
+ write16(ilb_base + ILB_IR23, 0x0003); /* IR17h IR(A) - PIRQ(D) */
+ write16(ilb_base + ILB_IR24, 0x0003); /* IR18h IR(A) - PIRQ(D) */
+ write16(ilb_base + ILB_IR31, 0x0020); /* IR1Fh IR(B) - PIRQ(C) */
+}
+
+/**
+ * /brief mainboard call for setup that needs to be done before fsp init
+ *
+ */
+void early_mainboard_romstage_entry(void)
+{
+ setup_soc_gpios(&gpio_map);
+}
+
+/**
+ * /brief mainboard call for setup that needs to be done after fsp init
+ *
+ */
+void late_mainboard_romstage_entry(void)
+{
+ interrupt_routing_config();
+}
+
+/**
+ * Get function disables - most of these will be done automatically
+ * @param fd_mask
+ */
+void get_func_disables(uint32_t *mask)
+{
+
+}
+
+void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
+{
+ /* No overrides needed */
+ return;
+}
diff --git a/src/mainboard/intel/mohonpeak/thermal.h b/src/mainboard/intel/mohonpeak/thermal.h
new file mode 100644
index 0000000..e0fbe30
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/thermal.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef MOHONPEAK_THERMAL_H
+#define MOHONPEAK_THERMAL_H
+
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 100
+
+#endif
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