[coreboot-gerrit] New patch to review for coreboot: 3fb70e9 Delete trailing blank lines at end of file

Sun Jul 27 20:56:51 CEST 2014

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6385

-gerrit

commit 3fb70e9f1219eb9c09e8b967e64ef36f98e50395
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sun Jul 27 20:56:39 2014 +0200

    Delete trailing blank lines at end of file
    
    Change-Id: Id347177cbf531277c04455cd818ab4c121cbd03c
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/arch/armv7/exception_asm.S                                      | 1 -
 src/arch/x86/boot/wakeup.S                                          | 1 -
 src/arch/x86/init/crt0_romcc_epilogue.inc                           | 1 -
 src/arch/x86/init/prologue.inc                                      | 1 -
 src/cpu/amd/agesa/Kconfig                                           | 1 -
 src/cpu/amd/geode_lx/cache_as_ram.inc                               | 1 -
 src/cpu/amd/model_fxx/microcode_rev_c.h                             | 2 --
 src/cpu/amd/model_fxx/microcode_rev_d.h                             | 2 --
 src/cpu/amd/model_fxx/microcode_rev_e.h                             | 2 --
 src/cpu/amd/socket_939/Kconfig                                      | 1 -
 src/cpu/amd/socket_AM2/Kconfig                                      | 1 -
 src/cpu/amd/socket_F/Kconfig                                        | 1 -
 src/cpu/intel/car/cache_as_ram.inc                                  | 1 -
 src/cpu/intel/car/cache_as_ram_ht.inc                               | 1 -
 src/cpu/intel/fit/Kconfig                                           | 1 -
 src/cpu/intel/haswell/cache_as_ram.inc                              | 1 -
 src/cpu/intel/microcode/update-microcodes.sh                        | 1 -
 src/cpu/intel/model_106cx/Kconfig                                   | 1 -
 src/cpu/intel/model_2065x/cache_as_ram.inc                          | 1 -
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 src/cpu/intel/socket_mPGA604/Kconfig                                | 1 -
 src/cpu/via/car/cache_as_ram.inc                                    | 1 -
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 src/cpu/x86/32bit/entry32.inc                                       | 1 -
 src/cpu/x86/smm/smm_stub.S                                          | 1 -
 src/cpu/x86/smm/smmhandler.S                                        | 1 -
 src/cpu/x86/sse_enable.inc                                          | 1 -
 src/device/oprom/x86emu/LICENSE                                     | 1 -
 src/drivers/emulation/Kconfig                                       | 1 -
 src/drivers/intel/fsp/cache_as_ram.inc                              | 1 -
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 src/mainboard/asrock/e350m1/Kconfig                                 | 1 -
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 src/mainboard/cubietech/cubieboard/board_info.txt                   | 1 -
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 src/mainboard/hp/dl145_g3/devicetree.cb                             | 2 --
 src/mainboard/hp/dl165_g6_fam10/devicetree.cb                       | 2 --
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 src/mainboard/ibm/e326/devicetree.cb                                | 1 -
 src/mainboard/iei/juki-511p/devicetree.cb                           | 1 -
 src/mainboard/iei/kino-780am2-fam10/devicetree.cb                   | 1 -
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 src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb                    | 1 -
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 src/mainboard/supermicro/h8dmr_fam10/README                         | 1 -
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 src/mainboard/supermicro/x6dhr_ig2/devicetree.cb                    | 1 -
 src/mainboard/technexion/tim5690/devicetree.cb                      | 1 -
 src/mainboard/technexion/tim8690/devicetree.cb                      | 1 -
 src/mainboard/tyan/s2735/devicetree.cb                              | 1 -
 src/mainboard/tyan/s2850/devicetree.cb                              | 1 -
 src/mainboard/tyan/s2875/devicetree.cb                              | 1 -
 src/mainboard/tyan/s2880/devicetree.cb                              | 1 -
 src/mainboard/tyan/s2881/devicetree.cb                              | 1 -
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 src/mainboard/tyan/s2885/devicetree.cb                              | 1 -
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 src/mainboard/tyan/s4882/devicetree.cb                              | 1 -
 src/mainboard/tyan/s8226/devicetree.cb                              | 1 -
 src/mainboard/via/vt8454c/Kconfig                                   | 1 -
 src/mainboard/via/vt8454c/devicetree.cb                             | 1 -
 src/mainboard/winent/pl6064/devicetree.cb                           | 1 -
 src/mainboard/wyse/s50/devicetree.cb                                | 1 -
 src/northbridge/amd/gx1/Kconfig                                     | 1 -
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 src/northbridge/intel/i440bx/Kconfig                                | 1 -
 src/northbridge/intel/i440lx/Kconfig                                | 1 -
 src/northbridge/intel/i82810/Kconfig                                | 1 -
 src/northbridge/intel/i82830/Kconfig                                | 1 -
 src/northbridge/via/cn400/Kconfig                                   | 1 -
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 src/northbridge/via/vt8601/Kconfig                                  | 1 -
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 src/soc/intel/baytrail/romstage/cache_as_ram.inc                    | 1 -
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 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidMid.c              | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnv.c              | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnvLib.c           | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLate.c          | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLate.c             | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c              | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataReset.c            | 1 -
 .../agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c  | 1 -
 .../amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c   | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdEnv.c                  | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdLate.c                 | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdMid.c                  | 1 -
 .../agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c  | 1 -
 .../f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c      | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcEnv.c                | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcReset.c              | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciMid.c               | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciReset.c             | 1 -
 .../agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c | 1 -
 .../f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciLateService.c      | 1 -
 .../f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciResetService.c     | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciReset.c             | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbEnv.c                | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbLate.c               | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbMid.c                | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbReset.c              | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciLate.c              | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciReset.c             | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h         | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h          | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h        | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c          | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c    | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c      | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c     | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c    | 4 ----
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c     | 2 --
 .../f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c   | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c   | 2 --
 .../Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c      | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c           | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c       | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c       | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c      | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c           | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c   | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c       | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c    | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c      | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c          | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c          | 2 --
 .../agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h    | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c    | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c     | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c   | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h   | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c  | 1 -
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h  | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c    | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h    | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c    | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h    | 2 --
 .../agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c  | 1 -
 .../f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h      | 2 --
 .../f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h  | 2 --
 .../f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h    | 2 --
 .../f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h | 2 --
 .../f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c | 1 -
 .../agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h | 1 -
 .../f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c    | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c           | 2 --
 .../amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c  | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c     | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c                       | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm        | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c            | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c       | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.h       | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c         | 3 ---
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.h         | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpSerial.c         | 3 ---
 .../amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c    | 2 --
 .../amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h    | 1 -
 .../amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h         | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/IdsLib.h                    | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c            | 3 ---
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsRegAcc.h         | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.h        | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.h            | 2 --
 .../amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c          | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c      | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/mftds.c          | 6 ------
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c              | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c   | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c           | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm                 | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c            | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c                | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c              | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c                     | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c                  | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c                 | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.h             | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.h           | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c          | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.h          | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.h          | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c          | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h          | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c        | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.h        | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c               | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h        | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfStandardTraining.h        | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfmemclr.h                  | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mftds.h                     | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h                        | 2 --
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h                        | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnpmu.h                     | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnreg.h                     | 1 -
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mu.h                        | 2 --
 src/vendorcode/amd/agesa/f16kb/gcccar.inc                           | 1 -
 src/vendorcode/amd/cimx/rd890/HotplugFirmware.h                     | 1 -
 src/vendorcode/amd/cimx/rd890/nbHtInterface.c                       | 1 -
 src/vendorcode/amd/cimx/rd890/nbInit.c                              | 2 --
 src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c                  | 1 -
 src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit32.S                | 1 -
 src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c                      | 1 -
 src/vendorcode/amd/cimx/rd890/nbRecovery.c                          | 2 --
 src/vendorcode/amd/cimx/sb700/ACPILIB.c                             | 1 -
 src/vendorcode/amd/cimx/sb700/AZALIA.c                              | 1 -
 src/vendorcode/amd/cimx/sb700/SBCMN.c                               | 1 -
 src/vendorcode/amd/cimx/sb700/SBPOR.c                               | 1 -
 src/vendorcode/amd/cimx/sb800/ACPILIB.c                             | 1 -
 src/vendorcode/amd/cimx/sb800/AMDLIB.c                              | 1 -
 src/vendorcode/amd/cimx/sb800/AZALIA.c                              | 1 -
 src/vendorcode/amd/cimx/sb800/ECLIB.c                               | 1 -
 src/vendorcode/amd/cimx/sb800/ECfan.h                               | 2 --
 src/vendorcode/amd/cimx/sb800/ECfanLIB.c                            | 2 --
 src/vendorcode/amd/cimx/sb800/GEC.c                                 | 2 --
 src/vendorcode/amd/cimx/sb800/MEMLIB.c                              | 2 --
 src/vendorcode/amd/cimx/sb800/SATA.c                                | 2 --
 src/vendorcode/amd/cimx/sb800/SB800.h                               | 1 -
 src/vendorcode/amd/cimx/sb800/SBDEF.h                               | 1 -
 src/vendorcode/amd/cimx/sb800/SBMAIN.c                              | 2 --
 src/vendorcode/amd/cimx/sb800/SBSUBFUN.h                            | 1 -
 src/vendorcode/amd/cimx/sb800/SMM.c                                 | 5 -----
 src/vendorcode/amd/cimx/sb800/USB.c                                 | 1 -
 src/vendorcode/amd/cimx/sb900/AcpiLib.c                             | 1 -
 src/vendorcode/amd/cimx/sb900/AmdLib.c                              | 1 -
 src/vendorcode/amd/cimx/sb900/AmdSbLib.c                            | 1 -
 src/vendorcode/amd/cimx/sb900/AmdSbLib.h                            | 1 -
 src/vendorcode/amd/cimx/sb900/Azalia.c                              | 1 -
 src/vendorcode/amd/cimx/sb900/EcFan.h                               | 2 --
 src/vendorcode/amd/cimx/sb900/EcFanLib.c                            | 1 -
 src/vendorcode/amd/cimx/sb900/EcFanc.c                              | 2 --
 src/vendorcode/amd/cimx/sb900/EcLib.c                               | 1 -
 src/vendorcode/amd/cimx/sb900/Gec.c                                 | 2 --
 src/vendorcode/amd/cimx/sb900/Gpp.c                                 | 1 -
 src/vendorcode/amd/cimx/sb900/GppHp.c                               | 1 -
 src/vendorcode/amd/cimx/sb900/Hudson-2.h                            | 1 -
 src/vendorcode/amd/cimx/sb900/MemLib.c                              | 2 --
 src/vendorcode/amd/cimx/sb900/OEM.h                                 | 1 -
 src/vendorcode/amd/cimx/sb900/Sata.c                                | 2 --
 src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h                      | 1 -
 src/vendorcode/amd/cimx/sb900/SbCmn.c                               | 1 -
 src/vendorcode/amd/cimx/sb900/SbDef.h                               | 1 -
 src/vendorcode/amd/cimx/sb900/SbMain.c                              | 2 --
 src/vendorcode/amd/cimx/sb900/Smm.c                                 | 5 -----
 src/vendorcode/google/Kconfig                                       | 1 -
 1685 files changed, 2284 deletions(-)

diff --git a/src/arch/armv7/exception_asm.S b/src/arch/armv7/exception_asm.S
index e46f4bc..a735db9 100644
--- a/src/arch/armv7/exception_asm.S
+++ b/src/arch/armv7/exception_asm.S
@@ -112,4 +112,3 @@ exception_test:
 	add	r0, $3
 	ldr	r1, [r1]
 	bx	lr
-
diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S
index 8748aa6..9b1b478 100644
--- a/src/arch/x86/boot/wakeup.S
+++ b/src/arch/x86/boot/wakeup.S
@@ -92,4 +92,3 @@ __wakeup_segment = RELOCATED(.)
 	.globl __wakeup_size
 __wakeup_size:
 	.long . - __wakeup
-
diff --git a/src/arch/x86/init/crt0_romcc_epilogue.inc b/src/arch/x86/init/crt0_romcc_epilogue.inc
index 419418d..8013d97 100644
--- a/src/arch/x86/init/crt0_romcc_epilogue.inc
+++ b/src/arch/x86/init/crt0_romcc_epilogue.inc
@@ -19,4 +19,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-
diff --git a/src/arch/x86/init/prologue.inc b/src/arch/x86/init/prologue.inc
index 84e465c..f505b43 100644
--- a/src/arch/x86/init/prologue.inc
+++ b/src/arch/x86/init/prologue.inc
@@ -22,4 +22,3 @@
 
 .section ".rom.data", "a", @progbits
 .section ".rom.text", "ax", @progbits
-
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index fcba0cf..06b2667 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -84,4 +84,3 @@ source src/cpu/amd/agesa/family14/Kconfig
 source src/cpu/amd/agesa/family15/Kconfig
 source src/cpu/amd/agesa/family15tn/Kconfig
 source src/cpu/amd/agesa/family16kb/Kconfig
-
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index 45fd166..5755a68 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -227,4 +227,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-
diff --git a/src/cpu/amd/model_fxx/microcode_rev_c.h b/src/cpu/amd/model_fxx/microcode_rev_c.h
index 9805724..5385ea7 100644
--- a/src/cpu/amd/model_fxx/microcode_rev_c.h
+++ b/src/cpu/amd/model_fxx/microcode_rev_c.h
@@ -145,5 +145,3 @@
 
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-
diff --git a/src/cpu/amd/model_fxx/microcode_rev_d.h b/src/cpu/amd/model_fxx/microcode_rev_d.h
index 61a510c..aee12e2 100644
--- a/src/cpu/amd/model_fxx/microcode_rev_d.h
+++ b/src/cpu/amd/model_fxx/microcode_rev_d.h
@@ -144,5 +144,3 @@
 
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-
diff --git a/src/cpu/amd/model_fxx/microcode_rev_e.h b/src/cpu/amd/model_fxx/microcode_rev_e.h
index 7cdeed0..568a936 100644
--- a/src/cpu/amd/model_fxx/microcode_rev_e.h
+++ b/src/cpu/amd/model_fxx/microcode_rev_e.h
@@ -145,5 +145,3 @@
 
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-
-
diff --git a/src/cpu/amd/socket_939/Kconfig b/src/cpu/amd/socket_939/Kconfig
index 6217072..6a8c1bf 100644
--- a/src/cpu/amd/socket_939/Kconfig
+++ b/src/cpu/amd/socket_939/Kconfig
@@ -2,4 +2,3 @@ config CPU_AMD_SOCKET_939
 	bool
 	select CPU_AMD_MODEL_FXX
 	select X86_AMD_FIXED_MTRRS
-
diff --git a/src/cpu/amd/socket_AM2/Kconfig b/src/cpu/amd/socket_AM2/Kconfig
index 7da5a4d..b0ee3ea 100644
--- a/src/cpu/amd/socket_AM2/Kconfig
+++ b/src/cpu/amd/socket_AM2/Kconfig
@@ -10,4 +10,3 @@ config CPU_SOCKET_TYPE
 	hex
 	default 0x11
 	depends on CPU_AMD_SOCKET_AM2
-
diff --git a/src/cpu/amd/socket_F/Kconfig b/src/cpu/amd/socket_F/Kconfig
index 6c2fafa..304aab8 100644
--- a/src/cpu/amd/socket_F/Kconfig
+++ b/src/cpu/amd/socket_F/Kconfig
@@ -9,4 +9,3 @@ config CPU_SOCKET_TYPE
 	hex
 	default 0x10
 	depends on CPU_AMD_SOCKET_F
-
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 1ea50b8..cfa57b6 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -369,4 +369,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index fb65316..522aa59 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -451,4 +451,3 @@ mtrr_table:
 	.word 0x208, 0x209, 0x20A, 0x20B
 	.word 0x20C, 0x20D, 0x20E, 0x20F
 mtrr_table_end:
-
diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig
index 9b57556..e48dca9 100644
--- a/src/cpu/intel/fit/Kconfig
+++ b/src/cpu/intel/fit/Kconfig
@@ -9,4 +9,3 @@ config CPU_INTEL_NUM_FIT_ENTRIES
 	depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	help
 	  This option selects the number of empty entries in the FIT table.
-
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 36d5654..07fff76 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -319,4 +319,3 @@ mtrr_table:
 	.word 0x20C, 0x20D, 0x20E, 0x20F
 	.word 0x210, 0x211, 0x212, 0x213
 mtrr_table_end:
-
diff --git a/src/cpu/intel/microcode/update-microcodes.sh b/src/cpu/intel/microcode/update-microcodes.sh
index febf6f9..7af446f 100755
--- a/src/cpu/intel/microcode/update-microcodes.sh
+++ b/src/cpu/intel/microcode/update-microcodes.sh
@@ -104,4 +104,3 @@ move_microcode
 
 rm -f $MICROCODE_ARCHIVE
 rm -f $MICROCODE_FILE
-
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index 456c99d..2c521ee 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -14,4 +14,3 @@ config CPU_INTEL_MODEL_106CX
 config CPU_ADDR_BITS
 	int
 	default 32
-
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 21f626b..f7b839b 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -294,4 +294,3 @@ mtrr_table:
 	.word 0x26B, 0x26C, 0x26D
 	.word 0x26E, 0x26F
 mtrr_table_end:
-
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 1a19707..f1d1387 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -333,4 +333,3 @@ mtrr_table:
 	.word 0x20C, 0x20D, 0x20E, 0x20F
 	.word 0x210, 0x211, 0x212, 0x213
 mtrr_table_end:
-
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index baf4ae8..40cdd9d 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -245,4 +245,3 @@ mtrr_table:
 	.word 0x208, 0x209, 0x20A, 0x20B
 	.word 0x20C, 0x20D, 0x20E, 0x20F
 mtrr_table_end:
-
diff --git a/src/cpu/intel/slot_2/Kconfig b/src/cpu/intel/slot_2/Kconfig
index 026099f..1f84d49 100644
--- a/src/cpu/intel/slot_2/Kconfig
+++ b/src/cpu/intel/slot_2/Kconfig
@@ -24,4 +24,3 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x01000
 	depends on CPU_INTEL_SLOT_2
-
diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig
index ea2de87..ef0fb21 100644
--- a/src/cpu/intel/socket_PGA370/Kconfig
+++ b/src/cpu/intel/socket_PGA370/Kconfig
@@ -35,4 +35,3 @@ config DCACHE_RAM_SIZE
 	default 0x01000
 
 endif
-
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 0d4d45f..d5d668a 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -29,4 +29,3 @@ config DCACHE_RAM_SIZE
 	default 0x4000
 
 endif # CPU_INTEL_SOCKET_MPGA604
-
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 17b4b83..69e3053 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -276,4 +276,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index c82edfd..4dad1e5 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -138,4 +138,3 @@ nullidt:
 .globl _estart
 _estart:
 	.code32
-
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index f74e1b8..b016f8e 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -63,4 +63,3 @@ __protected_start:
 
 	/* Restore the BIST value to %eax */
 	movl	%ebp, %eax
-
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 083cb57..b93d204 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -146,4 +146,3 @@ smm_trampoline32:
 
 	/* Exit from SM mode. */
 	rsm
-
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 484b643..e02d21b 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -207,4 +207,3 @@ jumptable:
 	/* core 0 */
 	ljmp $0xa000, $SMM_HANDLER_OFFSET
 .align 1024, 0x00
-
diff --git a/src/cpu/x86/sse_enable.inc b/src/cpu/x86/sse_enable.inc
index 09dea02..a1a7eea 100644
--- a/src/cpu/x86/sse_enable.inc
+++ b/src/cpu/x86/sse_enable.inc
@@ -27,4 +27,3 @@
 
 	/* Restore BIST. */
 	movl	%ebp, %eax
-
diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE
index a3ede4a..f13d418 100644
--- a/src/device/oprom/x86emu/LICENSE
+++ b/src/device/oprom/x86emu/LICENSE
@@ -14,4 +14,3 @@ know. Your code will be removed to comply with your wishes.
 If you have any questions about this, please send email to
 x86emu at linuxlabs.com or KendallB at scitechsoft.com for
 clarification.
-
diff --git a/src/drivers/emulation/Kconfig b/src/drivers/emulation/Kconfig
index 3da9f38..df8d4ff 100644
--- a/src/drivers/emulation/Kconfig
+++ b/src/drivers/emulation/Kconfig
@@ -1,2 +1 @@
 source src/drivers/emulation/qemu/Kconfig
-
diff --git a/src/drivers/intel/fsp/cache_as_ram.inc b/src/drivers/intel/fsp/cache_as_ram.inc
index 40787b5..a2109d1 100644
--- a/src/drivers/intel/fsp/cache_as_ram.inc
+++ b/src/drivers/intel/fsp/cache_as_ram.inc
@@ -166,4 +166,3 @@ CAR_init_params:
 CAR_init_stack:
 	.long  CAR_init_done
 	.long  CAR_init_params
-
diff --git a/src/drivers/sil/3114/Kconfig b/src/drivers/sil/3114/Kconfig
index a14515c..25bb202 100644
--- a/src/drivers/sil/3114/Kconfig
+++ b/src/drivers/sil/3114/Kconfig
@@ -4,5 +4,3 @@ config DRIVERS_SIL_3114
 	help
 	It sets PCI class to IDE compatible native mode, allowing
 	SeaBIOS, FILO etc... to boot from it.
-
-
diff --git a/src/drivers/sil/Kconfig b/src/drivers/sil/Kconfig
index a14515c..25bb202 100644
--- a/src/drivers/sil/Kconfig
+++ b/src/drivers/sil/Kconfig
@@ -4,5 +4,3 @@ config DRIVERS_SIL_3114
 	help
 	It sets PCI class to IDE compatible native mode, allowing
 	SeaBIOS, FILO etc... to boot from it.
-
-
diff --git a/src/drivers/trident/Kconfig b/src/drivers/trident/Kconfig
index 691891d..1dcd5f3 100644
--- a/src/drivers/trident/Kconfig
+++ b/src/drivers/trident/Kconfig
@@ -1,2 +1 @@
 source src/drivers/trident/blade3d/Kconfig
-
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index ebdbf43..73694c3 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -118,4 +118,3 @@ load_cached_ramstage(struct romstage_handoff *handoff,
 #endif /* defined(__PRE_RAM__) */
 
 #endif
-
diff --git a/src/include/cpu/amd/gx1def.h b/src/include/cpu/amd/gx1def.h
index ee36a68..8ac2c52 100644
--- a/src/include/cpu/amd/gx1def.h
+++ b/src/include/cpu/amd/gx1def.h
@@ -51,4 +51,3 @@
 #define MC_SYNC_TIM1		0x840c
 
 #define MC_GBASE_ADD		0x8414
-
diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h
index e6d686c..578f6c2 100644
--- a/src/include/cpu/amd/microcode.h
+++ b/src/include/cpu/amd/microcode.h
@@ -10,4 +10,3 @@ void update_microcode(u32 processor_rev_id);
 #define update_microcode(x)
 #endif
 #endif /* CPU_AMD_MICROCODE_H */
-
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h
index 1e85596..d1ffc0b 100644
--- a/src/include/cpu/amd/model_fxx_rev.h
+++ b/src/include/cpu/amd/model_fxx_rev.h
@@ -119,4 +119,3 @@ int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c
 #endif
 
 #endif
-
diff --git a/src/include/cpu/x86/name.h b/src/include/cpu/x86/name.h
index 2fec878..5a9dd8b 100644
--- a/src/include/cpu/x86/name.h
+++ b/src/include/cpu/x86/name.h
@@ -23,4 +23,3 @@
 void fill_processor_name(char *processor_name);
 
 #endif
-
diff --git a/src/include/device/i915.h b/src/include/device/i915.h
index 34f6d0d..1b7a0c9 100644
--- a/src/include/device/i915.h
+++ b/src/include/device/i915.h
@@ -48,5 +48,3 @@ u32 pack_aux(u32 *src, int src_bytes);
 void unpack_aux(u32 src, u8 *dst, int dst_bytes);
 int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
 	u8 *recv, int recv_size);
-
-
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index 307babd..f483779 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -74,4 +74,3 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void)
 #endif /* defined(__PRE_RAM__) */
 
 #endif /* ROMSTAGE_HANDOFF_H */
-
diff --git a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
index 221b80c..f1f3693 100644
--- a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
+++ b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
@@ -71,4 +71,3 @@ chip northbridge/amd/lx
 		end
 	end
 end
-
diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb
index 3331a12..781beb5 100644
--- a/src/mainboard/amd/db800/devicetree.cb
+++ b/src/mainboard/amd/db800/devicetree.cb
@@ -65,4 +65,3 @@ chip northbridge/amd/lx
 		end
 	end
 end
-
diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb
index 8dd971e..898537b 100644
--- a/src/mainboard/amd/dbm690t/devicetree.cb
+++ b/src/mainboard/amd/dbm690t/devicetree.cb
@@ -119,4 +119,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb
index 09becd4..6e910d3 100644
--- a/src/mainboard/amd/dinar/devicetree.cb
+++ b/src/mainboard/amd/dinar/devicetree.cb
@@ -106,4 +106,3 @@ chip northbridge/amd/agesa/family15/root_complex
 		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 	end #domain
 end #northbridge/amd/agesa/family15/root_complex
-
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 279c7ef..f0f835f 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -96,4 +96,3 @@ config SB800_AHCI_ROM
 	default n
 
 endif # BOARD_AMD_INAGUA
-
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 67c3a1a..95407e5 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -94,4 +94,3 @@ chip northbridge/amd/agesa/family14/root_complex
 		end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
 	end #domain
 end #northbridge/amd/agesa/family14/root_complex
-
diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb
index 93effaa..9a0121d 100644
--- a/src/mainboard/amd/norwich/devicetree.cb
+++ b/src/mainboard/amd/norwich/devicetree.cb
@@ -38,4 +38,3 @@ chip northbridge/amd/lx
 		end
 	end
 end
-
diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb
index 760e5ab..805df7c 100644
--- a/src/mainboard/amd/pistachio/devicetree.cb
+++ b/src/mainboard/amd/pistachio/devicetree.cb
@@ -78,4 +78,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb
index a7a352f..62fb287 100644
--- a/src/mainboard/amd/rumba/devicetree.cb
+++ b/src/mainboard/amd/rumba/devicetree.cb
@@ -18,4 +18,3 @@ chip northbridge/amd/gx2
       		end
     	end
 end
-
diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
index 28b7e01..8ff0e3e 100644
--- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb
+++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
@@ -145,5 +145,3 @@ chip northbridge/amd/amdk8/root_complex
 
 	end #domain
 end
-
-
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
index 685cd7a..ec397ba 100644
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
@@ -27,4 +27,3 @@ use c to delele hex file
 yhlu
 
 09/18/2005
-
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
index 8b5d817..54c34f8 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
@@ -135,5 +135,3 @@ chip northbridge/amd/amdfam10/root_complex
 #	end #domain
 
 end
-
-
diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
index 813dcfc..c058db2 100644
--- a/src/mainboard/amd/south_station/Kconfig
+++ b/src/mainboard/amd/south_station/Kconfig
@@ -89,4 +89,3 @@ config DRIVERS_PS2_KEYBOARD
 	default n
 
 endif # BOARD_AMD_SOUTHSTATION
-
diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb
index 60335d7..1e93585 100644
--- a/src/mainboard/amd/south_station/devicetree.cb
+++ b/src/mainboard/amd/south_station/devicetree.cb
@@ -109,4 +109,3 @@ chip northbridge/amd/agesa/family14/root_complex
                 end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family14/root_complex
-
diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig
index 6013df7..531abdf 100644
--- a/src/mainboard/amd/torpedo/Kconfig
+++ b/src/mainboard/amd/torpedo/Kconfig
@@ -167,4 +167,3 @@ config ONBOARD_LIGHTSENSOR
 	default n
 
 endif # BOARD_AMD_TORPEDO
-
diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb
index bc53f13..4b57b3a 100644
--- a/src/mainboard/amd/torpedo/devicetree.cb
+++ b/src/mainboard/amd/torpedo/devicetree.cb
@@ -87,4 +87,3 @@ chip northbridge/amd/agesa/family12/root_complex
                 end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family12/root_complex
-
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
index 8955435..eb0d6b2 100644
--- a/src/mainboard/amd/union_station/Kconfig
+++ b/src/mainboard/amd/union_station/Kconfig
@@ -88,4 +88,3 @@ config DRIVERS_PS2_KEYBOARD
 	default n
 
 endif # BOARD_AMD_UNIONSTATION
-
diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb
index 2289126..5b4d42b 100644
--- a/src/mainboard/amd/union_station/devicetree.cb
+++ b/src/mainboard/amd/union_station/devicetree.cb
@@ -85,4 +85,3 @@ chip northbridge/amd/agesa/family14/root_complex
                 end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family14/root_complex
-
diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb
index 2035117..5bb966d 100644
--- a/src/mainboard/arima/hdama/devicetree.cb
+++ b/src/mainboard/arima/hdama/devicetree.cb
@@ -183,4 +183,3 @@ chip northbridge/amd/amdk8/root_complex
 		end  # chip northbridge/amd/amdk8
 	end
 end
-
diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb
index d270f3d..2532885 100644
--- a/src/mainboard/artecgroup/dbe61/devicetree.cb
+++ b/src/mainboard/artecgroup/dbe61/devicetree.cb
@@ -39,4 +39,3 @@ chip northbridge/amd/lx
 	end
 
 end
-
diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb
index e8e6ac3..4a94a58 100644
--- a/src/mainboard/asi/mb_5blmp/devicetree.cb
+++ b/src/mainboard/asi/mb_5blmp/devicetree.cb
@@ -45,4 +45,3 @@ chip northbridge/amd/gx1		# Northbridge
   chip cpu/amd/geode_gx1		# CPU
   end
 end
-
diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb
index f246dcf..8b40b9f 100644
--- a/src/mainboard/asrock/939a785gmh/devicetree.cb
+++ b/src/mainboard/asrock/939a785gmh/devicetree.cb
@@ -129,4 +129,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 00cdaa7..876474d 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -82,4 +82,3 @@ config DRIVERS_PS2_KEYBOARD
 	default n
 
 endif # BOARD_ASROCK_E350M1
-
diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb
index e0cc9e3..397b999 100644
--- a/src/mainboard/asus/mew-vm/devicetree.cb
+++ b/src/mainboard/asus/mew-vm/devicetree.cb
@@ -49,4 +49,3 @@ chip northbridge/intel/i82810
 	chip cpu/intel/socket_PGA370
 	end
 end
-
diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb
index 9de4331..3e02a19 100644
--- a/src/mainboard/broadcom/blast/devicetree.cb
+++ b/src/mainboard/broadcom/blast/devicetree.cb
@@ -120,4 +120,3 @@ chip northbridge/amd/amdk8/root_complex
 
 	end #domain
 end
-
diff --git a/src/mainboard/cubietech/cubieboard/board_info.txt b/src/mainboard/cubietech/cubieboard/board_info.txt
index 14a3755..c67b641 100644
--- a/src/mainboard/cubietech/cubieboard/board_info.txt
+++ b/src/mainboard/cubietech/cubieboard/board_info.txt
@@ -1,2 +1 @@
 Category: sbc
-
diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb
index 839b767..db511e5 100644
--- a/src/mainboard/digitallogic/msm800sev/devicetree.cb
+++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb
@@ -83,4 +83,3 @@ chip northbridge/amd/lx
 	end
 
 end
-
diff --git a/src/mainboard/eaglelion/5bcm/devicetree.cb b/src/mainboard/eaglelion/5bcm/devicetree.cb
index 33f1f90..1ea541a 100644
--- a/src/mainboard/eaglelion/5bcm/devicetree.cb
+++ b/src/mainboard/eaglelion/5bcm/devicetree.cb
@@ -49,4 +49,3 @@ chip northbridge/amd/gx1
   end
 
 end
-
diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
index 9e47473..15b86a2 100644
--- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
+++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
@@ -71,4 +71,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-
diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb
index c955ac3..2d4adee 100644
--- a/src/mainboard/hp/dl145_g1/devicetree.cb
+++ b/src/mainboard/hp/dl145_g1/devicetree.cb
@@ -139,4 +139,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/hp/dl145_g3/devicetree.cb b/src/mainboard/hp/dl145_g3/devicetree.cb
index 7012cf9..b7f450e 100644
--- a/src/mainboard/hp/dl145_g3/devicetree.cb
+++ b/src/mainboard/hp/dl145_g3/devicetree.cb
@@ -83,5 +83,3 @@ chip northbridge/amd/amdk8/root_complex
 
    end #domain
 end
-
-
diff --git a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb
index 2dbcb9b..e321393 100644
--- a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb
+++ b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb
@@ -86,5 +86,3 @@ chip northbridge/amd/amdfam10/root_complex
 
    end #domain
 end
-
-
diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
index 7de0c83..04d6d8d 100644
--- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
+++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
@@ -56,4 +56,3 @@ chip northbridge/intel/i82810			# Northbridge
     end
   end
 end
-
diff --git a/src/mainboard/ibm/e325/devicetree.cb b/src/mainboard/ibm/e325/devicetree.cb
index bdaee50..f63249d 100644
--- a/src/mainboard/ibm/e325/devicetree.cb
+++ b/src/mainboard/ibm/e325/devicetree.cb
@@ -67,4 +67,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb
index 1888987..32d04a7 100644
--- a/src/mainboard/ibm/e326/devicetree.cb
+++ b/src/mainboard/ibm/e326/devicetree.cb
@@ -71,4 +71,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/iei/juki-511p/devicetree.cb b/src/mainboard/iei/juki-511p/devicetree.cb
index 4706ff5..4e2b1d9 100644
--- a/src/mainboard/iei/juki-511p/devicetree.cb
+++ b/src/mainboard/iei/juki-511p/devicetree.cb
@@ -54,4 +54,3 @@ chip northbridge/amd/gx1
   end
 
 end
-
diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb
index d5c7033..1dffb4b 100644
--- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb
+++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb
@@ -68,4 +68,3 @@ chip northbridge/amd/amdfam10/root_complex
 		end
 	end #domain
 end #root_complex
-
diff --git a/src/mainboard/iei/nova4899r/devicetree.cb b/src/mainboard/iei/nova4899r/devicetree.cb
index f27662e..2650f75 100644
--- a/src/mainboard/iei/nova4899r/devicetree.cb
+++ b/src/mainboard/iei/nova4899r/devicetree.cb
@@ -61,4 +61,3 @@ chip northbridge/amd/gx1
   end
 
 end
-
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
index a6dba30..99851b8 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
+++ b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
@@ -73,4 +73,3 @@ chip northbridge/amd/lx
 		end
 	end
 end
-
diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb
index b37750c..8d1549a 100644
--- a/src/mainboard/intel/eagleheights/devicetree.cb
+++ b/src/mainboard/intel/eagleheights/devicetree.cb
@@ -70,4 +70,3 @@ chip northbridge/intel/i3100
                 end
         end
 end
-
diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb
index 84cfc4b..16709db 100644
--- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb
+++ b/src/mainboard/iwave/iWRainbowG6/devicetree.cb
@@ -36,4 +36,3 @@ chip northbridge/intel/sch
 		end
 	end
 end
-
diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb
index 50d214b..c49c97a 100644
--- a/src/mainboard/iwill/dk8_htx/devicetree.cb
+++ b/src/mainboard/iwill/dk8_htx/devicetree.cb
@@ -115,5 +115,3 @@ chip northbridge/amd/amdk8/root_complex
 
 	end #domain
 end
-
-
diff --git a/src/mainboard/iwill/dk8s2/devicetree.cb b/src/mainboard/iwill/dk8s2/devicetree.cb
index fda8ca2..21eadb3 100644
--- a/src/mainboard/iwill/dk8s2/devicetree.cb
+++ b/src/mainboard/iwill/dk8s2/devicetree.cb
@@ -73,4 +73,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb
index ea7430b..d92cd6d 100644
--- a/src/mainboard/iwill/dk8x/devicetree.cb
+++ b/src/mainboard/iwill/dk8x/devicetree.cb
@@ -54,4 +54,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb
index 22bdae9..3ab3337 100644
--- a/src/mainboard/kontron/kt690/devicetree.cb
+++ b/src/mainboard/kontron/kt690/devicetree.cb
@@ -123,4 +123,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb
index 78d099a..eb518ea 100644
--- a/src/mainboard/lippert/frontrunner/devicetree.cb
+++ b/src/mainboard/lippert/frontrunner/devicetree.cb
@@ -18,4 +18,3 @@ chip northbridge/amd/gx2
 		end
 	end
 end
-
diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb
index 26e0e0a..48870e8 100644
--- a/src/mainboard/msi/ms6178/devicetree.cb
+++ b/src/mainboard/msi/ms6178/devicetree.cb
@@ -81,4 +81,3 @@ chip northbridge/intel/i82810			# Northbridge
     end
   end
 end
-
diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb
index 013bba3..3c9168d 100644
--- a/src/mainboard/msi/ms9185/devicetree.cb
+++ b/src/mainboard/msi/ms9185/devicetree.cb
@@ -83,5 +83,3 @@ chip northbridge/amd/amdk8/root_complex
 		end # amdk8
 	end #domain
 end
-
-
diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb
index cd4aefe..a3f164e 100644
--- a/src/mainboard/nec/powermate2000/devicetree.cb
+++ b/src/mainboard/nec/powermate2000/devicetree.cb
@@ -51,4 +51,3 @@ chip northbridge/intel/i82810			# Northbridge
     end
   end
 end
-
diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb
index bd00d28..8f7455c 100644
--- a/src/mainboard/newisys/khepri/devicetree.cb
+++ b/src/mainboard/newisys/khepri/devicetree.cb
@@ -79,4 +79,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb
index 85e967a..20e865a 100644
--- a/src/mainboard/pcengines/alix1c/devicetree.cb
+++ b/src/mainboard/pcengines/alix1c/devicetree.cb
@@ -83,4 +83,3 @@ chip northbridge/amd/lx
 	end
 
 end
-
diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb
index d8aa3bc..f8368ed 100644
--- a/src/mainboard/pcengines/alix2d/devicetree.cb
+++ b/src/mainboard/pcengines/alix2d/devicetree.cb
@@ -43,4 +43,3 @@ chip northbridge/amd/lx
 	end
 
 end
-
diff --git a/src/mainboard/pcengines/alix6/board_info.txt b/src/mainboard/pcengines/alix6/board_info.txt
index db8bbb2..6af0ddf 100644
--- a/src/mainboard/pcengines/alix6/board_info.txt
+++ b/src/mainboard/pcengines/alix6/board_info.txt
@@ -2,4 +2,3 @@ Category: half
 Board URL: http://pcengines.ch/alix6f2.htm
 Flashrom support: y
 Clone of: pcengines/alix2d
-
diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb
index d39126c..7c31423 100644
--- a/src/mainboard/rca/rm4100/devicetree.cb
+++ b/src/mainboard/rca/rm4100/devicetree.cb
@@ -65,4 +65,3 @@ chip northbridge/intel/i82830		# Northbridge
     end
   end
 end
-
diff --git a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
index 1d83f10..e47703f 100644
--- a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
+++ b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
@@ -132,4 +132,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README
index 485e7c8..1d7bbdc 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/README
+++ b/src/mainboard/supermicro/h8dmr_fam10/README
@@ -20,4 +20,3 @@ disabled in CBFS. I'm not sure what's causing this particular slowness.
 See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html
 
 Ward, 2009-09-22
-
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
index ee78a2f..c333fba 100644
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -90,4 +90,3 @@ config VGA_BIOS_ID
 	default "102b,0532"
 
 endif # BOARD_SUPERMICRO_H8QGI
-
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
index d99a6ba..6d60820 100644
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -135,4 +135,3 @@ chip northbridge/amd/agesa/family15/root_complex
 		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 	end #domain
 end #northbridge/amd/agesa/family15/root_complex
-
diff --git a/src/mainboard/supermicro/h8scm/devicetree.cb b/src/mainboard/supermicro/h8scm/devicetree.cb
index a4e6c97..f4e4639 100644
--- a/src/mainboard/supermicro/h8scm/devicetree.cb
+++ b/src/mainboard/supermicro/h8scm/devicetree.cb
@@ -130,4 +130,3 @@ chip northbridge/amd/agesa/family15/root_complex
 		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 	end #domain
 end #northbridge/amd/agesa/family15/root_complex
-
diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
index 9dda5d8..82229da 100644
--- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
@@ -121,5 +121,3 @@ chip northbridge/amd/amdfam10/root_complex
 #	end #domain
 
 end
-
-
diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb
index 60508a3..7d6a3c6 100644
--- a/src/mainboard/supermicro/x6dai_g/devicetree.cb
+++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb
@@ -62,4 +62,3 @@ chip northbridge/intel/e7525 # mch
 		end
 	end
 end
-
diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
index 3a037fb..ae38250 100644
--- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
@@ -82,4 +82,3 @@ chip northbridge/intel/e7520 # mch
 	end
 	register "intrline" = "0x00070105"
 end
-
diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
index ca8650b..1d5dd8f 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
@@ -73,4 +73,3 @@ chip northbridge/intel/e7520 # mch
 	end
 	register "intrline" = "0x00070105"
 end
-
diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb
index 23b9741..bf462e2 100644
--- a/src/mainboard/technexion/tim5690/devicetree.cb
+++ b/src/mainboard/technexion/tim5690/devicetree.cb
@@ -110,4 +110,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb
index ff14075..8d1df8b 100644
--- a/src/mainboard/technexion/tim8690/devicetree.cb
+++ b/src/mainboard/technexion/tim8690/devicetree.cb
@@ -113,4 +113,3 @@ chip northbridge/amd/amdk8/root_complex
 		end		#northbridge/amd/amdk8
 	end #domain
 end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb
index d3b6b1e..866bdc5 100644
--- a/src/mainboard/tyan/s2735/devicetree.cb
+++ b/src/mainboard/tyan/s2735/devicetree.cb
@@ -83,4 +83,3 @@ chip northbridge/intel/e7501
                 end
         end
 end
-
diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb
index 85c6384..2698542 100644
--- a/src/mainboard/tyan/s2850/devicetree.cb
+++ b/src/mainboard/tyan/s2850/devicetree.cb
@@ -93,4 +93,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb
index 39eb8b2..bdb4705 100644
--- a/src/mainboard/tyan/s2875/devicetree.cb
+++ b/src/mainboard/tyan/s2875/devicetree.cb
@@ -85,4 +85,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb
index f9f4856..3e18f55 100644
--- a/src/mainboard/tyan/s2880/devicetree.cb
+++ b/src/mainboard/tyan/s2880/devicetree.cb
@@ -96,4 +96,3 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 end
-
diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb
index aab75a3..7d0ed5e 100644
--- a/src/mainboard/tyan/s2881/devicetree.cb
+++ b/src/mainboard/tyan/s2881/devicetree.cb
@@ -127,4 +127,3 @@ chip northbridge/amd/amdk8/root_complex
     end
   end
 end
-
diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb
index 4074695..74a26d0 100644
--- a/src/mainboard/tyan/s2882/devicetree.cb
+++ b/src/mainboard/tyan/s2882/devicetree.cb
@@ -123,4 +123,3 @@ chip northbridge/amd/amdk8/root_complex
 		end # NB
 	end #domain
 end
-
diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb
index 7191e52..97a18e5 100644
--- a/src/mainboard/tyan/s2885/devicetree.cb
+++ b/src/mainboard/tyan/s2885/devicetree.cb
@@ -120,4 +120,3 @@ chip northbridge/amd/amdk8/root_complex
 
 	end #domain
 end
-
diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb
index da59eb5..d64d054 100644
--- a/src/mainboard/tyan/s4880/devicetree.cb
+++ b/src/mainboard/tyan/s4880/devicetree.cb
@@ -96,4 +96,3 @@ chip northbridge/amd/amdk8/root_complex
 
 	end #domain
 end
-
diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb
index 44da2c2..0eb59af 100644
--- a/src/mainboard/tyan/s4882/devicetree.cb
+++ b/src/mainboard/tyan/s4882/devicetree.cb
@@ -193,4 +193,3 @@ chip northbridge/amd/amdk8/root_complex
 
 	end
 end
-
diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb
index f879ec5..ffe47b0 100644
--- a/src/mainboard/tyan/s8226/devicetree.cb
+++ b/src/mainboard/tyan/s8226/devicetree.cb
@@ -130,4 +130,3 @@ chip northbridge/amd/agesa/family15/root_complex
 		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 	end #domain
 end #northbridge/amd/agesa/family15/root_complex
-
diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig
index da71c87..408206c 100644
--- a/src/mainboard/via/vt8454c/Kconfig
+++ b/src/mainboard/via/vt8454c/Kconfig
@@ -24,4 +24,3 @@ config IRQ_SLOT_COUNT
 	default 15
 
 endif # BOARD_VIA_VT8454C
-
diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb
index 87d2ed1..efb5b6c 100644
--- a/src/mainboard/via/vt8454c/devicetree.cb
+++ b/src/mainboard/via/vt8454c/devicetree.cb
@@ -51,4 +51,3 @@ chip northbridge/via/cx700
 		#device pci 12.0 on end  # Ethernet
 	end # pci domain 0
 end # cx700
-
diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb
index f900f78..20d7561 100644
--- a/src/mainboard/winent/pl6064/devicetree.cb
+++ b/src/mainboard/winent/pl6064/devicetree.cb
@@ -78,4 +78,3 @@ chip northbridge/amd/lx
 		end
 	end
 end
-
diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb
index 9008fe6..0288144 100644
--- a/src/mainboard/wyse/s50/devicetree.cb
+++ b/src/mainboard/wyse/s50/devicetree.cb
@@ -49,4 +49,3 @@ chip northbridge/amd/gx2
 		end
 	end
 end
-
diff --git a/src/northbridge/amd/gx1/Kconfig b/src/northbridge/amd/gx1/Kconfig
index 4d57613..86de9d7 100644
--- a/src/northbridge/amd/gx1/Kconfig
+++ b/src/northbridge/amd/gx1/Kconfig
@@ -19,4 +19,3 @@
 
 config NORTHBRIDGE_AMD_GX1
 	bool
-
diff --git a/src/northbridge/intel/e7501/Kconfig b/src/northbridge/intel/e7501/Kconfig
index c8219e8..f8a35a8 100644
--- a/src/northbridge/intel/e7501/Kconfig
+++ b/src/northbridge/intel/e7501/Kconfig
@@ -1,4 +1,3 @@
 config NORTHBRIDGE_INTEL_E7501
 	bool
 	select HAVE_DEBUG_RAM_SETUP
-
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index 902eb73..7544fb5 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -33,4 +33,3 @@ config SDRAMPWR_4DIMM
 	  If your board has 4 DIMM slots, you must use select this option, in
 	  your Kconfig file of the board. On boards with 3 DIMM slots,
 	  do _not_ select this option.
-
diff --git a/src/northbridge/intel/i440lx/Kconfig b/src/northbridge/intel/i440lx/Kconfig
index a88a7a1..80548db 100644
--- a/src/northbridge/intel/i440lx/Kconfig
+++ b/src/northbridge/intel/i440lx/Kconfig
@@ -20,4 +20,3 @@
 config NORTHBRIDGE_INTEL_I440LX
 	bool
 	select HAVE_DEBUG_RAM_SETUP
-
diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig
index 79fe36a..a0d9872 100644
--- a/src/northbridge/intel/i82810/Kconfig
+++ b/src/northbridge/intel/i82810/Kconfig
@@ -46,4 +46,3 @@ config VGA_BIOS_ID
 	string
 	default "8086,7121"
 	depends on NORTHBRIDGE_INTEL_I82810
-
diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig
index 20b31a2..f7fff2d 100644
--- a/src/northbridge/intel/i82830/Kconfig
+++ b/src/northbridge/intel/i82830/Kconfig
@@ -25,4 +25,3 @@ config VIDEO_MB
 	default 1   if I830_VIDEO_MB_1MB
 	default 8   if I830_VIDEO_MB_8MB
 	depends on NORTHBRIDGE_INTEL_I82830
-
diff --git a/src/northbridge/via/cn400/Kconfig b/src/northbridge/via/cn400/Kconfig
index 42fa096..58b9afc 100644
--- a/src/northbridge/via/cn400/Kconfig
+++ b/src/northbridge/via/cn400/Kconfig
@@ -33,4 +33,3 @@ config VIDEO_MB
 	default 64  if CN400_VIDEO_MB_64MB
 	default 128 if CN400_VIDEO_MB_128MB
 	depends on NORTHBRIDGE_VIA_CN400
-
diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig
index 34c330e..c6f73d8 100644
--- a/src/northbridge/via/cn700/Kconfig
+++ b/src/northbridge/via/cn700/Kconfig
@@ -34,4 +34,3 @@ config VIDEO_MB
 	default 64  if CN700_VIDEO_MB_64MB
 	default 128 if CN700_VIDEO_MB_128MB
 	depends on NORTHBRIDGE_VIA_CN700
-
diff --git a/src/northbridge/via/vt8601/Kconfig b/src/northbridge/via/vt8601/Kconfig
index 1b20267..bed2b73 100644
--- a/src/northbridge/via/vt8601/Kconfig
+++ b/src/northbridge/via/vt8601/Kconfig
@@ -1,4 +1,3 @@
 config NORTHBRIDGE_VIA_VT8601
 	bool
 	select HAVE_DEBUG_RAM_SETUP
-
diff --git a/src/northbridge/via/vt8623/Kconfig b/src/northbridge/via/vt8623/Kconfig
index c2aa82b..353b825 100644
--- a/src/northbridge/via/vt8623/Kconfig
+++ b/src/northbridge/via/vt8623/Kconfig
@@ -1,3 +1,2 @@
 config NORTHBRIDGE_VIA_VT8623
 	bool
-
diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig
index 48ea456..6264d52 100644
--- a/src/northbridge/via/vx800/Kconfig
+++ b/src/northbridge/via/vx800/Kconfig
@@ -2,4 +2,3 @@ config NORTHBRIDGE_VIA_VX800
 	bool
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
-
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index f6e029d..266e207 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -283,4 +283,3 @@ fixed_mtrr_table:
 	.word 0x26B, 0x26C, 0x26D
 	.word 0x26E, 0x26F
 fixed_mtrr_table_end:
-
diff --git a/src/southbridge/amd/amd8131/Kconfig b/src/southbridge/amd/amd8131/Kconfig
index 6093a56..a32e262 100644
--- a/src/southbridge/amd/amd8131/Kconfig
+++ b/src/southbridge/amd/amd8131/Kconfig
@@ -19,4 +19,3 @@
 
 config SOUTHBRIDGE_AMD_AMD8131
 	bool
-
diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig
index a4f9aa0..2be21b5 100644
--- a/src/southbridge/amd/cimx/sb700/Kconfig
+++ b/src/southbridge/amd/cimx/sb700/Kconfig
@@ -68,4 +68,3 @@ config REDIRECT_SBCIMX_TRACE_TO_SERIAL
 	  Warning: Only enable this option when debuging or tracing AMD CIMX code.
 
 endif #SOUTHBRIDGE_AMD_CIMX_SB700
-
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index ac25e89..564013b 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -223,4 +223,3 @@ config SB800_IMC_FAN_CONTROL
 endchoice
 
 endif #SOUTHBRIDGE_AMD_CIMX_SB800
-
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index 3bef95a..39c55e1 100644
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -55,4 +55,3 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
         default "southbridge/amd/cimx/sb900/bootblock.c"
 
 endif #SOUTHBRIDGE_AMD_CIMX_SB900
-
diff --git a/src/southbridge/amd/cs5530/Kconfig b/src/southbridge/amd/cs5530/Kconfig
index 3e04276..76f1252 100644
--- a/src/southbridge/amd/cs5530/Kconfig
+++ b/src/southbridge/amd/cs5530/Kconfig
@@ -71,4 +71,3 @@ config SPLASH_GRAPHIC
 	depends on GX1_VIDEO
 
 endmenu
-
diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig
index 5ebc7c8..8f576ab 100644
--- a/src/southbridge/amd/cs5536/Kconfig
+++ b/src/southbridge/amd/cs5536/Kconfig
@@ -20,4 +20,3 @@
 config SOUTHBRIDGE_AMD_CS5536
 	bool
 	select UDELAY_TSC
-
diff --git a/src/southbridge/amd/rs780/Kconfig b/src/southbridge/amd/rs780/Kconfig
index ed77c12..ac263f4 100644
--- a/src/southbridge/amd/rs780/Kconfig
+++ b/src/southbridge/amd/rs780/Kconfig
@@ -19,4 +19,3 @@
 
 config SOUTHBRIDGE_AMD_RS780
 	bool
-
diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig
index e0acc63..3b6d178 100644
--- a/src/southbridge/intel/i3100/Kconfig
+++ b/src/southbridge/intel/i3100/Kconfig
@@ -10,4 +10,3 @@ config HPET_MIN_TICKS
         default 0x90
 
 endif
-
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index d91c8b7..5466b12 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -5,4 +5,3 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/intel/i82371eb/bootblock.c"
 	depends on SOUTHBRIDGE_INTEL_I82371EB
-
diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig
index 839f735..f08808f 100644
--- a/src/southbridge/intel/i82801ax/Kconfig
+++ b/src/southbridge/intel/i82801ax/Kconfig
@@ -22,4 +22,3 @@ config SOUTHBRIDGE_INTEL_I82801AX
 	select IOAPIC
 	select HAVE_HARD_RESET
 	select USE_WATCHDOG_ON_BOOT
-
diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig
index 162f40a..f3609b3 100644
--- a/src/southbridge/intel/i82801bx/Kconfig
+++ b/src/southbridge/intel/i82801bx/Kconfig
@@ -22,4 +22,3 @@ config SOUTHBRIDGE_INTEL_I82801BX
 	select IOAPIC
 	select HAVE_HARD_RESET
 	select USE_WATCHDOG_ON_BOOT
-
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 777b69b..a050f42 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -41,4 +41,3 @@ config HPET_MIN_TICKS
 	default 0x80
 
 endif
-
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 493be60..c719679 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -38,4 +38,3 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
 	default "southbridge/intel/i82801ix/bootblock.c"
 
 endif
-
diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig
index d320a53..4ed9155 100644
--- a/src/southbridge/intel/sch/Kconfig
+++ b/src/southbridge/intel/sch/Kconfig
@@ -51,4 +51,3 @@ config HPET_MIN_TICKS
         default 0x80
 
 endif
-
diff --git a/src/southbridge/ricoh/rl5c476/Kconfig b/src/southbridge/ricoh/rl5c476/Kconfig
index 1213eb0..8712afd 100644
--- a/src/southbridge/ricoh/rl5c476/Kconfig
+++ b/src/southbridge/ricoh/rl5c476/Kconfig
@@ -19,4 +19,3 @@
 
 config SOUTHBRIDGE_RICOH_RL5C476
 	bool
-
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 1fbd57d..390589c 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -11,4 +11,3 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
 config EHCI_BAR
 	hex
 	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
-
diff --git a/src/southbridge/ti/pci7420/Kconfig b/src/southbridge/ti/pci7420/Kconfig
index 0413414..2c20057 100644
--- a/src/southbridge/ti/pci7420/Kconfig
+++ b/src/southbridge/ti/pci7420/Kconfig
@@ -19,4 +19,3 @@
 
 config SOUTHBRIDGE_TI_PCI7420
 	bool
-
diff --git a/src/southbridge/ti/pcixx12/Kconfig b/src/southbridge/ti/pcixx12/Kconfig
index 91dc1b2..5cc0066 100644
--- a/src/southbridge/ti/pcixx12/Kconfig
+++ b/src/southbridge/ti/pcixx12/Kconfig
@@ -19,4 +19,3 @@
 
 config SOUTHBRIDGE_TI_PCIXX12
 	bool
-
diff --git a/src/southbridge/via/vt8235/Kconfig b/src/southbridge/via/vt8235/Kconfig
index 1591274..2ebf814 100644
--- a/src/southbridge/via/vt8235/Kconfig
+++ b/src/southbridge/via/vt8235/Kconfig
@@ -19,4 +19,3 @@
 
 config SOUTHBRIDGE_VIA_VT8235
 	bool
-
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hInstall.h
index f6466ae..8bdba1d 100644
--- a/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hInstall.h
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hInstall.h
@@ -342,4 +342,3 @@ CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
   OPT_F10_HY_ID
   OPT_F10_RB_ID
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionLynxMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionLynxMicrocodeInstall.h
index f5e68aa..22038e7 100644
--- a/src/vendorcode/amd/agesa/f10/Include/OptionLynxMicrocodeInstall.h
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionLynxMicrocodeInstall.h
@@ -48,4 +48,3 @@
 // Code goes here
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionSanMarinoMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionSanMarinoMicrocodeInstall.h
index 672afe7..77f5349 100644
--- a/src/vendorcode/amd/agesa/f10/Include/OptionSanMarinoMicrocodeInstall.h
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionSanMarinoMicrocodeInstall.h
@@ -57,4 +57,3 @@ CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
 };
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionTigrisMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionTigrisMicrocodeInstall.h
index 601dbab..d6463d8 100644
--- a/src/vendorcode/amd/agesa/f10/Include/OptionTigrisMicrocodeInstall.h
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionTigrisMicrocodeInstall.h
@@ -62,4 +62,3 @@ CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
 
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/amd.inc b/src/vendorcode/amd/agesa/f10/Legacy/amd.inc
index d84e44d..85bcef4 100644
--- a/src/vendorcode/amd/agesa/f10/Legacy/amd.inc
+++ b/src/vendorcode/amd/agesa/f10/Legacy/amd.inc
@@ -458,4 +458,3 @@ ENDIF
 IFNDEF   BIT63
     BIT63                       EQU    8000000000000000h
 ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc
index b684a29..339a821 100644
--- a/src/vendorcode/amd/agesa/f10/Makefile.inc
+++ b/src/vendorcode/amd/agesa/f10/Makefile.inc
@@ -48,4 +48,3 @@ CFLAGS_x86_32 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
 export AGESA_ROOT
 export AGESA_INC
 CPPFLAGS_x86_32 += $(AGESA_INC)
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index 4f6e74d..a92b327 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -284,4 +284,3 @@ PmNbCofVidInitWarmCore (
   LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
   FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (((COFVID_STS_MSR *) &MsrRegister)->StartupPstate), (BOOLEAN) FALSE, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index 860e0eb..c45a4a5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -183,4 +183,3 @@ PmNbPstateInitCore (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
index f1c3b42..ac82b31 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -99,4 +99,3 @@ GetF10BlMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
index 631ca3d..3395df9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
@@ -99,4 +99,3 @@ GetF10BlLogicalIdAndRev (
 //  (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
 //  (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
 //};
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
index 442969c..6dba4a1 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -101,4 +101,3 @@ GetF10BlMicroCodePatchesStruct (
   *NumberOfElements = NumberOfUcode;
   *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
index fd6fbb7..b714b40 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -99,4 +99,3 @@ GetF10DaMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
index ef916a9..d556c1a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
@@ -99,4 +99,3 @@ GetF10DaLogicalIdAndRev (
 //  (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
 //  (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
 //};
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
index 8bb3fcc..e80760b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -101,4 +101,3 @@ GetF10DaMicroCodePatchesStruct (
   *NumberOfElements = NumberOfUcode;
   *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index ef5409b..2119230 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -398,4 +398,3 @@ F10CommonRevCGetNumberOfCoresForBrandstring (
   LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
   return (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo + 1);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
index 92b76e1..c300daa 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -101,5 +101,3 @@ GetF10RbMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
index ab6e671..1e5f3e7 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
@@ -112,4 +112,3 @@ CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
   (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10RbHtPhyRegisters
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
index f98489b..e9baf41 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -101,4 +101,3 @@ GetF10RbMicroCodePatchesStruct (
   *NumberOfElements = NumberOfUcode;
   *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
index 5aba3ff..6aaada3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
@@ -209,4 +209,3 @@ CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
   (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10RbPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index 5235603..e21a0dc 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -369,4 +369,3 @@ F10CommonRevDGetNumberOfCoresForBrandstring (
   }
   return ((UINT8) CmpCap);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
index 0f7abcd..adb6b84 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -107,4 +107,3 @@ GetF10HyMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
index 5bcac87..873fbfb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
@@ -109,4 +109,3 @@ GetF10HyLogicalIdAndRev (
   *HyIdPtr = CpuF10HyLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_10_HY;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
index 0923503..9ff2b8e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -109,4 +109,3 @@ GetF10HyMicroCodePatchesStruct (
   *NumberOfElements = NumberOfUcode;
   *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
index 2c441ca..fc441bf 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
@@ -135,5 +135,3 @@ CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
   (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
index c8fc912..3471e43 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
@@ -359,4 +359,3 @@ CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = {
   (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10HyPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
index 9cce68e..204d605 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -152,4 +152,3 @@ GetF10BrandIdString2 (
   *BrandString2Ptr = TableEntryPtr;
   *NumberOfElements = F10BrandIdString2TableCount;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
index 1c27f1d..55bd77e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
@@ -312,4 +312,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = {
   (sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayAm3
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
index 739d75e..0f1fef7 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
@@ -126,6 +126,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = {
   (sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayAsb2
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
index 133fb42..e356881 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
@@ -128,4 +128,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = {
   (sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayC32
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
index 0963f4c..b618816 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
@@ -173,4 +173,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayFr1207 = {
   (sizeof (CpuF10BrandIdString2ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayFr1207
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
index dbf12a6..e89882f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
@@ -121,4 +121,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34 = {
   (sizeof (CpuF10BrandIdString2ArrayG34) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayG34
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
index 676393f..325d2b5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
@@ -122,4 +122,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3 = {
   (sizeof (CpuF10BrandIdString2ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayS1g3
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
index af4baff..123f19c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
@@ -134,5 +134,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4 = {
   (sizeof (CpuF10BrandIdString2ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayS1g4
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
index 4f2296c..2f8936a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -121,4 +121,3 @@ GetF10CacheInfo (
   *NumberOfElements = 1;
   *CacheInfoPtr = &CpuF10CacheInfo;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
index 9959671..18efdcd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -408,4 +408,3 @@ F10Translate7BitVidTo6Bit (
     *MaxVidPtr = (*MaxVidPtr & 0x7E) >> 1;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
index 17ab548..5cc19ac 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -386,4 +386,3 @@ updateCpuFeatureList (
     thisCoreFeatureList++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
index 476a4f4..2bfffe1 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
@@ -744,4 +744,3 @@ CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable = {
   (sizeof (F10HtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10HtPhyRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c
index 29840c8..fa28269 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c
@@ -267,4 +267,3 @@ CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable = {
   (sizeof (F10MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *)F10MsrRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index 01cc2d3..54fcecd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -373,4 +373,3 @@ F10PmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
index ab45ad1..2d66ff4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -1765,4 +1765,3 @@ F10SetRegisterForHtLinkTokenEntry (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/cpuFamRegisters.h
index 4a027a8..864c408 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/cpuFamRegisters.h
@@ -177,4 +177,3 @@
 // TBD
 
 #endif      // _CPU_FAM_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h
index c4f51b7..28f3fea 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h
@@ -97,5 +97,3 @@ AllocateExecutionCache (
   );
 
 #endif  // _CPU_CACHE_INIT_H_
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
index 5af4fbd..bbac04d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -280,4 +280,3 @@ CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
  *                          L O C A L      F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
index 261e25b..2b54bf8 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
@@ -691,4 +691,3 @@ IntToString (
   }
   *(String + SizeInByte * 2) = 0x0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c
index 2d0d77e..ea37cb6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c
@@ -378,5 +378,3 @@ PStateGather (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c
index 1b7bc43..9c37163 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c
@@ -816,6 +816,3 @@ CreateAcpiTablesMain (
 
   return AGESA_SUCCESS;
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
index c5b969e..75ec4c5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
@@ -611,4 +611,3 @@ STATIC
   }
   return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
 } // MakeMemEntry()
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
index dcef101..8361aaa 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
@@ -273,4 +273,3 @@ CreateHestBank (
     HestBankPtr++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
index 9a30f7e..11ae5e4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
@@ -1171,4 +1171,3 @@ FindHtHostCapability (
   );
 
 #endif  // _CPU_TABLE_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.h
index 22acdca..b20c422 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.h
@@ -257,4 +257,3 @@ RelinquishControlOfAllAPs (
   );
 
 #endif  /* _CPU_APIC_UTILITIES_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.h
index c8c9eab..726b667 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.h
@@ -225,4 +225,3 @@ LoadMicrocodePatch (
   IN OUT   AMD_CONFIG_PARAMS *StdHeader
   );
 #endif  // _CPU_EARLY_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h
index 7bb6fcd..118d63b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h
@@ -1027,4 +1027,3 @@ GetEmptyArray (
   );
 
 #endif  // _CPU_FAMILY_TRANSLATION_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.h
index 971b755..eb5a634 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.h
@@ -231,4 +231,3 @@ FinalizeAtPost (
   IN       AMD_CONFIG_PARAMS *StdHeader
   );
 #endif  // _CPU_POST_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c
index cb22e7a..d2c8369 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -221,4 +221,3 @@ GetEarlyPmErrorsSingle (
 
   return (ReturnCode);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSystemTables.h
index 018be2a..a383b3c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSystemTables.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSystemTables.h
@@ -89,4 +89,3 @@ typedef struct {
 
 
 #endif  // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuRegisters.h
index 6a28087..6a951ce 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuRegisters.h
@@ -356,4 +356,3 @@ typedef struct {
 
 
 #endif      // _CPU_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c
index e8f01d1..ef34bf5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c
@@ -185,4 +185,3 @@ IsWarmReset (
  *                            L O C A L    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
index 566eb16..8817d0e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
@@ -155,5 +155,3 @@ AmdInitEnv (
   AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
   return  AmdInitEnvStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
index d9318d5..9025fdc 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
@@ -266,4 +266,3 @@ AmdInitLate (
   AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader);
   return  AmdInitLateStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
index 4f614cd..22a6f6b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
@@ -152,5 +152,3 @@ AmdInitMid (
 
   return AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
index 4aec160..5ed3b61 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
@@ -292,4 +292,3 @@ AmdInitPost (
   IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader);
   return  AmdInitPostStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
index 0ea3a7f..0581ca6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
@@ -204,4 +204,3 @@ AmdInitResetConstructor (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
index 5bb58af..d9d655a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
@@ -153,4 +153,3 @@ AmdLateRunApTaskInitializer (
   AmdApExeParams->RelatedBlockLength = 0;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
index b145909..2cac309 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
@@ -111,4 +111,3 @@ CommonPlatformConfigInit (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h
index afecdce..b776127 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h
@@ -62,4 +62,3 @@ CommonPlatformConfigInit (
   );
 
 #endif // _COMMON_INITS_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h
index e782042..fa28ad2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h
@@ -192,4 +192,3 @@ AmdLateRunApTaskInitializer (
   IN OUT   AP_EXE_PARAMS     *AmdApExeParams
   );
 #endif // _CREATE_STRUCT_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
index 3d98b38..7a8262a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
@@ -301,4 +301,3 @@ S3RestoreStateFromTable (
   IDS_HDT_CONSOLE (" End S3 Restore \n");
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
index 4904c1b..e6020e9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
@@ -395,4 +395,3 @@ Fam10RevDBufferOptimizations (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h
index 4096c3f..15c7b1c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h
@@ -75,5 +75,3 @@ CoherentDiscovery (
   );
 
 #endif  /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h
index 4511214..a454895 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h
@@ -76,5 +76,3 @@ RegangLinks (
   );
 
 #endif  /* _HT_FEAT_GANGING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h
index 1c9d5b8..d018427 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h
@@ -85,5 +85,3 @@ MakeHopCountTable (
   );
 
 #endif  /* _HT_FEAT_ROUTING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h
index 4684d40..f3e6b4f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h
@@ -75,5 +75,3 @@ SubLinkRatioFixup (
   );
 
 #endif  /* _HT_FEAT_SUBLINKS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h
index 0d28191..9a75c27 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h
@@ -74,5 +74,3 @@ TrafficDistribution (
   );
 
 #endif  /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
index 06c69b4..5e47a61 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
@@ -145,4 +145,3 @@ HtIdsGetPortOverride (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h
index ebbd4fa..7962537 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h
@@ -174,4 +174,3 @@ HandleSpecialNodeCase (
   IN       STATE_DATA  *State,
   IN       NORTHBRIDGE *Nb
   );
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h
index fc236c9..b1c77c2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h
@@ -140,4 +140,3 @@ GraphGetBc (
   );
 
 #endif  /* _HT_GRAPH_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
index 5bc51ab..791babd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
@@ -192,4 +192,3 @@ GraphGetBc (
   ASSERT ((NodeA < size) && (NodeB < size));
   return Graph[1 + (NodeA*size + NodeB)*2];
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c
index 669b5cf..c1bdfd1 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c
@@ -89,4 +89,3 @@ CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
   0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x90, 0xFF,  0x00, 0x77, // Node6
   0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x66,  0x60, 0xFF  // Node7
 };
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
index 6ba128e..b47f052 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
@@ -387,4 +387,3 @@ GetOverrideBusNumbers (
   // SecBus, SubBus are not valid if Result is FALSE.
   return result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
index b885bf2..3282f76 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
@@ -237,4 +237,3 @@ NewNorthBridge (
   // Set the config handle for passing to the library.
   Nb->ConfigHandle = State->ConfigHandle;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsCtrl.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsCtrl.c
index 4538c5e..a565be5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsCtrl.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsCtrl.c
@@ -768,4 +768,3 @@ IdsSubHtLinkControl (
   }
   return IDS_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c
index 4b1aa3e..5eca8a2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c
@@ -394,4 +394,3 @@ IdsApRunCodeOnAllLocalCores (
  // BSP codes
   ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, NULL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
index cec2bd8..e48bdcb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
@@ -140,4 +140,3 @@ IdsErrorStopExit:
   ret
 IdsErrorStop  endp
 END
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.c
index 297d030..d3e55af 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.c
@@ -49,4 +49,3 @@
 #include "IdsF10BLService.h"
 #include "Filecode.h"
 #define FILECODE PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.c
index 88f0d9b..8a9a34a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.c
@@ -49,5 +49,3 @@
 #include "IdsF10DAService.h"
 #include "Filecode.h"
 #define FILECODE PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.h
index d29acc5..5262146 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.h
@@ -76,4 +76,3 @@ typedef enum {
   IDS_F10_SCRUB_AUTO = 0x1F       ///< Auto
 } IDS_SCRUB_OPTIONS;
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.c
index da0ac1a..257a948 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.c
@@ -49,4 +49,3 @@
 #include "IdsF10RBService.h"
 #include "Filecode.h"
 #define FILECODE PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsLib.h
index fb686c5..87b1eb4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsLib.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsLib.h
@@ -292,4 +292,3 @@ IdsSubTargetPstate (
   IN       IDS_NV_ITEM *IdsNvPtr
   );
 #endif //_IDS_LIB_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Perf/IdsPerf.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Perf/IdsPerf.c
index f54e229..e65ae07 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Perf/IdsPerf.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Perf/IdsPerf.c
@@ -237,5 +237,3 @@ IdsPerfAnalyseTimestamp (
   IdsPerfRestoreReg (&PerfReg, StdHeader);
   return status;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h
index 25f2196..78e8aab 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h
@@ -76,5 +76,3 @@ MemFInterleaveChannels (
   );
 
 #endif  /* _MFCHI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h
index 744291e..8525e5a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -76,5 +76,3 @@ MemFInterleaveBanks (
   );
 
 #endif  /* _MFCSI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
index 61f6b7c..d060bb9 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
@@ -563,4 +563,3 @@ MemFDMISupport2 (
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
index 5d08b5c..4fdc743 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
@@ -312,4 +312,3 @@ MemFGetScrubAddr (
   return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16));
 }
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h
index 4f42172..b58b85d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h
@@ -76,5 +76,3 @@ MemFInitECC (
   );
 
 #endif  /* _MFECC_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 68891c7..7953a1c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -191,4 +191,3 @@ MemFRASExcludeDIMM (
   NBPtr->SwitchDCT (NBPtr, ReserveDCT);
   return RetVal;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index f4df3a8..a4027cc 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -144,5 +144,3 @@ MemFInterleaveRegion (
     }
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
index a5f9d19..3d9b764 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
@@ -76,5 +76,3 @@ MemFInterleaveRegion (
   );
 
 #endif  /* _MFINTLVRN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index af31a47..5650f4d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -144,4 +144,3 @@ MemFMctMemClr_Sync (
   }
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h
index 8eaf5a8..f6f70d2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h
@@ -74,5 +74,3 @@ MemFInterleaveNodes (
   );
 
 #endif  /* _MFNDI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h
index 705f1d5..b4a9408 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h
@@ -75,5 +75,3 @@ MemFOnlineSpare (
   );
 
 #endif  /* _MFSPR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c
index 00eac12..dd8278c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c
@@ -311,9 +311,3 @@ SetTableValues (
     }
   }
 }
-
-
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c
index 96a8a74..75e4656 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c
@@ -183,4 +183,3 @@ MemErrHandle (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c
index d4a7c9b..9dff6d5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c
@@ -221,4 +221,3 @@ MemMUmaAlloc (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
index fe4c86b..1e77bdb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
@@ -480,4 +480,3 @@ AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
 AlignPointerTo16Byte ENDP
 
     END
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c
index f232fdf..d4447d3 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c
@@ -451,4 +451,3 @@ MemNReadPatternC32 (
   Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
   MemUReadCachelines (Buffer, Address, ClCount);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h
index 99b2939..dc59512 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h
@@ -191,5 +191,3 @@ MemNForceLvDimmVoltageC32 (
   );
 
 #endif  /* _MNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c
index 8b50978..f7e8176 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c
@@ -128,4 +128,3 @@ MemNPlatformSpecificFormFactorInitC32 (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c
index 623f530..d3b51ed 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c
@@ -457,4 +457,3 @@ MemNReadPatternDA (
   Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
   MemUReadCachelines (Buffer, Address, ClCount);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h
index 98de990..df390ba 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h
@@ -189,5 +189,3 @@ MemNCapSpeedBatteryLifeDA (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c
index cdb3b8e..cc4da50 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c
@@ -132,4 +132,3 @@ MemNPlatformSpecificFormFactorInitDA (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c
index 444459c..b8c1156 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c
@@ -190,6 +190,3 @@ MemNPowerDownCtlDA (
     }
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c
index 623d424..ebe92db 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c
@@ -78,4 +78,3 @@ MemPNodeMemBoundaryDA (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c
index f70dfc3..df23242 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c
@@ -506,4 +506,3 @@ MemNProgramCycTimingsDr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c
index c79fe40..a835f40 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c
@@ -449,4 +449,3 @@ MemNReadPatternDr (
   Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
   MemUReadCachelines (Buffer, Address, ClCount);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c
index 9eba8fe..26266ef 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c
@@ -132,6 +132,3 @@ MemNPlatformSpecificFormFactorInitDr (
  *
  *----------------------------------------------------------------------------
  */
-
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c
index fc58fb1..afc77ab 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c
@@ -189,6 +189,3 @@ MemNPowerDownCtlDR (
     }
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c
index 855b1c5..3af3b47 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c
@@ -161,4 +161,3 @@ MemPNodeMemBoundaryDr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c
index 42ff00d..0758b61 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c
@@ -127,4 +127,3 @@ MemNPlatformSpecificFormFactorInitHy (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c
index 8780ce5..eed1936 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c
@@ -450,4 +450,3 @@ MemNReadPatternHy (
   Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
   MemUReadCachelines (Buffer, Address, ClCount);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h
index 157ca63..a5922eb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h
@@ -185,5 +185,3 @@ MemNBeforeDQSTrainingHy (
   );
 
 #endif  /* _MNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c
index b4f4a80..93c2f91 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c
@@ -459,4 +459,3 @@ MemNReadPatternNi (
   Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
   MemUReadCachelines (Buffer, Address, ClCount);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h
index 4e2aaa3..cce2b2f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h
@@ -105,5 +105,3 @@ MemNReadPatternNi (
   );
 
 #endif  /* _MNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c
index 53a8df4..45d2a32 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c
@@ -392,5 +392,3 @@ MemNPollBitFieldNb (
     MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c
index 52f4245..6162980 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c
@@ -153,4 +153,3 @@ MemPDoPsSDA2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c
index e84769d..c8bac8e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c
@@ -158,4 +158,3 @@ MemPDoPsRDr2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c
index aa9ab50..29d75b0 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c
@@ -197,4 +197,3 @@ MemPDoPsRDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c
index 52b9284..344555f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c
@@ -184,4 +184,3 @@ MemPDoPsSDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c
index 6c58cb6..86e8f6e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c
@@ -158,4 +158,3 @@ MemPDoPsUDr2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c
index b2b2cb4..8aff54d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c
@@ -153,4 +153,3 @@ MemPDoPsUDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c
index a8d0810..6c38e4e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c
@@ -225,5 +225,3 @@ MemConstructTechBlock2 (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.h
index 8798e5b..2850d86 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.h
@@ -120,5 +120,3 @@ MemTGetDimmSpdBuffer2 (
   );
 
 #endif  /* _MT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c
index 384b247..f9dfad6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c
@@ -154,6 +154,3 @@ MemTGetLD2 (
 
   return LD;
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.h
index b2764be..5a254fb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.h
@@ -84,5 +84,3 @@ MemTGetLD2 (
   );
 
 #endif  /* _MTOT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.h
index d7011b6..df0d2f0 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.h
@@ -178,5 +178,3 @@
 
 
 #endif  /* _MTSPD2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h
index 4470e38..3b50bbe 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h
@@ -131,5 +131,3 @@ MemTGetDimmSpdBuffer3 (
   );
 
 #endif  /* _MT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h
index 6a66971..190aaf0 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h
@@ -86,5 +86,3 @@ MemTGetLD3 (
   );
 
 #endif  /* _MTOT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
index 77ddfb4..dc9e6c6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -304,4 +304,3 @@ FreqChgCtrlWrd3 (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h
index fd558e6..9ae20d5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h
@@ -83,5 +83,3 @@ MemTDramControlRegInit3 (
   );
 
 #endif  /* _MTRCI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h
index aaa7b61..5312c8a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h
@@ -82,5 +82,3 @@ MemTEMRS23 (
   );
 
 #endif  /* _MTSDI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
index b5e7635..1e8c99d 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -1086,4 +1086,3 @@ MemTGetDimmSpdBuffer3 (
   }
   return DimmPresent;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h
index b63fd76..987abcf 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -162,5 +162,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
index 660f227..5d34f9c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -600,4 +600,3 @@ MemTExitPhyAssistedTrainingClient3 (
   TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisDllShutdownSR, 0);
   return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
index 7d4f728..54ef35c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
@@ -848,4 +848,3 @@ MemTDataEyeSave (
     ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm];
   }
  }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.h
index f3f2670..b66a963 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.h
@@ -113,5 +113,3 @@ typedef struct _SWEEP_INFO {
 
 
 #endif  /* _MTTEDGEDETECT_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c
index 933ee94..0b906b7 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c
@@ -336,4 +336,3 @@ MemTDqsTrainRcvrEnSw (
   IDS_HDT_CONSOLE ("End SW RxEn training\n\n");
   return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfParallelTraining.h
index 947f4e3..79c111b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfParallelTraining.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfParallelTraining.h
@@ -109,5 +109,3 @@ MemFParallelTraining (
  );
 
 #endif  /* _MFPARALLELTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfStandardTraining.h
index fc10aa1..5326dfd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfStandardTraining.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfStandardTraining.h
@@ -77,5 +77,3 @@ MemFStandardTraining (
   );
 
 #endif  /* _MFSTANDARDTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfmemclr.h
index 17469b0..b406b54 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfmemclr.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfmemclr.h
@@ -79,5 +79,3 @@ MemFMctMemClr_Sync (
   );
 
 #endif  /* _MFMEMCLR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mftds.h
index 3e78d24..2ad3bdb 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/mftds.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mftds.h
@@ -76,5 +76,3 @@ MemFInitTableDrive (
   IN       UINT8     time
   );
 #endif  /* _MFTDS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mm.h
index 1983a7a..85e59e5 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/mm.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mm.h
@@ -838,5 +838,3 @@ SetMemRecError (
   );
 
 #endif  /* _MM_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h
index c82ceed..79be138 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h
@@ -1055,5 +1055,3 @@ MemNPhyPowerSavingClientNb (
   );
 
 #endif  /* _MN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mu.h
index abeb985..a571c6b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/mu.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mu.h
@@ -221,5 +221,3 @@ GetVarMtrrHiMsk (
   );
 
 #endif  /* _MU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c
index 016b757..64427fd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c
@@ -92,5 +92,3 @@ AmdCpuRecovery (
   SetRegistersFromTables (&CpuRecoveryParams->PlatformConfig, &CpuRecoveryParams->StdHeader);
   return (AGESA_SUCCESS);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.h
index 788eb1a..f8b72a4 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.h
@@ -72,4 +72,3 @@ AmdCpuRecovery (
   );
 
 #endif // _CPU_RECOVERY_H_
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c
index 469c974..5c03274 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c
@@ -156,4 +156,3 @@ AmdHtInitRecovery (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.h
index 4988547..12be296 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.h
@@ -99,5 +99,3 @@ MemRecNFinalizeMctC32 (
   );
 
 #endif  /* _MRNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
index fd2aa2a..8a18e9f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
@@ -53,5 +53,3 @@
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.h
index 0db57d2..f513a4a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.h
@@ -100,5 +100,3 @@ MemRecNFinalizeMctDA (
 
 
 #endif  /* _MRNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.h
index e4b11cd..f5b4e8b 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.h
@@ -99,5 +99,3 @@ MemRecNFinalizeMctDR (
   );
 
 #endif  /* _MRNDR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.h
index 1b68d55..71060fe 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.h
@@ -107,5 +107,3 @@ MemRecNFinalizeMctHy (
   );
 
 #endif  /* _MRNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnprotohy.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
index c939b06..9e09531 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
@@ -53,5 +53,3 @@
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.h
index 8804b7b..d22de3e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.h
@@ -91,5 +91,3 @@ MemRecNSwitchChannelNi (
   );
 
 #endif  /* _MRNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c
index d6b9011..582f8e8 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c
@@ -185,4 +185,3 @@ MemRecNSetTrainDlyNb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
index d85b6b7..d8e3bda 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
@@ -125,5 +125,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c
index fda9a54..fe24ec7 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -106,5 +106,3 @@ MemRecTTrainDQSPosSw (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c
index 88065d9..d5e54a2 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c
@@ -110,4 +110,3 @@ SetMemRecError (
     MCTPtr->ErrCode = Errorval;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrt3.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrt3.h
index b1bf765..e8daa3e 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrt3.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrt3.h
@@ -115,5 +115,3 @@ MemRecTDramControlRegInit3 (
   );
 
 #endif  /* _MRT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
index 725bd94..9cbc4a6 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
@@ -184,4 +184,3 @@ MemRecUFlushPattern ENDP
 
 
     END
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.h
index 6d69716..4dfcc1c 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.h
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.h
@@ -127,5 +127,3 @@ MemRecFindPSOverrideEntry (
   );
 
 #endif  /* _MRU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c
index 515f993..79eb41f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c
@@ -259,4 +259,3 @@ MemRecFindPSOverrideEntry (
   }
   return NULL;
 }
-
diff --git a/src/vendorcode/amd/agesa/f10/cpcar.inc b/src/vendorcode/amd/agesa/f10/cpcar.inc
index 1a692c4..39744d4 100644
--- a/src/vendorcode/amd/agesa/f10/cpcar.inc
+++ b/src/vendorcode/amd/agesa/f10/cpcar.inc
@@ -474,4 +474,3 @@ AMD_CPUID MACRO arg0
     db    0Fh, 0A2h
   ENDIF
 ENDM
-
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc
index 11f50db..47a5a2c 100644
--- a/src/vendorcode/amd/agesa/f10/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f10/gcccar.inc
@@ -1609,4 +1609,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/BrazosInstall.h b/src/vendorcode/amd/agesa/f12/Include/BrazosInstall.h
index ab6743a..34bfeea 100644
--- a/src/vendorcode/amd/agesa/f12/Include/BrazosInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/BrazosInstall.h
@@ -96,4 +96,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/DanNiInstall.h b/src/vendorcode/amd/agesa/f12/Include/DanNiInstall.h
index 5db06b0..4aebc42 100644
--- a/src/vendorcode/amd/agesa/f12/Include/DanNiInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/DanNiInstall.h
@@ -111,4 +111,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/DanubeInstall.h b/src/vendorcode/amd/agesa/f12/Include/DanubeInstall.h
index 072d9a0..681e1a5 100644
--- a/src/vendorcode/amd/agesa/f12/Include/DanubeInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/DanubeInstall.h
@@ -96,4 +96,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/DevTestInstall.h b/src/vendorcode/amd/agesa/f12/Include/DevTestInstall.h
index 6cbd808..3b81459 100644
--- a/src/vendorcode/amd/agesa/f12/Include/DevTestInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/DevTestInstall.h
@@ -141,4 +141,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/DragonInstall.h b/src/vendorcode/amd/agesa/f12/Include/DragonInstall.h
index 62b9dd7..49c2067 100644
--- a/src/vendorcode/amd/agesa/f12/Include/DragonInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/DragonInstall.h
@@ -96,4 +96,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/LynxInstall.h b/src/vendorcode/amd/agesa/f12/Include/LynxInstall.h
index 19510c4..39cd920 100644
--- a/src/vendorcode/amd/agesa/f12/Include/LynxInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/LynxInstall.h
@@ -96,4 +96,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/f12/Include/MaranelloInstall.h
index 4e06208..5eead99 100644
--- a/src/vendorcode/amd/agesa/f12/Include/MaranelloInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/MaranelloInstall.h
@@ -112,4 +112,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/NileInstall.h b/src/vendorcode/amd/agesa/f12/Include/NileInstall.h
index 78e8d44..01d060b 100644
--- a/src/vendorcode/amd/agesa/f12/Include/NileInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/NileInstall.h
@@ -96,4 +96,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/SabineInstall.h b/src/vendorcode/amd/agesa/f12/Include/SabineInstall.h
index e118f2a..927d5b4 100644
--- a/src/vendorcode/amd/agesa/f12/Include/SabineInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/SabineInstall.h
@@ -111,4 +111,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/SanMarinoInstall.h b/src/vendorcode/amd/agesa/f12/Include/SanMarinoInstall.h
index 4b62f69..b6540fc 100644
--- a/src/vendorcode/amd/agesa/f12/Include/SanMarinoInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/SanMarinoInstall.h
@@ -112,4 +112,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/ScorpiusInstall.h b/src/vendorcode/amd/agesa/f12/Include/ScorpiusInstall.h
index 3111861..c8aa24c 100644
--- a/src/vendorcode/amd/agesa/f12/Include/ScorpiusInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/ScorpiusInstall.h
@@ -111,4 +111,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/TigrisInstall.h b/src/vendorcode/amd/agesa/f12/Include/TigrisInstall.h
index b8c91bc..2409a93 100644
--- a/src/vendorcode/amd/agesa/f12/Include/TigrisInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/TigrisInstall.h
@@ -96,4 +96,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Include/VirgoInstall.h b/src/vendorcode/amd/agesa/f12/Include/VirgoInstall.h
index 8774f78..c87c92f 100644
--- a/src/vendorcode/amd/agesa/f12/Include/VirgoInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/VirgoInstall.h
@@ -129,4 +129,3 @@
 #define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c
index 2241ed7..0f37d66 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c
@@ -417,4 +417,3 @@ AgesaFchOemCallout (
   Status = AmdAgesaCallout (AGESA_FCH_OEM_CALLOUT, (UINT32) 0, FchData);
   return  Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/amd.inc b/src/vendorcode/amd/agesa/f12/Legacy/amd.inc
index 389efba..b227bb3 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/amd.inc
+++ b/src/vendorcode/amd/agesa/f12/Legacy/amd.inc
@@ -458,4 +458,3 @@ ENDIF
 IFNDEF   BIT63
     BIT63                       EQU    8000000000000000h
 ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
index 394e15c..5d9fb7c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
@@ -177,4 +177,3 @@ SetAsymBoost (
   ((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
   LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
index 24e99af..194dcd4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
@@ -74,4 +74,3 @@ F10PmAsymBoostInit (
   );
 
 #endif  // _CPU_F10_ASYM_BOOST_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
index 0e8a532..92992cd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
@@ -242,4 +242,3 @@ SetPstateMSR (
   }
   return (LowestPsEn);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
index 941bcf4..9a511e4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
@@ -74,4 +74,3 @@ F10PmDualPlaneOnlySupport (
   );
 
 #endif  // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index 63e9232..966d774 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -296,4 +296,3 @@ PmNbCofVidInitWarmCore (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index 19a8217..bc8ccbf 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -182,4 +182,3 @@ PmNbPstateInitCore (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
index 0851500..ff3ccc2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -102,4 +102,3 @@ GetF10BlMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
index 72e29cf..e28958d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
@@ -102,4 +102,3 @@ GetF10BlLogicalIdAndRev (
 //  (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
 //  (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
 //};
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
index 5392f4f..a69a5f3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -102,4 +102,3 @@ GetF10BlMicroCodePatchesStruct (
   *NumberOfElements = CpuF10BlNumberOfMicrocodePatches;
   *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
index 6fd6b6f..46c9f3a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -103,4 +103,3 @@ GetF10DaMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
index ca1e6dc..8207354 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
@@ -103,4 +103,3 @@ GetF10DaLogicalIdAndRev (
 //  (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
 //  (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
 //};
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
index 6d1b2df..180c1fb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -102,4 +102,3 @@ GetF10DaMicroCodePatchesStruct (
   *NumberOfElements = CpuF10DaNumberOfMicrocodePatches;
   *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index 407db95..5dfea52 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -505,4 +505,3 @@ F10CommonRevCGetNumberOfPhysicalCores (
   LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
   return (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo + 1);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
index a254928..7aff2f7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -105,5 +105,3 @@ GetF10RbMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
index bf98025..f71c6ec 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
@@ -116,4 +116,3 @@ CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
   (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10RbHtPhyRegisters
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
index ab45bda..bb7e047 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -102,4 +102,3 @@ GetF10RbMicroCodePatchesStruct (
   *NumberOfElements = CpuF10RbNumberOfMicrocodePatches;
   *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
index f4801b9..130d737 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
@@ -230,4 +230,3 @@ CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
   (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10RbPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index 482af86..8e4e45a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -401,4 +401,3 @@ F10CommonRevDGetNumberOfPhysicalCores (
   }
   return ((UINT8) CmpCap);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
index 8a6bdc4..201fafc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -102,4 +102,3 @@ GetF10HyMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
index 7f5148a..f0e205c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
@@ -104,4 +104,3 @@ GetF10HyLogicalIdAndRev (
   *HyIdPtr = CpuF10HyLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_10_HY;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
index 3cae4f7..b2e3286 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -102,4 +102,3 @@ GetF10HyMicroCodePatchesStruct (
   *NumberOfElements = CpuF10HyNumberOfMicrocodePatches;
   *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
index 1dcf3b1..8fcc740 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
@@ -132,5 +132,3 @@ CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
   (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
index 58abbac..c3bf7f8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
@@ -380,4 +380,3 @@ CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = {
   (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10HyPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
index 1fe908d..8450d19 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
@@ -101,4 +101,3 @@ GetF10PhMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10PhMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *PhEquivalenceTablePtr = CpuF10PhMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
index faa0645..efe2a6e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
@@ -92,4 +92,3 @@ GetF10PhLogicalIdAndRev (
   *PhIdPtr = CpuF10PhLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_10_PH;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
index d6d3417..a34f103 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
@@ -101,4 +101,3 @@ GetF10PhMicroCodePatchesStruct (
   *NumberOfElements = CpuF10PhNumberOfMicrocodePatches;
   *PhUcodePtr = &CpuF10PhMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c
index 401b082..0201a79 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -140,4 +140,3 @@ GetF10BrandIdString2 (
   *BrandString2Ptr = TableEntryPtr;
   *NumberOfElements = F10BrandIdString2TableCount;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
index f7604e6..10bb116 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
@@ -331,4 +331,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = {
   (sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayAm3
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
index 6a23f09..54d577e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
@@ -130,6 +130,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = {
   (sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayAsb2
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
index dd38b2c..c7aa750 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
@@ -131,4 +131,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = {
   (sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayC32
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
index 62c9b46..4655452 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
@@ -175,4 +175,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayFr1207 = {
   (sizeof (CpuF10BrandIdString2ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayFr1207
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
index 8ce3763..19ceec9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
@@ -123,4 +123,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34 = {
   (sizeof (CpuF10BrandIdString2ArrayG34) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayG34
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
index 46330ca..2bc72a4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
@@ -124,4 +124,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3 = {
   (sizeof (CpuF10BrandIdString2ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayS1g3
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
index 79d92ef..8c358c8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
@@ -137,5 +137,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4 = {
   (sizeof (CpuF10BrandIdString2ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayS1g4
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
index b9bd763..5047268 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -122,4 +122,3 @@ GetF10CacheInfo (
   *NumberOfElements = 1;
   *CacheInfoPtr = &CpuF10CacheInfo;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c
index 1b2a19b..f592502 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -481,4 +481,3 @@ F10Translate7BitVidTo6Bit (
     *MaxVidPtr = (*MaxVidPtr & 0x7E) >> 1;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
index 704dd74..0923a6d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -389,4 +389,3 @@ updateCpuFeatureList (
     thisCoreFeatureList++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
index 0e30770..ea06afa 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
@@ -747,4 +747,3 @@ CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable = {
   (sizeof (F10HtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10HtPhyRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10MsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10MsrTables.c
index 97d82df..0656eb3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10MsrTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10MsrTables.c
@@ -270,4 +270,3 @@ CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable = {
   (sizeof (F10MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *)F10MsrRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index 1598996..f9b0883 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -406,4 +406,3 @@ F10PmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
index 0df5082..5933e30 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
@@ -543,4 +543,3 @@ typedef struct {
 /* Boost Offset Register F3x10C */
 #define F3x10C_REG 0x10C
 #define F3x10C_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, F3x10C_REG))
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c
index d5bc4e5..2490aa0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -842,4 +842,3 @@ F10GetFrequencyXlatRegInfo (
 
   return AGESA_ERROR;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Utilities.c
index 7d82754..cfe0f39 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -1189,5 +1189,3 @@ F10GetNumberOfBoostedPstatesOnCore (
 
   return NumBoostStates;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c
index 7e7b089..41711e7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c
@@ -275,4 +275,3 @@ CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport =
   F12CreateAcpiCstObj,
   (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c
index 84edcac..c1456a9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c
@@ -110,4 +110,3 @@ GetF12LnMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF12LnMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *LnEquivalenceTablePtr = CpuF12LnMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c
index 4e88e59..0af0a7f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c
@@ -107,4 +107,3 @@ GetF12LnLogicalIdAndRev (
   *LnIdPtr = CpuF12LnLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_12_LN;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c
index 8dc7244..4a2bdc7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c
@@ -108,4 +108,3 @@ GetF12LnMicroCodePatchesStruct (
   *NumberOfElements = CpuF12LnNumberOfMicrocodePatches;
   *LnUcodePtr = &CpuF12LnMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c
index 8711d68..094938c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c
@@ -228,5 +228,3 @@ CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1 = {
   (sizeof (CpuF12LnBrandIdString2ArrayFm1) / sizeof (AMD_CPU_BRAND)),
   CpuF12LnBrandIdString2ArrayFm1
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c
index 372ae4c..ea0496e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c
@@ -177,5 +177,3 @@ CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1 = {
   (sizeof (CpuF12LnBrandIdString2ArrayFs1) / sizeof (AMD_CPU_BRAND)),
   CpuF12LnBrandIdString2ArrayFs1
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c
index 900c82b..a677d76 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c
@@ -127,4 +127,3 @@ GetF12CacheInfo (
   *NumberOfElements = 1;
   *CacheInfoPtr = &CpuF12CacheInfo;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c
index 7d47641..b5ef6c1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c
@@ -210,5 +210,3 @@ CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable = {
   (sizeof (F12MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *) &F12MsrRegisters,
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c
index 56ab032..48892ce 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c
@@ -101,4 +101,3 @@ CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable = {
   (sizeof (F12PerCorePciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F12PerCorePciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c
index d96f6ec..8d7d588 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c
@@ -361,4 +361,3 @@ F12PmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c
index 8b4fbd5..4f4c191 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c
@@ -478,4 +478,3 @@ CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices =
   F12GetPstateMaxState,
   F12GetPstateRegisterInfo
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h
index db4e7ad..bc61a9f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h
@@ -223,4 +223,3 @@
 // TBD
 
 #endif      // _CPU_FAM_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
index fbc1b5e..b428685 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
@@ -747,5 +747,3 @@ IsPowerOfTwo (
   }
   return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.h
index a327d54..c58a6b9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.h
@@ -129,4 +129,3 @@ AllocateExecutionCache (
   );
 
 #endif  // _CPU_CACHE_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c
index 27537d6..c260c8e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -361,4 +361,3 @@ CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
  *                          L O C A L      F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c
index 5661291..683b953 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c
@@ -795,4 +795,3 @@ IntToString (
   }
   *(String + SizeInByte * 2) = 0x0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c
index 8a59886..12d9aa8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuSrat.c
@@ -614,4 +614,3 @@ STATIC
   }
   return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
 } // MakeMemEntry()
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c
index bdef5ba..e81f47e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuWhea.c
@@ -280,4 +280,3 @@ CreateHestBank (
     HestBankPtr++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
index e2c7e14..744edb6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Table.h
@@ -1291,4 +1291,3 @@ GetPerformanceFeatures (
   );
 
 #endif  // _CPU_TABLE_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.h
index 59b836a..c16d099 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.h
@@ -300,4 +300,3 @@ GetIdtr (
   );
 
 #endif  /* _CPU_APIC_UTILITIES_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.h
index 0cda4ad..b0dae3e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.h
@@ -245,4 +245,3 @@ LoadMicrocodePatch (
   IN OUT   AMD_CONFIG_PARAMS *StdHeader
   );
 #endif  // _CPU_EARLY_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h
index a0f2609..779625d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h
@@ -1003,4 +1003,3 @@ GetEmptyArray (
   );
 
 #endif  // _CPU_FAMILY_TRANSLATION_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.h
index 4fd5781..33fe2f9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.h
@@ -228,4 +228,3 @@ SetCoresTscFreqSel (
   IN       AMD_CONFIG_PARAMS   *StdHeader
   );
 #endif  // _CPU_POST_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSystemTables.h
index 0adb279..6b7e3f6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSystemTables.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPowerMgmtSystemTables.h
@@ -89,4 +89,3 @@ typedef struct {
 
 
 #endif  // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuRegisters.h
index 941f4b6..450791c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuRegisters.h
@@ -385,4 +385,3 @@ typedef enum {
 } CPUID_REG;
 
 #endif      // _CPU_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c
index e812dc4..7bb8d7a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuWarmReset.c
@@ -232,4 +232,3 @@ SetWarmResetAtEarly (
  *                            L O C A L    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
index dacaded..4f3a9cd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
@@ -867,5 +867,3 @@ HeapGetCurrentBase (
   ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE));
   return ReturnPtr;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c
index c49cd26..ad9109a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitEnv.c
@@ -177,5 +177,3 @@ AmdInitEnv (
   IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
   return  AmdInitEnvStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c
index fb63efb..b0d4a57 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitLate.c
@@ -293,4 +293,3 @@ AmdInitLate (
   IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader);
   return  AmdInitLateStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c
index 4ec3f7d..dd03b3e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitMid.c
@@ -165,5 +165,3 @@ AmdInitMid (
   IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader);
   return AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c
index 23fa606..4e5360f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitPost.c
@@ -340,4 +340,3 @@ AmdInitPost (
 
   return  AmdInitPostStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c
index 27eae0e..587f5aa 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdInitReset.c
@@ -252,4 +252,3 @@ AmdInitResetConstructor (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c
index 0bedc9b..6ac7a1d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdLateRunApTask.c
@@ -156,4 +156,3 @@ AmdLateRunApTaskInitializer (
   AmdApExeParams->RelatedBlockLength = 0;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c
index c12ad55..9d7c077 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.c
@@ -133,4 +133,3 @@ CommonPlatformConfigInit (
   }
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.h
index 1a736b6..65766d6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonInits.h
@@ -62,4 +62,3 @@ CommonPlatformConfigInit (
   );
 
 #endif // _COMMON_INITS_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c
index d27f817..450b7e7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/CommonReturns.c
@@ -204,4 +204,3 @@ FchTaskDummy (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.h
index 65a2040..30ce8cc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/CreateStruct.h
@@ -192,4 +192,3 @@ AmdLateRunApTaskInitializer (
   IN OUT   AP_EXE_PARAMS     *AmdApExeParams
   );
 #endif // _CREATE_STRUCT_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
index 7b2056b..e5b8ebd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/S3RestoreState.c
@@ -438,4 +438,3 @@ S3RestoreStateFromTable (
   IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c
index 9d37abb..8dca3f0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c
@@ -56,4 +56,3 @@ FchInitLateAzalia (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c
index 4bc7514..6ff0b7d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c
@@ -74,4 +74,3 @@ FchInitRecoveryAzalia (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.c
index 16705a1..e01c925 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.c
@@ -227,5 +227,3 @@ GetFchAcpiPmBase (
 {
   ReadPmio (FCH_PMIOA_REG60, AccessWidth16, AcpiPmBase, StdHeader);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h
index be90192..7345fb7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h
@@ -64,4 +64,3 @@
 #define BOOT_TIME_FLAG_INT19                  0xFC
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c
index 7c4fe81..22d7521 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c
@@ -44,4 +44,3 @@
 #include "FchPlatform.h"
 #include "heapManager.h"
 #define FILECODE PROC_FCH_COMMON_FCHCOMMON_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
index e971abe..f237fd5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
@@ -68,4 +68,3 @@ FchSmmAcpiOn (
   //
   RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGAC, AccessWidth8, ~(BIT6), 0);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchDef.h
index 32230f4..26b224e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchDef.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchDef.h
@@ -441,4 +441,3 @@ BOOLEAN  IsExternalClockMode (IN VOID  *FchDataPtr);
 BOOLEAN  IsLpcRom (OUT VOID);
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
index 0e191c1..f4d630d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
@@ -193,4 +193,3 @@ GetEfuseStatus (
   Mask8 = BIT5;
   LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c
index f478365..72cff31 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c
@@ -141,4 +141,3 @@ RwMem (
   Result = (Result & Mask) | Data;
   WriteMem (Address, OpFlag, &Result);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c
index 0c36786..2c25992 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c
@@ -90,5 +90,3 @@ RwPci (
   rMask = ~Mask;
   LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h
index fb87827..ea5490d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h
@@ -1946,4 +1946,3 @@ FCH_MISC_REGF0                   EQU     0F0h
 #define BGADJ                             0x1F
 #define DACADJ                            0x1B
 #define EFUS_DAC_ADJUSTMENT_CONTROL_DATA  (BGADJ + (DACADJ << 8) + BIT16 )
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
index aadb7bf..02568f6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
@@ -101,4 +101,3 @@ FchInitGecController (
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT3, 0x00);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c
index 99a7287..e202ba9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c
@@ -60,6 +60,3 @@ FchInitEnvGec (
 {
   FchInitGecController (FchDataPtr);
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c
index fae66c1..fbb5cd8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c
@@ -57,5 +57,3 @@ FchInitLateGec (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c
index 78f1549..6fd12e8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c
@@ -80,4 +80,3 @@ FchInitRecoveryGec (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
index 3c55ac6..46328c7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
@@ -338,6 +338,3 @@ StressResetModeLate (
   while (LocalCfgPtr->HwAcpi.StressResetMode) {
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
index ab15687..ef79561 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
@@ -139,4 +139,3 @@ ProgramFchHwAcpiResetP (
     LocalCfgPtr->SataClkMode = 0x0a;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c
index e1e89d3..c9e14d3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c
@@ -103,4 +103,3 @@ FchInitEnvHwAcpi (
   //
   ProgramSpecificFchInitEnvAcpiMmio (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c
index f68916e..ccdf082 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c
@@ -132,4 +132,3 @@ IsGCPU (
     return FALSE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c
index e1f8c60..2b2cce6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c
@@ -196,5 +196,3 @@ FchInitRecoveryHwAcpi (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
index 48a7636..075f4d1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
@@ -167,4 +167,3 @@ FchECfancontrolservice (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
index da47151..dfa040d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
@@ -245,4 +245,3 @@ HwmCaculate (
     LocalCfgPtr->Hwm.HwmCurrent.Voltage[Index] = (ValueWord >> 6) * 512 / LocalCfgPtr->Hwm.HwmCalibrationFactor;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c
index 88f1be7..9dfc67b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c
@@ -72,4 +72,3 @@ FchInitEnvHwm (
     HwmSetRegister (LocalCfgPtr);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c
index 3dd309b..a29bea9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c
@@ -80,5 +80,3 @@ FchInitLateHwm (
     FchECfancontrolservice (LocalCfgPtr);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c
index b219cff..43b50df 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c
@@ -115,6 +115,3 @@ FchInitEnvIde (
   //
   RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, ~BIT0, 0, StdHeader);
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c
index e25271b..3426121 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c
@@ -55,5 +55,3 @@ FchInitLateIde (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c
index 1f4c298..b9a4174 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c
@@ -58,4 +58,3 @@ FchInitMidIde (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
index 826546a..501ba83 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
@@ -123,4 +123,3 @@ SoftwareToggleImcStrapping (
   LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
   FchStall (0xffffffff, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c
index 988d80b..7f00926 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c
@@ -57,5 +57,3 @@ FchInitLateEc (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c
index 2cbe428..1bd0ca0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c
@@ -127,6 +127,3 @@ FchInitRecoveryEc (
   )
 {
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c
index c8b8e8d..12cb969 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c
@@ -150,4 +150,3 @@ ValidateImcFirmware (
     return  TRUE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c
index 0ba9de5..fab8ae2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c
@@ -79,4 +79,3 @@ ImcDisarmSurebootTimer (
   ImcDisableSurebootTimer (LocalCfgPtr);
   LocalCfgPtr->Imc.ImcSureBootTimer = 0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c
index 36c7696..5e26e07 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c
@@ -91,4 +91,3 @@ FchInitRecoveryImc (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
index f8de7ed..374c9a0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
@@ -351,5 +351,3 @@ FCH_DATA_BLOCK   InitEnvCfgDefault = {
     0,                       // CG2PLL
   }
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
index f2a7c41..d0527d2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
@@ -83,5 +83,3 @@ FCH_RESET_DATA_BLOCK   InitResetCfgDefault = {
   FALSE,                 // SerialDebugBusEnable
   FALSE                  // GppToggleReset
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
index 4fe936f..d568fee 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
@@ -109,5 +109,3 @@ FchEnvConstructor (
   EnvParams->FchInterface = FchInterfaceDefault;
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c
index de64e18..54e05a4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c
@@ -97,4 +97,3 @@ FchResetConstructor (
   ResetParams->FchInterface = FchResetInterfaceDefault;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
index 41fb5f8..9544187 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
@@ -91,4 +91,3 @@ FchInitS3LateRestore (
   AgesaStatus = FchTaskLauncher (&FchInitS3LateTaskTable[0], FchDataPtr);
   FchDataPtr->Misc.S3Resume = 0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c
index f34f43b..a39a3a7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c
@@ -59,4 +59,3 @@ FchTaskLauncher (
   }
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c
index 7566a4b..91b47a4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c
@@ -166,5 +166,3 @@ FchInitEnvCreatePrivateData (
 
   return FchParams;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitResetDef.c
index a239aa4..b0b067d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitResetDef.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitResetDef.c
@@ -60,4 +60,3 @@ FchInitResetLoadPrivateDefault (
   StdHeader
   );
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrLate.c
index dfd4a3a..2497a5a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrLate.c
@@ -56,5 +56,3 @@ FchInitLateIr (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Oem.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Oem.h
index 5e2fad9..2a74c32 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Oem.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Oem.h
@@ -138,4 +138,3 @@
 #ifdef NO_EC_SUPPORT
   #define FCH_NO_HWM_SUPPORT          TRUE
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c
index e8036d6..d27fe6e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c
@@ -104,4 +104,3 @@ FchInitEnvPcib (
     RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG40, AccessWidth8, ~BIT3, BIT3, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c
index 20c1a55..f659a12 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c
@@ -109,4 +109,3 @@ FchInitRecoveryPcib (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c
index 98b87e5..678a370 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c
@@ -76,4 +76,3 @@ FchInitEnvAbSpecial (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c
index 1c59cd8..6104e6d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c
@@ -72,4 +72,3 @@ FchInitLateAb (
     WriteAlink (FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), AbValue, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c
index 718fd03..295014d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c
@@ -59,4 +59,3 @@ FchInitMidAb (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c
index 5165b33..7eb1d1d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c
@@ -61,4 +61,3 @@ FchInitResetAb (
 {
   FchProgramAbPowerOnReset (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
index 366adfd..12c8dda 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
@@ -123,4 +123,3 @@ FchProgramAbPowerOnReset (
   RwAlink (FCH_AX_INDXP_REGA4, 0xFFFFFFFE, AbValue, StdHeader);
 
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
index f5e9c94..ae0d8b5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
@@ -44,4 +44,3 @@
 #include "FchPlatform.h"
 #include "Filecode.h"
 #define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
index 16fcde1..da51669 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
@@ -120,4 +120,3 @@ FchResetPcie (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
index fc26d97..b6e72c0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
@@ -204,4 +204,3 @@ FchGppDynamicPowerSaving (
     RwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c
index d9bd435..1a96f6f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c
@@ -559,4 +559,3 @@ AfterGppLinkInit (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c
index 4c12177..eb95ce4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c
@@ -190,4 +190,3 @@ GppPortPollingLtssm (
   FailedPorts |= ActivePorts;
   return FailedPorts;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c
index 92ffde6..af6f162 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c
@@ -61,5 +61,3 @@ FchInitResetGpp (
 {
   ProgramFchGppInitReset (FchDataPtr);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c
index 570609b..0133f23 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c
@@ -64,4 +64,3 @@ FchInitEnvPcie (
   //
   ProgramPcieNativeMode (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c
index e8f0e45..7125eb1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c
@@ -57,5 +57,3 @@ FchInitLatePcie (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c
index b4d7618..b856473 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c
@@ -59,5 +59,3 @@ FchInitResetPcie (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c
index 6312a83..046efa9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c
@@ -67,4 +67,3 @@ FchInitMidSataAhci (
   SataBar5setting (LocalCfgPtr, &Bar5);
   ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
index 627b54d..17ae35c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
@@ -215,4 +215,3 @@ FchProgramSataPhy (
   RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4), StdHeader);
   RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x10, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
index ce795b6..dec267a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
@@ -127,5 +127,3 @@ FchInitResetSataProgram (
     RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFF, 0x04, StdHeader);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
index ef57858..7f1dc88 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
@@ -678,4 +678,3 @@ FchSataSetPortGenMode (
     RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80), AccessWidth16, ~BIT8, 0, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidEnv.c
index 3e455bf..71dc6d9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidEnv.c
@@ -102,4 +102,3 @@ FchInitEnvSataRaid  (
     RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0, SataSSIDValue, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLate.c
index f77d206..b5fd963 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLate.c
@@ -61,5 +61,3 @@ FchInitLateSataRaid (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLib.c
index b7e0d5b..0343987 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLib.c
@@ -65,5 +65,3 @@ SataRaidSetDeviceNumMsi (
 
   SataSetDeviceNumMsi (LocalCfgPtr);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidMid.c
index 7763e36..f637439 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidMid.c
@@ -71,4 +71,3 @@ FchInitMidSataRaid (
   SataBar5setting (LocalCfgPtr, &Bar5);
   ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnv.c
index e5a84a9..c87a594 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnv.c
@@ -102,4 +102,3 @@ FchInitEnvSata (
 
   SataDisableWriteAccess (StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnvLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnvLib.c
index d4d85b5..0384321 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnvLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnvLib.c
@@ -85,4 +85,3 @@ SataSetIrqIntResource (
 
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLate.c
index 98e12cf..a543122 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLate.c
@@ -67,5 +67,3 @@ FchInitLateSataIde (
   SataBar5setting (LocalCfgPtr, &Bar5);
   ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLate.c
index 4973ac5..d387563 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLate.c
@@ -115,4 +115,3 @@ FchInitLateSata (
   //
   SataDisableWriteAccess (StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c
index e88d51e..ce15edd 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c
@@ -257,4 +257,3 @@ FchSataDriveFpga (
 }
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataReset.c
index b6d92de..de9f426 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataReset.c
@@ -62,4 +62,3 @@ FchInitResetSata (
 {
   FchInitResetSataProgram ( FchDataPtr );
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdEnv.c
index 29040a7..08e3d99 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdEnv.c
@@ -99,4 +99,3 @@ FchInitEnvSd (
     RwMem (ACPI_MMIO_BASE + PMIO_BASE +  FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x00);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdLate.c
index ad66637..39602ac 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdLate.c
@@ -56,5 +56,3 @@ FchInitLateSd (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdMid.c
index 8b6a550..20fd987 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdMid.c
@@ -58,4 +58,3 @@ FchInitMidSd (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcEnv.c
index d273897..1ff5091 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcEnv.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcEnv.c
@@ -107,4 +107,3 @@ FchInitEnvLpc (
     RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG78, AccessWidth32, ~BIT1, BIT1, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiReset.c
index d288cce..d2861f9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiReset.c
@@ -110,4 +110,3 @@ FchInitRecoverySpi (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciMid.c
index b651022..360f40f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciMid.c
@@ -156,4 +156,3 @@ EhciInitAfterPciInit (
 {
   FchEhciInitAfterPciInit ( Value, FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
index c79064e..b33a14d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
@@ -176,4 +176,3 @@ FchEhciInitAfterPciInit (
     RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, FchDataPtr->StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
index f316234..b653278 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
@@ -45,4 +45,3 @@
 //
 // Declaration of local functions
 //
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
index 6173ffa..a472360 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
@@ -115,4 +115,3 @@ FchInitResetXhciProgram (
     WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciReset.c
index 7d4ec9f..aee730e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciReset.c
@@ -75,4 +75,3 @@ FchInitRecoveryOhci (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbLate.c
index 038ed24..d435552 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbLate.c
@@ -58,4 +58,3 @@ FchInitLateUsb (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbMid.c
index f6ab38d..15881db 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbMid.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbMid.c
@@ -65,4 +65,3 @@ FchInitMidUsb (
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, ~BIT0, 0);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciLate.c
index 4c35ff3..21444ca 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciLate.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciLate.c
@@ -60,4 +60,3 @@ FchInitLateUsbXhci (
 {
   FchInitLateUsbXhciProgram ( FchDataPtr );
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciRecovery.c
index 6bb82cc..7f06ada 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciRecovery.c
@@ -329,4 +329,3 @@ FchXhciEarlyInit (
   // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702)
   RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT20), BIT20);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciReset.c
index d1606af..4341bc5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciReset.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciReset.c
@@ -78,4 +78,3 @@ FchInitRecoveryXhci (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFuseTable.h
index 9bdeb5f..be619ef 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFuseTable.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFuseTable.h
@@ -83,4 +83,3 @@ typedef struct  {
 #pragma pack (pop)
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h
index bc19ff0..897a68e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h
@@ -63,4 +63,3 @@ GfxFmGmcAllowPstateHigh (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
index 6ece971..dfff378 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
@@ -668,4 +668,3 @@ TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = {
   sizeof (CnbToGncRegisterCopyTable) / sizeof (REGISTER_COPY_ENTRY),
   CnbToGncRegisterCopyTable
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h
index 794241f..5f3c70b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h
@@ -52,4 +52,3 @@ GfxInitAtMidPost (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h
index 3a45f31..8d24226 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h
@@ -52,4 +52,3 @@ GfxInitAtPost (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h
index fdb6862..ee7b1d0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h
@@ -74,4 +74,3 @@ GfxSetIdleVoltageMode (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h
index 28b046d..d034f1d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h
@@ -1853,4 +1853,3 @@
  *</table>
  *</div>
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index 27ed1b8..7f70c81 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -606,4 +606,3 @@ GnbLibLocateService (
   }
   return AGESA_UNSUPPORTED;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
index bb15e6e..4f78755 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -126,5 +126,3 @@ GnbLibCpuPciIndirectWrite (
     GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
   } while ((OffsetRegisterValue & BIT31) == 0);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
index bfef414..0b1559e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -156,4 +156,3 @@ GnbLocateHeapBuffer (
   }
   return LocHeapParams.BufferPtr;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
index 1d6be12..be9c86d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -119,4 +119,3 @@ GnbLibIoRead (
 {
   LibAmdIoRead (Width, Address, Value, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
index db2f717..cbaa625 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -119,7 +119,3 @@ GnbLibMemRead (
 {
   LibAmdMemRead (Width, Address, Value, StdHeader);
 }
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c
index c3f76ed..a9fc75a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c
@@ -149,4 +149,3 @@ GnbLibTimeStamp (
     );
   return TimeStamp;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
index 5f267c6..90c24db 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
@@ -483,4 +483,3 @@ PcieFmGetSbConfigInfo (
   }
   return Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
index 90e9ca5..64df497 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
@@ -239,4 +239,3 @@ GnbIommuIvrsTableDump (
   IDS_HDT_CONSOLE (GNB_TRACE, "\n");
   IDS_HDT_CONSOLE (GNB_TRACE, "<----------  IVRS Table End -------------> \n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
index e668f1b..3ee06ff 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
@@ -396,5 +396,3 @@ GnbLocateLowestVidCode (
   ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0);
   return PpFuseArray->SclkVid[MinVidIndex];
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
index 87607a5..a0ca7cc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
@@ -96,4 +96,3 @@ GnbLocateLowestVidCode (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
index d4cc767..53d3da3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
@@ -356,4 +356,3 @@
       Store (Local0, ABDA)
     }
   }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
index bbe7c18..130ab2a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
@@ -528,5 +528,3 @@ Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16})
     Stall (10)
     Store ("PcieLaneEnableControl Exit", Debug)
   }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
index 6a1b3ac..7d000f3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
@@ -54,4 +54,3 @@ PcieLocateConfigurationData (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index ee7ef01..a4fbf04 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -717,4 +717,3 @@ PcieUserConfigConfigDump (
   }
   IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
index 682e336..72bf4e1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
@@ -199,4 +199,3 @@ PcieUserConfigConfigDump (
 #define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer))
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
index c6d9d47..2596c39 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -253,4 +253,3 @@ PcieInputParserGetEngineDescriptor (
     return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
index d10c383..0b3bd3d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
@@ -80,4 +80,3 @@ PcieInputParserGetLengthOfPcieEnginesList (
   IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
   );
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
index 1c103f7..2afab0d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -655,4 +655,3 @@ PcieIsDescriptorLinkWidthValid (
 
   return Result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
index d68429d..a883e8f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
@@ -53,5 +53,3 @@ PcieMapTopologyOnComplex (
  );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
index 2d4ffe5..22f2e8d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
@@ -188,4 +188,3 @@ PcieAspmGetMaxExitLatencyCallback (
   }
   return SCAN_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
index 556c7fd..f83d5f0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -227,4 +227,3 @@ PciePortRegisterRMW (
   Value = (Value & (~AndMask)) | OrMask;
   PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
index 8b1ac5b..c6850f8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
@@ -114,5 +114,3 @@ PciePollLinkForL0Exit (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
index cf9d127..00ec6a2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
@@ -387,5 +387,3 @@ PciePwrClockGating (
   }
   IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
index 1d0d0ba..3ee639e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
@@ -251,4 +251,3 @@ PcieSiliconHidePorts (
     GnbLibGetHeader (Pcie)
     );
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
index f4c446a..86d9f79 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
@@ -129,5 +129,3 @@ PcieWrapSetTxOffCtrlForLaneMux (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
index 302c78a..2bbb387 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
@@ -60,4 +60,3 @@ PcieTrainingSetPortState (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
index 8914631..150d35c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
@@ -371,5 +371,3 @@ PcieIsDeskewCardDetected (
   }
   return FALSE;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
index 76c4a0b..c41b146 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
@@ -138,5 +138,3 @@ SbPcieInitAspm (
   GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader);
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h
index 6c5facf..df233b6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h
@@ -3006,4 +3006,3 @@ SMU_FIRMWARE_HEADER Fm = {
   &FmBlockArray[0]
 };
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h
index 483bcf3..b2874a7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h
@@ -111,4 +111,3 @@ NbFmInitLclkDpmRcActivity (
   IN      AMD_CONFIG_PARAMS   *StdHeader
   );
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c
index 0e44ebb..1babdc6 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c
@@ -230,4 +230,3 @@ NbInitOnPowerOn (
 
   return  AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c
index 4b997c4..85e6e44 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c
@@ -118,5 +118,3 @@ NbInitAtEarly (
   IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Exit[0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h
index 9e6bb70..eb03a1a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h
@@ -52,6 +52,3 @@ NbInitAtEnv (
   );
 
 #endif
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h
index fde262f..3310df0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h
@@ -52,4 +52,3 @@ NbInitAtLatePost (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c
index aee9193..acf000f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c
@@ -117,5 +117,3 @@ NbInitAtPost (
   IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Exit[0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl
index 29696d4..8ce0c36 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl
@@ -233,5 +233,3 @@ DefinitionBlock (
     }
   } //End of Scope(\_SB)
 }   //End of DefinitionBlock
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c
index a1b9d4b..a3d1b15 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c
@@ -159,4 +159,3 @@ PcieFmGetSbConfigInfo (
   LibAmdMemCopy (SbPort, &DefaultSbPort, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader);
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c
index c7b08a3..d314fda 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c
@@ -240,4 +240,3 @@ PcieFmEnableSlotPowerLimit (
     );
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h
index bee92ad..9b71967 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h
@@ -138,4 +138,3 @@ PcieFmPhyLaneInitInitCallback (
   IN      PCIe_PLATFORM_CONFIG        *Pcie
   );
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c
index 1f16b7f..3ca7c2b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c
@@ -363,4 +363,3 @@ PciePostInit (
   IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h
index 47994ee..c01bca0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h
@@ -62,5 +62,3 @@ PciePortsVisibilityControl (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
index 60640c5..97b6820 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
@@ -121,4 +121,3 @@ PcieInitAtEarly (
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h
index ae33626..d51740b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h
@@ -52,4 +52,3 @@ PcieLateInit (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h
index 1208f2a..614ecf5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h
@@ -66,5 +66,3 @@ PciePortPostS3Init (
   IN       PCIe_PLATFORM_CONFIG  *Pcie
   );
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c
index bd20f36..b2b957b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c
@@ -398,4 +398,3 @@ Fam10RevDBufferOptimizations (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.h
index 926028c..0215f06 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.h
@@ -75,5 +75,3 @@ CoherentDiscovery (
   );
 
 #endif  /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.h
index f168f14..86903f9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.h
@@ -76,5 +76,3 @@ RegangLinks (
   );
 
 #endif  /* _HT_FEAT_GANGING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.h
index 5dbcd6a..d0d205c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.h
@@ -85,5 +85,3 @@ MakeHopCountTable (
   );
 
 #endif  /* _HT_FEAT_ROUTING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.h
index 701e3f3..48c64b9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.h
@@ -75,5 +75,3 @@ SubLinkRatioFixup (
   );
 
 #endif  /* _HT_FEAT_SUBLINKS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c
index bba026f..f2fd9ee 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c
@@ -408,4 +408,3 @@ TrafficDistribution (
       );
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.h
index fbf561a..29081b9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.h
@@ -74,5 +74,3 @@ TrafficDistribution (
   );
 
 #endif  /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c
index ab91fe3..bd040e8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c
@@ -147,4 +147,3 @@ HtIdsGetPortOverride (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.h
index 72b8e96..d93af3e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.h
@@ -174,4 +174,3 @@ HandleSpecialNodeCase (
   IN       STATE_DATA  *State,
   IN       NORTHBRIDGE *Nb
   );
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph.h
index 9f8c104..f68143b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph.h
@@ -140,4 +140,3 @@ GraphGetBc (
   );
 
 #endif  /* _HT_GRAPH_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c
index 5b5517b..9973c22 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c
@@ -195,4 +195,3 @@ GraphGetBc (
   ASSERT ((NodeA < size) && (NodeB < size));
   return Graph[1 + (NodeA*size + NodeB)*2];
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8Ladder.c
index eec64bd..3e83946 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8Ladder.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8Ladder.c
@@ -92,4 +92,3 @@ CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
   0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x90, 0xFF,  0x00, 0x77, // Node6
   0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x66,  0x60, 0xFF  // Node7
 };
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c
index cd19d3d..2038463 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c
@@ -390,4 +390,3 @@ GetOverrideBusNumbers (
   // SecBus, SubBus are not valid if Result is FALSE.
   return result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c
index 428e897..0708150 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c
@@ -244,4 +244,3 @@ NewNorthBridge (
   // Set the config handle for passing to the library.
   Nb->ConfigHandle = State->ConfigHandle;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsLib.h
index 3b55253..750244b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsLib.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/IDS/IdsLib.h
@@ -122,4 +122,3 @@ typedef enum {
 #define IDS_CPB_BOOST_DIS_IGNORE  0xFFFFFFFF
 
 #endif //_IDS_LIB_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.h
index 75f5166..d544500 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.h
@@ -76,5 +76,3 @@ MemFInterleaveChannels (
   );
 
 #endif  /* _MFCHI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.h
index f31896c..9fccd53 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -76,5 +76,3 @@ MemFInterleaveBanks (
   );
 
 #endif  /* _MFCSI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c
index a663337..511f845 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c
@@ -585,4 +585,3 @@ MemFDMISupport2 (
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.h
index aed0eec..33f255c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.h
@@ -76,5 +76,3 @@ MemFInitECC (
   );
 
 #endif  /* _MFECC_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index d146743..6e5f8b1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -198,4 +198,3 @@ MemFRASExcludeDIMM (
   NBPtr->SwitchDCT (NBPtr, ReserveDCT);
   return RetVal;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index f04d119..d63a63d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -159,5 +159,3 @@ MemFInterleaveRegion (
     }
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
index 364d0f2..5837094 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
@@ -76,5 +76,3 @@ MemFInterleaveRegion (
   );
 
 #endif  /* _MFINTLVRN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index 8ace00f..5e6d9c3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -148,4 +148,3 @@ MemFMctMemClr_Sync (
   }
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.h
index 218f475..7469bd5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.h
@@ -74,5 +74,3 @@ MemFInterleaveNodes (
   );
 
 #endif  /* _MFNDI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.h
index bfad4eb..d666356 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.h
@@ -75,5 +75,3 @@ MemFOnlineSpare (
   );
 
 #endif  /* _MFSPR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/mftds.c
index 42617e6..6c7e11c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/mftds.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/mftds.c
@@ -322,9 +322,3 @@ SetTableValues (
     }
   }
 }
-
-
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c
index 1bf4e5d..d460272 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c
@@ -184,4 +184,3 @@ MemErrHandle (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c
index 8bdc7fe..6e48374 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c
@@ -242,4 +242,3 @@ MemMUmaAlloc (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c
index f46d501..6585596 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c
@@ -486,4 +486,3 @@ memNEnableTrainSequenceC32 (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.h
index cc739af..5b50d0e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.h
@@ -207,5 +207,3 @@ MemNForceLvDimmVoltageC32 (
   );
 
 #endif  /* _MNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c
index d9609ca..8218172 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c
@@ -131,4 +131,3 @@ MemNPlatformSpecificFormFactorInitC32 (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c
index ed2ae37..dd311b1 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c
@@ -488,4 +488,3 @@ memNEnableTrainSequenceDA (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.h
index 8bf710f..1f6f748 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.h
@@ -204,5 +204,3 @@ MemNPlatformSpecificFormFactorInitNi (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c
index 9a95b97..0e8d86f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c
@@ -135,4 +135,3 @@ MemNPlatformSpecificFormFactorInitDA (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c
index 1038dbf..a2d4b1a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c
@@ -194,6 +194,3 @@ MemNPowerDownCtlDA (
     }
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c
index 8ad203f..8e83fd0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c
@@ -82,4 +82,3 @@ MemPNodeMemBoundaryDA (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c
index b443b76..cb6a777 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c
@@ -510,4 +510,3 @@ MemNProgramCycTimingsDr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c
index 0e100c8..a67eb63 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c
@@ -135,6 +135,3 @@ MemNPlatformSpecificFormFactorInitDr (
  *
  *----------------------------------------------------------------------------
  */
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c
index 37a2e36..700a901 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c
@@ -193,6 +193,3 @@ MemNPowerDownCtlDR (
     }
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c
index 2dfb5dc..c3d3bc3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c
@@ -165,4 +165,3 @@ MemPNodeMemBoundaryDr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c
index 5f9357c..cfdbd26 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c
@@ -130,4 +130,3 @@ MemNPlatformSpecificFormFactorInitHy (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c
index 72274b3..52fd536 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c
@@ -486,4 +486,3 @@ memNEnableTrainSequenceHy (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.h
index 472474f..2b2b6bb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.h
@@ -207,5 +207,3 @@ MemNBeforeDQSTrainingHy (
   );
 
 #endif  /* _MNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c
index 812c604..ce52041 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c
@@ -790,5 +790,3 @@ MemNS3ChangeNbFrequencyWrapLN (
 
   return Status;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c
index 9b66b23..31f08ce 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c
@@ -163,4 +163,3 @@ MemNTechBlockSwitchLN (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.h
index 73f6748..5607676 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.h
@@ -232,5 +232,3 @@ MemNOverridePrevPassRcvEnDlyLN (
   );
 
 #endif  /* _MNLN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c
index ded05e4..31286ef 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c
@@ -201,6 +201,3 @@ MemNPowerDownCtlLN (
     MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c
index 766b444..6a1f5ff 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c
@@ -210,4 +210,3 @@ MemNOverridePrevPassRcvEnDlyLN (
   }
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c
index 9c52705..acbcae7 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c
@@ -604,5 +604,3 @@ MemNInitNBRegTableLN (
  *                              LOCAL FUNCTIONS
  *
  *----------------------------------------------------------------------------*/
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c
index aed7aa5f..ed1d662 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c
@@ -493,4 +493,3 @@ memNEnableTrainSequenceNi (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.h
index e25956d..8fbf0bf 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.h
@@ -108,5 +108,3 @@ memNEnableTrainSequenceNi (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c
index 0991ad6..0a8d6a9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c
@@ -136,4 +136,3 @@ MemNPlatformSpecificFormFactorInitNi (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c
index 12c4aa5..3bab92e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c
@@ -493,4 +493,3 @@ memNEnableTrainSequencePh (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.h
index 8d3892f..bba9b20 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.h
@@ -119,5 +119,3 @@ memNEnableTrainSequencePh (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c
index e187680..b25b917 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c
@@ -137,4 +137,3 @@ MemNPlatformSpecificFormFactorInitPh (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c
index 2829aa7..7d823e8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c
@@ -493,4 +493,3 @@ memNEnableTrainSequenceRb (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.h
index 1748f75..085c13e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.h
@@ -119,5 +119,3 @@ memNEnableTrainSequenceRb (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c
index 3d08535..fe6e879 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c
@@ -137,4 +137,3 @@ MemNPlatformSpecificFormFactorInitRb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c
index 99d8a16..22fb0fb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c
@@ -1290,4 +1290,3 @@ MemNInitCPGUnb (
   NBPtr->FamilySpecificHook[SetupHwTrainingEngine] = MemNSetupHwTrainingEngineUnb;
   NBPtr->CPGInit = 0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c
index 08b3a66..056559f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c
@@ -1967,4 +1967,3 @@ MemNResetRxFifoPtrClientNb (
   }
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c
index 84153f8..418afca 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c
@@ -156,4 +156,3 @@ MemPDoPsSDA2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c
index 059d854..cc73ecb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c
@@ -161,4 +161,3 @@ MemPDoPsRDr2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c
index 589fd37..25c5893 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c
@@ -200,4 +200,3 @@ MemPDoPsRDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c
index a30fbf9..fcdf647 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c
@@ -187,4 +187,3 @@ MemPDoPsSDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c
index f08fd34..2cb7a22 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c
@@ -161,4 +161,3 @@ MemPDoPsUDr2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c
index 778f4b9..14e7454 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c
@@ -156,4 +156,3 @@ MemPDoPsUDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c
index 2803a39..dd4d0d5 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c
@@ -162,4 +162,3 @@ MemPDoPsSLN3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c
index 2d261f8..728c588 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c
@@ -520,4 +520,3 @@ MemPPSCGen (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c
index be9033a..3a66c48 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c
@@ -228,5 +228,3 @@ MemConstructTechBlock2 (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.h
index 6966a7b..8472b43 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.h
@@ -120,5 +120,3 @@ MemTGetDimmSpdBuffer2 (
   );
 
 #endif  /* _MT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c
index a45a970..020629d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c
@@ -157,6 +157,3 @@ MemTGetLD2 (
 
   return LD;
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.h
index ac52ffe..a4b7386 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.h
@@ -84,5 +84,3 @@ MemTGetLD2 (
   );
 
 #endif  /* _MTOT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.h
index bd212d9..7de2dd3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.h
@@ -178,5 +178,3 @@
 
 
 #endif  /* _MTSPD2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.h
index 4eed7eb..9f9b186 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.h
@@ -130,5 +130,3 @@ MemTGetDimmSpdBuffer3 (
   IN       UINT8 Dimm
   );
 #endif  /* _MT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c
index e7a76dc..08bab6a 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c
@@ -1104,4 +1104,3 @@ MemTLrdimmSyncTrainedDlys (
     return FALSE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.h
index bb047b2..b427044 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.h
@@ -86,5 +86,3 @@ MemTGetLD3 (
   );
 
 #endif  /* _MTOT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c
index b1d5994..b7042f0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -302,4 +302,3 @@ FreqChgCtrlWrd3 (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.h
index e70d934..845d224 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.h
@@ -83,5 +83,3 @@ MemTDramControlRegInit3 (
   );
 
 #endif  /* _MTRCI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.h
index 883546e..480bb94 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.h
@@ -92,5 +92,3 @@ MemTEMRS23 (
   );
 
 #endif  /* _MTSDI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c
index dac3df3..4972c52 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -1153,4 +1153,3 @@ MemTGetDimmSpdBuffer3 (
   }
   return DimmPresent;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.h
index aaa6285..900b3d4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -172,5 +172,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c
index da42c63..1147afc 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -697,4 +697,3 @@ MemTExitPhyAssistedTrainingClient3 (
   }
   return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
index 9ae5fe0..45ed6b8 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c
@@ -907,4 +907,3 @@ MemTDataEyeSave (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.h
index 590eafd..0f834b3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.h
@@ -113,5 +113,3 @@ typedef struct _SWEEP_INFO {
 
 
 #endif  /* _MTTEDGEDETECT_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c
index 2f30178..c4fc174 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c
@@ -341,4 +341,3 @@ MemTDqsTrainRcvrEnSw (
   IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n");
   return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfParallelTraining.h
index 32ce395..ee98728 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfParallelTraining.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfParallelTraining.h
@@ -109,5 +109,3 @@ MemFParallelTraining (
  );
 
 #endif  /* _MFPARALLELTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfStandardTraining.h
index 36edf96..2b4e42e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfStandardTraining.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfStandardTraining.h
@@ -77,5 +77,3 @@ MemFStandardTraining (
   );
 
 #endif  /* _MFSTANDARDTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfmemclr.h
index 6c134c3..c94063d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfmemclr.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfmemclr.h
@@ -79,5 +79,3 @@ MemFMctMemClr_Sync (
   );
 
 #endif  /* _MFMEMCLR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mftds.h
index 089ba5f..c3f1510 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mftds.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mftds.h
@@ -76,5 +76,3 @@ MemFInitTableDrive (
   IN       UINT8     time
   );
 #endif  /* _MFTDS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mm.h
index 93476c4..debbb8b 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mm.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mm.h
@@ -1125,5 +1125,3 @@ AGESA_STATUS
 memDefRetSuccess (VOID);
 
 #endif  /* _MM_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h
index f211bd8..f1efa8c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h
@@ -1628,4 +1628,3 @@ MemNResetRxFifoPtrClientNb (
   );
 
 #endif  /* _MN_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mu.h
index 9fc8559..4d61e13 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mu.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mu.h
@@ -224,5 +224,3 @@ MemUnsToMemClk (
   IN       UINT32 NumberOfns
   );
 #endif  /* _MU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.c
index 233a862..fd51838 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.c
@@ -98,5 +98,3 @@ AmdCpuRecovery (
   LoadMicrocodePatch (&CpuRecoveryParams->StdHeader);
   return (AGESA_SUCCESS);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.h
index a8ab34d..b195e01 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/CPU/cpuRecovery.h
@@ -72,4 +72,3 @@ AmdCpuRecovery (
   );
 
 #endif // _CPU_RECOVERY_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/GnbRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/GnbRecovery.c
index fc8378a..59232f4 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/GnbRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/GNB/GnbRecovery.c
@@ -97,5 +97,3 @@ AmdGnbRecovery (
   GnbSetTom (NbPciAddress, StdHeader);
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitRecovery.c
index dced7d5..7e8e4ed 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/HT/htInitRecovery.c
@@ -160,4 +160,3 @@ AmdHtInitRecovery (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnc32.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnc32.h
index 7ff4822..d1e0679 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnc32.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnc32.h
@@ -104,5 +104,3 @@ MemRecNInitializeMctC32 (
   );
 
 #endif  /* _MRNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
index 0fa8447..8b3da63 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
@@ -56,5 +56,3 @@ RDATA_GROUP (G2_PEI)
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnda.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnda.h
index eea7fde..e90b89d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnda.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DA/mrnda.h
@@ -104,5 +104,3 @@ MemRecNInitializeMctDA (
   );
 
 #endif  /* _MRNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrndr.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrndr.h
index a76559a..280649c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrndr.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/DR/mrndr.h
@@ -104,5 +104,3 @@ MemRecNInitializeMctDR (
   );
 
 #endif  /* _MRNDR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnhy.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnhy.h
index 555b24f..e17d443 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnhy.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnhy.h
@@ -104,5 +104,3 @@ MemRecNInitializeMctHy (
   );
 
 #endif  /* _MRNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnprotohy.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
index 781695b..ef91aab 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
@@ -56,5 +56,3 @@ RDATA_GROUP (G2_PEI)
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrndctln.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrndctln.c
index 6a6fdb8..6b3c8a3 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrndctln.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrndctln.c
@@ -370,5 +370,3 @@ MemRecNAutoConfigLN (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnln.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnln.h
index cd0a82b..65c37b9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnln.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/LN/mrnln.h
@@ -127,5 +127,3 @@ MemRecNAutoConfigLN (
   );
 
 #endif  /* _MRNLN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/NI/mrnNi.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/NI/mrnNi.h
index 5c0f73f..5ec110e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/NI/mrnNi.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/NI/mrnNi.h
@@ -91,5 +91,3 @@ MemRecNSwitchChannelNi (
   );
 
 #endif  /* _MRNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/PH/mrnPh.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/PH/mrnPh.h
index d476f3b..266b83c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/PH/mrnPh.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/PH/mrnPh.h
@@ -91,5 +91,3 @@ MemRecNSwitchChannelPh (
   );
 
 #endif  /* _MRNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.h
index 26b9527..4a63963 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/RB/mrnRb.h
@@ -91,5 +91,3 @@ MemRecNSwitchChannelRb (
   );
 
 #endif  /* _MRNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c
index 502f5e2..c1b1023 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrn.c
@@ -185,4 +185,3 @@ MemRecNSetTrainDlyNb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c
index 86c68ae..36f62f0 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrndct.c
@@ -1573,4 +1573,3 @@ MemRecNCompareTestPatternUnb (
   Pass = ~Pass;
   return Pass;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrntrain3.c
index 507e8ab..055e38d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrntrain3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/NB/mrntrain3.c
@@ -155,4 +155,3 @@ MemNRecTrainingFlowUnb (
 
   MemRecTTrainRcvrEnHwSeedless (NBPtr->TechPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
index 87c2b7d..461b9ae 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
@@ -126,5 +126,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrc.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrc.c
index 129532f..c939009 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrc.c
@@ -326,4 +326,3 @@ MemRecTProgramRcvrEnDly (
   );
   return MaxDly;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
index da6bf9d..ce6671e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
@@ -311,4 +311,3 @@ MemRecTProgramRcvrEnDly (
 
   return MaxDly;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttpos.c
index 67ac527..e705c41 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttpos.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -109,5 +109,3 @@ MemRecTTrainDQSPosSw (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrdef.c
index 626cd1f..1004126 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrdef.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrdef.c
@@ -124,4 +124,3 @@ SetMemRecError (
     MCTPtr->ErrCode = Errorval;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrt3.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrt3.h
index 09e7b6c..12e5b87 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrt3.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mrt3.h
@@ -115,5 +115,3 @@ MemRecTDramControlRegInit3 (
   );
 
 #endif  /* _MRT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mru.h b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mru.h
index a2d17ce..1bf3f32 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mru.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mru.h
@@ -134,5 +134,3 @@ RecGetMaxDimmsPerChannel (
   );
 
 #endif  /* _MRU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mruc.c
index d0fa900..b009f1f 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mruc.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Recovery/Mem/mruc.c
@@ -262,4 +262,3 @@ MemRecFindPSOverrideEntry (
   }
   return NULL;
 }
-
diff --git a/src/vendorcode/amd/agesa/f12/cpcar.inc b/src/vendorcode/amd/agesa/f12/cpcar.inc
index acb2636..0867ae7 100644
--- a/src/vendorcode/amd/agesa/f12/cpcar.inc
+++ b/src/vendorcode/amd/agesa/f12/cpcar.inc
@@ -1297,6 +1297,3 @@ GET_NODE_ID_CORE_ID_F15 MACRO
     .endif
 node_core_f15_exit:
 ENDM
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
index 22564cb..2de5e8d 100644
--- a/src/vendorcode/amd/agesa/f12/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f12/gcccar.inc
@@ -1603,4 +1603,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h b/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
index 9e975ae..ba2b8cf 100644
--- a/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
@@ -98,4 +98,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/DanNiInstall.h b/src/vendorcode/amd/agesa/f14/Include/DanNiInstall.h
index 14a32fa..e834e5c 100644
--- a/src/vendorcode/amd/agesa/f14/Include/DanNiInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/DanNiInstall.h
@@ -114,4 +114,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/DanubeInstall.h b/src/vendorcode/amd/agesa/f14/Include/DanubeInstall.h
index 0230bf7..cb06552 100644
--- a/src/vendorcode/amd/agesa/f14/Include/DanubeInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/DanubeInstall.h
@@ -99,4 +99,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/DevTestInstall.h b/src/vendorcode/amd/agesa/f14/Include/DevTestInstall.h
index c8d0ee8..0b74585 100644
--- a/src/vendorcode/amd/agesa/f14/Include/DevTestInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/DevTestInstall.h
@@ -108,4 +108,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/DragonInstall.h b/src/vendorcode/amd/agesa/f14/Include/DragonInstall.h
index a4edad9..dce29ee 100644
--- a/src/vendorcode/amd/agesa/f14/Include/DragonInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/DragonInstall.h
@@ -99,4 +99,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/LynxInstall.h b/src/vendorcode/amd/agesa/f14/Include/LynxInstall.h
index 2a0c963..8296c56 100644
--- a/src/vendorcode/amd/agesa/f14/Include/LynxInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/LynxInstall.h
@@ -99,4 +99,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/f14/Include/MaranelloInstall.h
index c11f2f5..5a5bd1e 100644
--- a/src/vendorcode/amd/agesa/f14/Include/MaranelloInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/MaranelloInstall.h
@@ -115,4 +115,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/NileInstall.h b/src/vendorcode/amd/agesa/f14/Include/NileInstall.h
index 441c854..705cfc2 100644
--- a/src/vendorcode/amd/agesa/f14/Include/NileInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/NileInstall.h
@@ -99,4 +99,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/SabineInstall.h b/src/vendorcode/amd/agesa/f14/Include/SabineInstall.h
index c0b7c65..23b1b2d 100644
--- a/src/vendorcode/amd/agesa/f14/Include/SabineInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/SabineInstall.h
@@ -114,4 +114,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/SanMarinoInstall.h b/src/vendorcode/amd/agesa/f14/Include/SanMarinoInstall.h
index a4cb467..cd71452 100644
--- a/src/vendorcode/amd/agesa/f14/Include/SanMarinoInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/SanMarinoInstall.h
@@ -115,4 +115,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/ScorpiusInstall.h b/src/vendorcode/amd/agesa/f14/Include/ScorpiusInstall.h
index f6ee192..cb24d95 100644
--- a/src/vendorcode/amd/agesa/f14/Include/ScorpiusInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/ScorpiusInstall.h
@@ -114,4 +114,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Include/TigrisInstall.h b/src/vendorcode/amd/agesa/f14/Include/TigrisInstall.h
index 8256f6d..5c8fc21 100644
--- a/src/vendorcode/amd/agesa/f14/Include/TigrisInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/TigrisInstall.h
@@ -99,4 +99,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/amd.inc b/src/vendorcode/amd/agesa/f14/Legacy/amd.inc
index b716202..24619d8 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/amd.inc
+++ b/src/vendorcode/amd/agesa/f14/Legacy/amd.inc
@@ -458,4 +458,3 @@ ENDIF
 IFNDEF   BIT63
     BIT63                       EQU    8000000000000000h
 ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
index cece9dc..a8bab56 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
@@ -179,4 +179,3 @@ SetAsymBoost (
   ((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
   LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
index 609cc21..78c4961 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
@@ -76,4 +76,3 @@ F10PmAsymBoostInit (
   );
 
 #endif  // _CPU_F10_ASYM_BOOST_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
index da77c29..3381524 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
@@ -243,4 +243,3 @@ SetPstateMSR (
   }
   return (LowestPsEn);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
index dcd5d4f..b3d42f5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
@@ -76,4 +76,3 @@ F10PmDualPlaneOnlySupport (
   );
 
 #endif  // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index d5b515f..c957405 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -297,4 +297,3 @@ PmNbCofVidInitWarmCore (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index 50b7238..c312319 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -185,4 +185,3 @@ PmNbPstateInitCore (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
index 3fd8c61..c9bd666 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -104,4 +104,3 @@ GetF10BlMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
index bfbd19e..7f7a15f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
@@ -104,4 +104,3 @@ GetF10BlLogicalIdAndRev (
 //  (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
 //  (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
 //};
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
index 762c2ea..a8e96f2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -104,4 +104,3 @@ GetF10BlMicroCodePatchesStruct (
   *NumberOfElements = CpuF10BlNumberOfMicrocodePatches;
   *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
index e08498e..f9f96ff 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -105,4 +105,3 @@ GetF10DaMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
index 26d5460..9ec4202 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
@@ -105,4 +105,3 @@ GetF10DaLogicalIdAndRev (
 //  (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
 //  (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
 //};
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
index 96438f6..c930db7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -104,4 +104,3 @@ GetF10DaMicroCodePatchesStruct (
   *NumberOfElements = CpuF10DaNumberOfMicrocodePatches;
   *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index 8f324a9..be99dd6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -433,4 +433,3 @@ F10CommonRevCGetNumberOfCoresForBrandstring (
   LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
   return (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo + 1);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
index d657152..0c5912f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -107,5 +107,3 @@ GetF10RbMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
index 9f5c9c8..ca66ef4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
@@ -118,4 +118,3 @@ CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
   (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10RbHtPhyRegisters
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
index 2364217..a1e7f89 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -104,4 +104,3 @@ GetF10RbMicroCodePatchesStruct (
   *NumberOfElements = CpuF10RbNumberOfMicrocodePatches;
   *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
index bfe0eb1..c88d1ec 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
@@ -232,4 +232,3 @@ CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
   (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10RbPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index c53e7d5..945076f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -367,4 +367,3 @@ F10CommonRevDGetNumberOfCoresForBrandstring (
   }
   return ((UINT8) CmpCap);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
index eb0c8bc..d13edcd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -104,4 +104,3 @@ GetF10HyMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
index 4e1c775..c530826 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
@@ -106,4 +106,3 @@ GetF10HyLogicalIdAndRev (
   *HyIdPtr = CpuF10HyLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_10_HY;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
index 8c148ac..f414aed 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -104,4 +104,3 @@ GetF10HyMicroCodePatchesStruct (
   *NumberOfElements = CpuF10HyNumberOfMicrocodePatches;
   *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
index 1dc9e93..4b2fffe 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
@@ -134,5 +134,3 @@ CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
   (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
index d44dc46..8d9abac 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
@@ -347,4 +347,3 @@ CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = {
   (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10HyPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
index ad73fa5..2520917 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
@@ -103,4 +103,3 @@ GetF10PhMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10PhMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *PhEquivalenceTablePtr = CpuF10PhMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
index 32a574a..a8006d8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
@@ -94,4 +94,3 @@ GetF10PhLogicalIdAndRev (
   *PhIdPtr = CpuF10PhLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_10_PH;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
index 59522a4..bfcd52d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
@@ -103,4 +103,3 @@ GetF10PhMicroCodePatchesStruct (
   *NumberOfElements = CpuF10PhNumberOfMicrocodePatches;
   *PhUcodePtr = &CpuF10PhMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c
index c696f4f..1bffef2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -142,4 +142,3 @@ GetF10BrandIdString2 (
   *BrandString2Ptr = TableEntryPtr;
   *NumberOfElements = F10BrandIdString2TableCount;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
index 2486284..42beb93 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
@@ -330,4 +330,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = {
   (sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayAm3
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
index d8ab245..a4b6915 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
@@ -133,6 +133,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = {
   (sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayAsb2
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
index fb0249c..847c056 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
@@ -131,4 +131,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = {
   (sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayC32
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
index a02dedc..a407ac1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
@@ -172,4 +172,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayFr1207 = {
   (sizeof (CpuF10BrandIdString2ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayFr1207
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
index 833a13b..2c8e740 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
@@ -125,4 +125,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34 = {
   (sizeof (CpuF10BrandIdString2ArrayG34) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayG34
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
index 8e0145d..8ec5f92 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
@@ -126,4 +126,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3 = {
   (sizeof (CpuF10BrandIdString2ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayS1g3
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
index 990884a..f34052f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
@@ -140,5 +140,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4 = {
   (sizeof (CpuF10BrandIdString2ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayS1g4
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
index 4f88c9d..be2e024 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -124,4 +124,3 @@ GetF10CacheInfo (
   *NumberOfElements = 1;
   *CacheInfoPtr = &CpuF10CacheInfo;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
index ad00e44..2661167 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -475,4 +475,3 @@ F10Translate7BitVidTo6Bit (
     *MaxVidPtr = (*MaxVidPtr & 0x7E) >> 1;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
index cca3ccd..5860f10 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -391,4 +391,3 @@ updateCpuFeatureList (
     thisCoreFeatureList++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
index cac7569..390b385 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
@@ -749,4 +749,3 @@ CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable = {
   (sizeof (F10HtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10HtPhyRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10MsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10MsrTables.c
index 34dbac0..f9f9e05 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10MsrTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10MsrTables.c
@@ -272,4 +272,3 @@ CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable = {
   (sizeof (F10MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *)F10MsrRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index f469f1d..c9f1e40 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -418,4 +418,3 @@ F10PmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrReg, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrReg, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
index 55e715d..002ad00 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
@@ -545,4 +545,3 @@ typedef struct {
 /* Boost Offset Register F3x10C */
 #define F3x10C_REG 0x10C
 #define F3x10C_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, F3x10C_REG))
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
index dbfe2d9..5c24a9c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -860,4 +860,3 @@ F10GetFrequencyXlatRegInfo (
 
   return AGESA_ERROR;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
index 09973fb..877d3ba 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -1115,5 +1115,3 @@ F10SetHtPhyRegister (
     LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
   } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
index 2673af7..bed1ca6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
@@ -130,6 +130,3 @@ GetF14OnMicrocodeEquivalenceTable (
     *OnEquivalenceTablePtr = CpuF14MicrocodeEquivalenceTable;
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
index e44f07f..e1df9a3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
@@ -314,4 +314,3 @@ F14OnProductionErrataAtEarly (
     LibAmdMsrWrite (MSR_LS_CFG, &MsrValue, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h
index efe95ca..2fa3077 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h
@@ -66,4 +66,3 @@ typedef enum {
   ON_ERRATUM463_WORKAROUND_DISABLE = 0, ///< work around disable
   ON_ERRATUM463_WORKAROUND_ENABLE = 1, ///< work around enable
 } ON_ERRATUM463_WORKAROUND;
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
index fa702f6..4d0fd87 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
@@ -111,4 +111,3 @@ GetF14OnLogicalIdAndRev (
   *OnIdPtr = CpuF14OnLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_14_ON;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
index 8cad6a4..9582060 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
@@ -107,4 +107,3 @@ GetF14OnMicroCodePatchesStruct (
   *NumberOfElements = CpuF14OnNumberOfMicrocodePatches;
   *OnUcodePtr = &CpuF14OnMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
index 4ed896b..4a39d80 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
@@ -157,5 +157,3 @@ CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1 = {
   (sizeof (CpuF14OnBrandIdString2ArrayFt1) / sizeof (AMD_CPU_BRAND)),
   CpuF14OnBrandIdString2ArrayFt1
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
index 467ecfa..9d318f7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
@@ -128,4 +128,3 @@ GetF14CacheInfo (
   *NumberOfElements = 1;
   *CacheInfoPtr = &CpuF14CacheInfo;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c
index 7f7776d..812b0ff 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c
@@ -209,5 +209,3 @@ CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable = {
   (sizeof (F14MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *) &F14MsrRegisters,
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
index f0f519b..af0f611 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
@@ -451,4 +451,3 @@ F14PmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h
index 145a0cb..e601e15 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h
@@ -225,4 +225,3 @@
 // TBD
 
 #endif      // _CPU_FAM_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
index f5772e9..fa1dbd1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
@@ -740,5 +740,3 @@ IsPowerOfTwo (
   }
   return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.h
index eadf9ff..2f3de3d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.h
@@ -131,4 +131,3 @@ AllocateExecutionCache (
   );
 
 #endif  // _CPU_CACHE_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c
index 21d3e9b..703240f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -350,4 +350,3 @@ CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
  *                          L O C A L      F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c
index b43165f..1a1d5f9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c
@@ -700,4 +700,3 @@ IntToString (
   }
   *(String + SizeInByte * 2) = 0x0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c
index 0b3b3f2..795f243 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c
@@ -574,4 +574,3 @@ STATIC
   }
   return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
 } // MakeMemEntry()
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c
index 2c6e18c..b8e0c6c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c
@@ -282,4 +282,3 @@ CreateHestBank (
     HestBankPtr++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
index 2d33021..55d3040 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h
@@ -1235,4 +1235,3 @@ GetPerformanceFeatures (
   );
 
 #endif  // _CPU_TABLE_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.h
index acc47a5..06c1417 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.h
@@ -259,4 +259,3 @@ RelinquishControlOfAllAPs (
   );
 
 #endif  /* _CPU_APIC_UTILITIES_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h
index ba923c5..e406bdd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h
@@ -247,4 +247,3 @@ LoadMicrocodePatch (
   IN OUT   AMD_CONFIG_PARAMS *StdHeader
   );
 #endif  // _CPU_EARLY_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h
index c74996a..e9c48e3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h
@@ -954,4 +954,3 @@ GetEmptyArray (
   );
 
 #endif  // _CPU_FAMILY_TRANSLATION_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.h
index f423b8c..78c5bcb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.h
@@ -225,4 +225,3 @@ SetCoresTscFreqSel (
   IN       AMD_CONFIG_PARAMS   *StdHeader
   );
 #endif  // _CPU_POST_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c
index 21c4c25..9bb2d36 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -248,4 +248,3 @@ GetEarlyPmErrorsSingle (
 
   return (ReturnCode);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSystemTables.h
index a533171..b56f939 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSystemTables.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSystemTables.h
@@ -91,4 +91,3 @@ typedef struct {
 
 
 #endif  // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h
index 7d43c17..b7e6bf7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h
@@ -391,4 +391,3 @@ typedef struct {
 } IDT_BASE_LIMIT;
 
 #endif      // _CPU_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c
index fbb7cbb..33aaafa 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c
@@ -234,4 +234,3 @@ SetWarmResetAtEarly (
  *                            L O C A L    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
index 800f10b..d8edd9c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
@@ -850,5 +850,3 @@ HeapGetCurrentBase (
   ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE));
   return ReturnPtr;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c
index 8a540cd..16b1684 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c
@@ -173,5 +173,3 @@ AmdInitEnv (
   IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
   return  AmdInitEnvStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c
index 93b5317..9005cee 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c
@@ -306,4 +306,3 @@ AmdInitLate (
   IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader);
   return  AmdInitLateStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c
index 2af106c..4eefff3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c
@@ -159,5 +159,3 @@ AmdInitMid (
   IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader);
   return AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c
index ea4802d..ca60ca6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c
@@ -342,4 +342,3 @@ AmdInitPost (
 
   return  AmdInitPostStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c
index 7b75aad..ae0f12f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c
@@ -253,4 +253,3 @@ AmdInitResetConstructor (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c
index 9a1c99e..3532697 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c
@@ -158,4 +158,3 @@ AmdLateRunApTaskInitializer (
   AmdApExeParams->RelatedBlockLength = 0;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c
index 286647c..32600e8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c
@@ -135,4 +135,3 @@ CommonPlatformConfigInit (
   }
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.h
index 34f3c93..ae6519b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.h
@@ -63,4 +63,3 @@ CommonPlatformConfigInit (
   );
 
 #endif // _COMMON_INITS_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h
index ace0176..b652ad8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h
@@ -194,4 +194,3 @@ AmdLateRunApTaskInitializer (
   IN OUT   AP_EXE_PARAMS     *AmdApExeParams
   );
 #endif // _CREATE_STRUCT_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
index e8350a3..42f8d22 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3RestoreState.c
@@ -440,4 +440,3 @@ S3RestoreStateFromTable (
   IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h
index 6391009..238ff1f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h
@@ -83,4 +83,3 @@ typedef struct  {
 #pragma pack (pop)
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
index a974108..00caa29 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
@@ -636,4 +636,3 @@ TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = {
   sizeof (CnbToGncRegisterCopyTable) / sizeof (REGISTER_COPY_ENTRY),
   CnbToGncRegisterCopyTable
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h
index 5ce0c70..ac9a316 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h
@@ -64,4 +64,3 @@ GfxFmGmcAllowPstateHigh (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
index 7929d02..03f6141 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c
@@ -803,4 +803,3 @@ GfxGmcInit (
   IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n");
   return  Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.h
index 106ed57..c04f17a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.h
@@ -53,4 +53,3 @@ GfxInitAtMidPost (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.h
index 71041e6..34a6630 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.h
@@ -53,4 +53,3 @@ GfxInitAtPost (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h
index db57043..4f5cd08 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h
@@ -70,4 +70,3 @@ GfxSetBootUpVoltage (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c
index 8eea87e..3723a4c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c
@@ -93,4 +93,3 @@ GnbInitAtEarly (
   Status = GnbLibDispatchFeatures (&GnbEarlyFeatureTable[0], &EarlyParamsPtr->StdHeader);
   return  Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h
index e2a4d34..2f22a8c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h
@@ -1855,4 +1855,3 @@
  *</table>
  *</div>
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index 5facb18..d4eac92 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -465,5 +465,3 @@ GnbLibFind (
   }
   return NULL;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
index 1583eb3..96ef8c0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -127,5 +127,3 @@ GnbLibCpuPciIndirectWrite (
     GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
   } while ((OffsetRegisterValue & BIT31) == 0);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
index e6e7c03..b3ff4b1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -127,4 +127,3 @@ GnbLocateHeapBuffer (
   }
   return LocHeapParams.BufferPtr;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
index 7440ba2..fd045c6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -120,4 +120,3 @@ GnbLibIoRead (
 {
   LibAmdIoRead (Width, Address, Value, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
index 64679b4..cafab6c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -120,7 +120,3 @@ GnbLibMemRead (
 {
   LibAmdMemRead (Width, Address, Value, StdHeader);
 }
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
index b276382..2493940 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
@@ -414,4 +414,3 @@ PcieAlibSetPortInfoCallback (
   PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug;
   PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
index ab67b9e..d3f5f5e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
@@ -357,4 +357,3 @@
       Store (Local0, ABDA)
     }
   }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
index 5fa1a97..d75d83a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
@@ -451,5 +451,3 @@ Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16})
     Stall (10)
     Store ("PcieLaneEnableControl Exit", Debug)
   }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
index 6a7e19d..d03f9dd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
@@ -66,4 +66,3 @@ PcieRebaseConfigurationData (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
index 2182ba0..d5beb44 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
@@ -120,4 +120,3 @@ PcieConfigRunProcForAllWrappers (
   IN       PCIe_PLATFORM_CONFIG          *Pcie
   );
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
index 468a80e..4ab1c44 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -224,4 +224,3 @@ PcieInputParserGetEngineDescriptor (
     return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
index 9890755..1970693 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
@@ -72,4 +72,3 @@ PcieInputParserGetEngineDescriptor (
 
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
index 77ae9c3..1b39c24 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -723,4 +723,3 @@ PcieComplexConfigConfigDump (
   }
   IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
index e9a8274..54cb7f5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
@@ -54,5 +54,3 @@ PcieMapTopologyOnComplex (
  );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
index f5693f4..6496d2a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
@@ -189,4 +189,3 @@ PcieAspmGetMaxExitLatencyCallback (
   }
   return SCAN_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
index c606583..b68d046 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -228,4 +228,3 @@ PciePortRegisterRMW (
   Value = (Value & (~AndMask)) | OrMask;
   PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
index ac23548..ae1fc40 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
@@ -402,4 +402,3 @@ PcieForceCompliance (
       );
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
index 9cf7a62..67cecab 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
@@ -97,5 +97,3 @@ PciePifSetPllModeForL1 (
   IN      PCIe_PLATFORM_CONFIG  *Pcie
   );
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
index 5cf003f..c9f4218 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
@@ -347,5 +347,3 @@ PciePwrClockGating (
   }
   IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
index b24b37b..ad8dc58 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
@@ -221,4 +221,3 @@ PcieSbLinkVcEnable (
 {
 
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
index 546fcbb..f398e5c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
@@ -252,4 +252,3 @@ PcieSiliconHidePorts (
     GnbLibGetHeader (Pcie)
     );
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
index 1e36aed..7a655ee 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
@@ -130,5 +130,3 @@ PcieWrapSetTxOffCtrlForLaneMux (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
index 2d4381d..dec9c1c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
@@ -61,4 +61,3 @@ PcieTrainingSetPortState (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
index f80f445..3c722f9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
@@ -372,5 +372,3 @@ PcieIsDeskewCardDetected (
   }
   return FALSE;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
index 827bd7f..ceecc4a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
@@ -345,4 +345,3 @@ NbFmDpmStateBootupInit (
   }
   return LclkDpmValidState;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
index 6f196c8..49f6f91 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
@@ -1450,4 +1450,3 @@ SMU_FIRMWARE_HEADER Fm = {
   &FmBlockArray[0]
 };
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h
index 4d0f185..e90b6ba 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h
@@ -112,4 +112,3 @@ NbFmInitLclkDpmRcActivity (
   IN      AMD_CONFIG_PARAMS   *StdHeader
   );
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c
index 458bd80..881e957 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c
@@ -231,4 +231,3 @@ NbInitOnPowerOn (
 
   return  AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c
index d4c90c7..545f85c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c
@@ -119,5 +119,3 @@ NbInitAtEarly (
   IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Exit[0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.h
index 433eb43..12b1b65 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.h
@@ -53,6 +53,3 @@ NbInitAtEnv (
   );
 
 #endif
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.h
index 3f56a33..367cd99 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.h
@@ -53,4 +53,3 @@ NbInitAtLatePost (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c
index 57280a1..120e153 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c
@@ -118,5 +118,3 @@ NbInitAtPost (
   IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Exit[0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
index fbfea63..7e92941 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
@@ -142,5 +142,3 @@ DefinitionBlock (
     }
   } //End of Scope(\_SB)
 }   //End of DefinitionBlock
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
index 88937c6..9d2ce67 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
@@ -122,5 +122,3 @@ PcieFmBuildComplexConfiguration (
 
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
index 3f2a5bc..e371fe9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
@@ -242,4 +242,3 @@ PcieFmEnableSlotPowerLimit (
     );
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/PcieFamilyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/PcieFamilyServices.h
index df2837d..fb31179 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/PcieFamilyServices.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/PcieFamilyServices.h
@@ -132,4 +132,3 @@ PcieFmPhyLaneInitInitCallback (
   IN      PCIe_PLATFORM_CONFIG  *Pcie
   );
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
index b83afea..29e098f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
@@ -372,4 +372,3 @@ PciePostInit (
   IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.h
index 6eaccea..f4c1c1a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.h
@@ -63,5 +63,3 @@ PciePortsVisibilityControl (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
index 9b5ae2f..f227d2e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
@@ -122,4 +122,3 @@ PcieInitAtEarly (
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.h
index 047db0f..207e6b0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.h
@@ -53,4 +53,3 @@ PcieLateInit (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c
index f218741..525400d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c
@@ -156,4 +156,3 @@ PcieUtilGlobalGenCapability (
 
   return GlobalCapability;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h
index ad0502b..f73412e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h
@@ -67,5 +67,3 @@ PciePortPostS3Init (
   IN       PCIe_PLATFORM_CONFIG  *Pcie
   );
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c
index 2bdf406..ac74e4a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c
@@ -399,4 +399,3 @@ Fam10RevDBufferOptimizations (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.h
index 112f771..b5d8444 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.h
@@ -76,5 +76,3 @@ CoherentDiscovery (
   );
 
 #endif  /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.h
index 30a7732..c2fa217 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.h
@@ -76,5 +76,3 @@ RegangLinks (
   );
 
 #endif  /* _HT_FEAT_GANGING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.h
index d4583ea..cdb760f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.h
@@ -86,5 +86,3 @@ MakeHopCountTable (
   );
 
 #endif  /* _HT_FEAT_ROUTING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.h
index 9c67f0e..4cf3e3d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.h
@@ -76,5 +76,3 @@ SubLinkRatioFixup (
   );
 
 #endif  /* _HT_FEAT_SUBLINKS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.h
index f482a8a..482adfc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.h
@@ -75,5 +75,3 @@ TrafficDistribution (
   );
 
 #endif  /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c
index 9b19010..aebd64a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c
@@ -150,4 +150,3 @@ HtIdsGetPortOverride (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.h
index b65fc8d..3fee385 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.h
@@ -175,4 +175,3 @@ HandleSpecialNodeCase (
   IN       STATE_DATA  *State,
   IN       NORTHBRIDGE *Nb
   );
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph.h
index e20d6b0..30ffe81 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph.h
@@ -141,4 +141,3 @@ GraphGetBc (
   );
 
 #endif  /* _HT_GRAPH_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c
index bcdfc13..2cd1d1c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c
@@ -196,4 +196,3 @@ GraphGetBc (
   ASSERT ((NodeA < size) && (NodeB < size));
   return Graph[1 + (NodeA*size + NodeB)*2];
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8Ladder.c
index 332a459..ff991ee 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8Ladder.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8Ladder.c
@@ -93,4 +93,3 @@ CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
   0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x90, 0xFF,  0x00, 0x77, // Node6
   0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x66,  0x60, 0xFF  // Node7
 };
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c
index 43a0ba7..49573c0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c
@@ -391,4 +391,3 @@ GetOverrideBusNumbers (
   // SecBus, SubBus are not valid if Result is FALSE.
   return result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c
index cc96906..9443fa2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c
@@ -244,4 +244,3 @@ NewNorthBridge (
   // Set the config handle for passing to the library.
   Nb->ConfigHandle = State->ConfigHandle;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h
index 2c135f2..fd6dc86 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h
@@ -125,4 +125,3 @@ typedef enum {
 #define IDS_CPB_BOOST_DIS_IGNORE  0xFFFFFFFF
 
 #endif //_IDS_LIB_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h
index 51d8282..7b88f1f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h
@@ -78,5 +78,3 @@ MemFInterleaveChannels (
   );
 
 #endif  /* _MFCHI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h
index f019773..dbe44c5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -78,5 +78,3 @@ MemFInterleaveBanks (
   );
 
 #endif  /* _MFCSI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
index 2d7151d..c0cb26a5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
@@ -580,4 +580,3 @@ MemFDMISupport2 (
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h
index 7f11334..fa5831f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h
@@ -78,5 +78,3 @@ MemFInitECC (
   );
 
 #endif  /* _MFECC_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 872bd1e..b74ee16 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -201,4 +201,3 @@ MemFRASExcludeDIMM (
   NBPtr->SwitchDCT (NBPtr, ReserveDCT);
   return RetVal;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index d834cc1..34ac90f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -148,5 +148,3 @@ MemFInterleaveRegion (
     }
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
index 52aac8f..400b369 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
@@ -78,5 +78,3 @@ MemFInterleaveRegion (
   );
 
 #endif  /* _MFINTLVRN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index 71c2219..c7b7849 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -141,4 +141,3 @@ MemFMctMemClr_Sync (
   }
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h
index e8ff3b1..1c13b3b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h
@@ -76,5 +76,3 @@ MemFInterleaveNodes (
   );
 
 #endif  /* _MFNDI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h
index dacc143..b99b211 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h
@@ -77,5 +77,3 @@ MemFOnlineSpare (
   );
 
 #endif  /* _MFSPR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c
index 0608575..b942cca 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c
@@ -316,9 +316,3 @@ SetTableValues (
     }
   }
 }
-
-
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c
index b2beeb1..3302ef6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/merrhdl.c
@@ -186,4 +186,3 @@ MemErrHandle (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
index 19fdbbe..adc9350 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
@@ -245,4 +245,3 @@ MemMUmaAlloc (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm
index 63c85b9..a4cacd7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm
@@ -494,4 +494,3 @@ MemUMFenceInstr PROC CALLCONV PUBLIC
 MemUMFenceInstr ENDP
 
     END
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c
index 8945652..267549f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c
@@ -482,4 +482,3 @@ memNEnableTrainSequenceC32 (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h
index 6dc6376..808250f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h
@@ -192,5 +192,3 @@ memNEnableTrainSequenceC32 (
   );
 
 #endif  /* _MNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c
index 7fa502d..755006c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c
@@ -133,4 +133,3 @@ MemNPlatformSpecificFormFactorInitC32 (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c
index 17057ab..67da2a4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c
@@ -487,4 +487,3 @@ memNEnableTrainSequenceDA (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h
index d6957e7..3ed253f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h
@@ -206,5 +206,3 @@ MemNPlatformSpecificFormFactorInitNi (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c
index 11d0c2f..f6f18ce 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c
@@ -137,4 +137,3 @@ MemNPlatformSpecificFormFactorInitDA (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c
index 713bddf..cb467f9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c
@@ -196,6 +196,3 @@ MemNPowerDownCtlDA (
     }
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c
index 8d4a742..3dddaf5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c
@@ -84,4 +84,3 @@ MemPNodeMemBoundaryDA (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c
index 085356b..ed377d9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c
@@ -512,4 +512,3 @@ MemNProgramCycTimingsDr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c
index c31913a..cec9d66 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c
@@ -137,6 +137,3 @@ MemNPlatformSpecificFormFactorInitDr (
  *
  *----------------------------------------------------------------------------
  */
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c
index ce0eebb..4f39439 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c
@@ -195,6 +195,3 @@ MemNPowerDownCtlDR (
     }
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c
index 1b3af82..57665b2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c
@@ -167,4 +167,3 @@ MemPNodeMemBoundaryDr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c
index 1ac0db1..c5a1c6c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c
@@ -132,4 +132,3 @@ MemNPlatformSpecificFormFactorInitHy (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c
index 6408058..19c5e46 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c
@@ -484,4 +484,3 @@ memNEnableTrainSequenceHy (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h
index 5040765..2f7417e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h
@@ -198,5 +198,3 @@ MemNSendMrsCmdPerCsHy (
   );
 
 #endif  /* _MNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c
index c8782bc..aa66fdc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c
@@ -492,4 +492,3 @@ memNEnableTrainSequenceNi (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h
index e153041..fa8b1fb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h
@@ -110,5 +110,3 @@ memNEnableTrainSequenceNi (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c
index fdabf0f..18ed215 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c
@@ -138,4 +138,3 @@ MemNPlatformSpecificFormFactorInitNi (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
index 334942b..ba9851b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
@@ -166,4 +166,3 @@ MemNTechBlockSwitchON (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
index a0703cc..ffc058a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
@@ -460,5 +460,3 @@ memNEnableTrainSequenceON (
   }
   return Retval;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
index 8d71f3d..491326c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
@@ -252,5 +252,3 @@ MemNResetRxFifoPtrON (
   IN OUT   VOID *OptParam
   );
 #endif  /* _MNON_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c
index 40a1dd6..1319386 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c
@@ -491,4 +491,3 @@ memNEnableTrainSequencePh (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h
index 8b7bdb4..f3065ee 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h
@@ -121,5 +121,3 @@ memNEnableTrainSequencePh (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c
index 59a46dc..1e0463a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c
@@ -139,4 +139,3 @@ MemNPlatformSpecificFormFactorInitPh (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c
index 69e111e..85cbdaf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c
@@ -491,4 +491,3 @@ memNEnableTrainSequenceRb (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h
index 445da83..a4b3939 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h
@@ -121,5 +121,3 @@ memNEnableTrainSequenceRb (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c
index 38e5812..86b2b46 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c
@@ -139,4 +139,3 @@ MemNPlatformSpecificFormFactorInitRb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
index 7fb195d..0458e8f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
@@ -926,4 +926,3 @@ MemNS3GetDummyReadAddr (
 
   return AddrFound;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
index 0bec481..9379ac7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
@@ -1290,4 +1290,3 @@ MemNInitCPGUnb (
   NBPtr->FamilySpecificHook[SetupHwTrainingEngine] = MemNSetupHwTrainingEngineUnb;
   NBPtr->CPGInit = 0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c
index 245943f..a696152 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c
@@ -265,4 +265,3 @@ MemNCleanupDctRegsNb (
     MemNSetBitFieldNb (NBPtr, BitField, 0);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c
index 101c3ec..9146353 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c
@@ -433,5 +433,3 @@ MemNPollBitFieldNb (
     MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c
index 8009a65..1605dfb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c
@@ -158,4 +158,3 @@ MemPDoPsSDA2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c
index cfc00bc..2beb310 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c
@@ -163,4 +163,3 @@ MemPDoPsRDr2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c
index 38a83b0..180cb66 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c
@@ -202,4 +202,3 @@ MemPDoPsRDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c
index b9e914a..6f1aca6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c
@@ -189,4 +189,3 @@ MemPDoPsSDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c
index dfa4bd2..7d63829 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c
@@ -163,4 +163,3 @@ MemPDoPsUDr2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c
index 53e962d..06b7a46 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c
@@ -158,4 +158,3 @@ MemPDoPsUDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c
index 1b40102..966e16f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c
@@ -507,4 +507,3 @@ MemPPSCGen (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c
index 5bdc190..77949e3 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c
@@ -230,5 +230,3 @@ MemConstructTechBlock2 (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h
index f963d94..d349863 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h
@@ -122,5 +122,3 @@ MemTGetDimmSpdBuffer2 (
   );
 
 #endif  /* _MT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c
index 99799d8..ef7580b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c
@@ -159,6 +159,3 @@ MemTGetLD2 (
 
   return LD;
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h
index 20f0b6e..f717fe4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h
@@ -86,5 +86,3 @@ MemTGetLD2 (
   );
 
 #endif  /* _MTOT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h
index 92292dc..15667a4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h
@@ -180,5 +180,3 @@
 
 
 #endif  /* _MTSPD2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h
index cf5a26c..12b5169 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h
@@ -132,5 +132,3 @@ MemTGetDimmSpdBuffer3 (
   IN       UINT8 Dimm
   );
 #endif  /* _MT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c
index d556549..c9616d2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c
@@ -1099,4 +1099,3 @@ MemTLrdimmSyncTrainedDlys (
     return FALSE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h
index 9caca54..8c8de15 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h
@@ -88,5 +88,3 @@ MemTGetLD3 (
   );
 
 #endif  /* _MTOT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
index 85d052c..c2e803e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -295,4 +295,3 @@ FreqChgCtrlWrd3 (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h
index 540af2c..30096c4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h
@@ -85,5 +85,3 @@ MemTDramControlRegInit3 (
   );
 
 #endif  /* _MTRCI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h
index 8c6c0b5..9480b1c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h
@@ -94,5 +94,3 @@ MemTEMRS23 (
   );
 
 #endif  /* _MTSDI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
index ea9cabc..95d706c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -1150,4 +1150,3 @@ MemTGetDimmSpdBuffer3 (
   }
   return DimmPresent;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h
index 3b37429..58e9943 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -173,5 +173,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c
index 8d8b6b6..b5c11ce 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -683,4 +683,3 @@ MemTExitPhyAssistedTrainingClient3 (
   }
   return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
index f1fa73e..5d8e0bc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c
@@ -893,4 +893,3 @@ MemTDataEyeSave (
     ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm];
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h
index 2aa9d60..0818dd0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h
@@ -115,5 +115,3 @@ typedef struct _SWEEP_INFO {
 
 
 #endif  /* _MTTEDGEDETECT_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c
index be647ea..41648f5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttsrc.c
@@ -343,4 +343,3 @@ MemTDqsTrainRcvrEnSw (
   IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n");
   return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h
index 8f5025e..bfe584d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfParallelTraining.h
@@ -111,5 +111,3 @@ MemFParallelTraining (
  );
 
 #endif  /* _MFPARALLELTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfStandardTraining.h
index b0ea9e5..e850560 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfStandardTraining.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfStandardTraining.h
@@ -79,5 +79,3 @@ MemFStandardTraining (
   );
 
 #endif  /* _MFSTANDARDTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h
index 337ee4a..aee3bcf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h
@@ -81,5 +81,3 @@ MemFMctMemClr_Sync (
   );
 
 #endif  /* _MFMEMCLR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h
index 687cfde..c68fd61 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h
@@ -78,5 +78,3 @@ MemFInitTableDrive (
   IN       UINT8     time
   );
 #endif  /* _MFTDS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h
index 1d66d0f..cc824cb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h
@@ -1006,5 +1006,3 @@ AGESA_STATUS
 memDefRetSuccess (VOID);
 
 #endif  /* _MM_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
index e25c938..8f18dba 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
@@ -1389,6 +1389,3 @@ MemNBfAfExcludeDimmClientNb (
   );
 
 #endif  /* _MN_H_ */
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h
index d64047b..b5841d9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h
@@ -221,5 +221,3 @@ MemUMFenceInstr (
   );
 
 #endif  /* _MU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c
index a5e27e5..704388c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c
@@ -100,5 +100,3 @@ AmdCpuRecovery (
   LoadMicrocodePatch (&CpuRecoveryParams->StdHeader);
   return (AGESA_SUCCESS);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.h
index b99d2b7..aabf194 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.h
@@ -74,4 +74,3 @@ AmdCpuRecovery (
   );
 
 #endif // _CPU_RECOVERY_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.h
index 2e6f40c..319d41d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.h
@@ -74,4 +74,3 @@ AmdGfxRecovery (
   );
 
 #endif // _GNB_RECOVERY_H_
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c
index 9118a37..400e157 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c
@@ -99,5 +99,3 @@ AmdGnbRecovery (
   GnbSetTom (NbPciAddress, StdHeader);
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitRecovery.c
index 6ead2a1..5142250 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/HT/htInitRecovery.c
@@ -160,4 +160,3 @@ AmdHtInitRecovery (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.h
index c0f87ed..4d721de 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.h
@@ -106,5 +106,3 @@ MemRecNInitializeMctC32 (
   );
 
 #endif  /* _MRNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
index d6521bd..bf31846 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
@@ -58,5 +58,3 @@ RDATA_GROUP (G2_PEI)
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.h
index 3b47d55..ae194e2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.h
@@ -106,5 +106,3 @@ MemRecNInitializeMctDA (
   );
 
 #endif  /* _MRNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.h
index ebb498b..d448db9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.h
@@ -106,5 +106,3 @@ MemRecNInitializeMctDR (
   );
 
 #endif  /* _MRNDR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.h
index 2326bac..304cf40 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.h
@@ -106,5 +106,3 @@ MemRecNInitializeMctHy (
   );
 
 #endif  /* _MRNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnprotohy.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
index aa2a7f8..56960bd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
@@ -58,5 +58,3 @@ RDATA_GROUP (G2_PEI)
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.h
index 3299d6ae..668b8d7 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.h
@@ -93,5 +93,3 @@ MemRecNSwitchChannelNi (
   );
 
 #endif  /* _MRNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c
index d11fad8..9ab752f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c
@@ -419,5 +419,3 @@ MemRecNOverrideRcvEnSeedON (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h
index 4d60923..f71a869 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h
@@ -116,5 +116,3 @@ MemRecNOverrideRcvEnSeedON (
   IN OUT   VOID *SeedPtr
   );
 #endif  /* _MRNON_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.h
index 21bc08d..15a921d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.h
@@ -93,5 +93,3 @@ MemRecNSwitchChannelPh (
   );
 
 #endif  /* _MRNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.h
index 0258e4b..fa1a2a0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.h
@@ -93,5 +93,3 @@ MemRecNSwitchChannelRb (
   );
 
 #endif  /* _MRNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c
index cc9741d..f34a9e9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c
@@ -187,4 +187,3 @@ MemRecNSetTrainDlyNb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c
index 3ebc581..edd4646 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c
@@ -136,4 +136,3 @@ MemNRecTrainingFlowClientNb (
 
   MemRecTTrainDQSPosSw (NBPtr->TechPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
index 684ed7d..1ca7356 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
@@ -128,5 +128,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c
index ab4bcc7..1a8349d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c
@@ -328,4 +328,3 @@ MemRecTProgramRcvrEnDly (
   );
   return MaxDly;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c
index bc20486..710358e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -111,5 +111,3 @@ MemRecTTrainDQSPosSw (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrdef.c
index ca0a8ba..b2f10b5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrdef.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrdef.c
@@ -126,4 +126,3 @@ SetMemRecError (
     MCTPtr->ErrCode = Errorval;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrt3.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrt3.h
index dcacd65..4050d48 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrt3.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrt3.h
@@ -117,5 +117,3 @@ MemRecTDramControlRegInit3 (
   );
 
 #endif  /* _MRT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm
index 56db233..381b4b2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm
@@ -184,4 +184,3 @@ MemRecUFlushPattern ENDP
 
 
     END
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.h
index 8c0aa11..ef70768 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.h
@@ -136,5 +136,3 @@ RecGetMaxDimmsPerChannel (
   );
 
 #endif  /* _MRU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mruc.c
index 6d1ee80..89320df 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mruc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mruc.c
@@ -264,4 +264,3 @@ MemRecFindPSOverrideEntry (
   }
   return NULL;
 }
-
diff --git a/src/vendorcode/amd/agesa/f14/cpcar.inc b/src/vendorcode/amd/agesa/f14/cpcar.inc
index ce33f62..b93a427 100644
--- a/src/vendorcode/amd/agesa/f14/cpcar.inc
+++ b/src/vendorcode/amd/agesa/f14/cpcar.inc
@@ -1119,6 +1119,3 @@ GET_NODE_ID_CORE_ID_F15 MACRO
     ;
 node_core_f15_exit:
 ENDM
-
-
-
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 40e0e31..9ef9ffb 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -1617,4 +1617,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h
index a1dd4fc..6bcba0f 100644
--- a/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h
@@ -113,4 +113,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h b/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h
index 6e0393c..c591e73 100644
--- a/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h
@@ -113,4 +113,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f15/Include/ScorpiusInstall.h b/src/vendorcode/amd/agesa/f15/Include/ScorpiusInstall.h
index bb152d7..5f03d93 100644
--- a/src/vendorcode/amd/agesa/f15/Include/ScorpiusInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/ScorpiusInstall.h
@@ -112,4 +112,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/amd.inc b/src/vendorcode/amd/agesa/f15/Legacy/amd.inc
index 86e3a02..39ae737 100644
--- a/src/vendorcode/amd/agesa/f15/Legacy/amd.inc
+++ b/src/vendorcode/amd/agesa/f15/Legacy/amd.inc
@@ -459,4 +459,3 @@ ENDIF
 IFNDEF   BIT63
     BIT63                       EQU    8000000000000000h
 ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
index 8c31a4d..1e3898d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
@@ -173,4 +173,3 @@ SetAsymBoost (
   ((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
   LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
index d03d676..d528d9b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
@@ -75,4 +75,3 @@ F10PmAsymBoostInit (
   );
 
 #endif  // _CPU_F10_ASYM_BOOST_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
index 0fc1631..a62ada6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
@@ -240,4 +240,3 @@ SetPstateMSR (
   }
   return (LowestPsEn);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
index 53ba399..7696457 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
@@ -75,4 +75,3 @@ F10PmDualPlaneOnlySupport (
   );
 
 #endif  // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index 515484c..40f28b8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -293,4 +293,3 @@ PmNbCofVidInitWarmCore (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index bf3f4bd..698a6da 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -182,4 +182,3 @@ PmNbPstateInitCore (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
index cbbb43f..df6933d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -103,4 +103,3 @@ GetF10BlMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
index ed0ad17..271a9bd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
@@ -103,4 +103,3 @@ GetF10BlLogicalIdAndRev (
 //  (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
 //  (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
 //};
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
index 4cf0507..b919aa2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -103,4 +103,3 @@ GetF10BlMicroCodePatchesStruct (
   *NumberOfElements = CpuF10BlNumberOfMicrocodePatches;
   *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
index 4405135..d6ec38a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -104,4 +104,3 @@ GetF10DaMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
index b828ff4..2c7649b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
@@ -104,4 +104,3 @@ GetF10DaLogicalIdAndRev (
 //  (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
 //  (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
 //};
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
index 2e77327..d5d11fc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -103,4 +103,3 @@ GetF10DaMicroCodePatchesStruct (
   *NumberOfElements = CpuF10DaNumberOfMicrocodePatches;
   *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index dd87ad3..fce411b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -492,4 +492,3 @@ F10CommonRevCGetNumberOfPhysicalCores (
   LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
   return (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo + 1);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
index 0f773a2..a66e398 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -106,5 +106,3 @@ GetF10RbMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
index 646ab56..a88922b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
@@ -117,4 +117,3 @@ CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
   (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10RbHtPhyRegisters
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
index d4c65d1..17638a7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -103,4 +103,3 @@ GetF10RbMicroCodePatchesStruct (
   *NumberOfElements = CpuF10RbNumberOfMicrocodePatches;
   *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
index 35042a2..6ed5a81 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
@@ -231,4 +231,3 @@ CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
   (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10RbPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index 2b1efc6..480f701 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -452,4 +452,3 @@ F10CommonRevDGetNumberOfPhysicalCores (
   }
   return ((UINT8) CmpCap);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
index 1b4a1b8..084db58 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -111,4 +111,3 @@ GetF10HyMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
index 79339a8..2665db6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
@@ -113,4 +113,3 @@ GetF10HyLogicalIdAndRev (
   *HyIdPtr = CpuF10HyLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_10_HY;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
index a924bbd..1f51c23 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -111,4 +111,3 @@ GetF10HyMicroCodePatchesStruct (
   *NumberOfElements = CpuF10HyNumberOfMicrocodePatches;
   *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
index 83094bd..7046ff7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
@@ -133,5 +133,3 @@ CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
   (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
index d1fa49d..06718c2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
@@ -381,4 +381,3 @@ CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = {
   (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10HyPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
index 5f85f5d..1ce5078 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
@@ -102,4 +102,3 @@ GetF10PhMicrocodeEquivalenceTable (
   *NumberOfElements = ((sizeof (CpuF10PhMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
   *PhEquivalenceTablePtr = CpuF10PhMicrocodeEquivalenceTable;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
index 1cd88ca..1385f47 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
@@ -93,4 +93,3 @@ GetF10PhLogicalIdAndRev (
   *PhIdPtr = CpuF10PhLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_10_PH;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
index 6c5ff70..8eaf9da 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
@@ -102,4 +102,3 @@ GetF10PhMicroCodePatchesStruct (
   *NumberOfElements = CpuF10PhNumberOfMicrocodePatches;
   *PhUcodePtr = &CpuF10PhMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c
index edda5bc..f976810 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -157,4 +157,3 @@ GetF10BrandIdString2 (
   *BrandString2Ptr = TableEntryPtr;
   *NumberOfElements = F10BrandIdString2TableCount;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
index 9aaf777..5cac8ee 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
@@ -332,4 +332,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = {
   (sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayAm3
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
index 50e5d03..b926ad2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
@@ -131,6 +131,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = {
   (sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayAsb2
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
index c5a6fe1..0564798 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
@@ -132,4 +132,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = {
   (sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayC32
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
index 4c87430..4a73612 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
@@ -176,4 +176,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayFr1207 = {
   (sizeof (CpuF10BrandIdString2ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayFr1207
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
index 0df104e..f06fc69 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
@@ -124,4 +124,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34 = {
   (sizeof (CpuF10BrandIdString2ArrayG34) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayG34
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
index c2f8f69..189aa01 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
@@ -125,4 +125,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3 = {
   (sizeof (CpuF10BrandIdString2ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayS1g3
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
index 6ec940e..3eda82d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
@@ -138,5 +138,3 @@ CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4 = {
   (sizeof (CpuF10BrandIdString2ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
   CpuF10BrandIdString2ArrayS1g4
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
index 6ba8ed8..40d1c55 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -128,4 +128,3 @@ GetF10CacheInfo (
   *NumberOfElements = 1;
   *CacheInfoPtr = &CpuF10CacheInfo;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c
index 641b7e7..281c751 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -516,4 +516,3 @@ F10Translate7BitVidTo6Bit (
     *MaxVidPtr = (*MaxVidPtr & 0x7E) >> 1;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
index c7fb857..67fe42b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
@@ -451,4 +451,3 @@ F10PmVoltageAlignmentAfterResetCore (
   LibAmdMsrRead (MSR_PSTATE_STS, &CurrentStatus, StdHeader);
   LibAmdMsrWrite (MSR_PSTATE_CTL, &CurrentStatus, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
index a282fa6..91cf9a7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -390,4 +390,3 @@ updateCpuFeatureList (
     thisCoreFeatureList++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
index 14ae439..d29cab9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
@@ -748,4 +748,3 @@ CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable = {
   (sizeof (F10HtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F10HtPhyRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c
index f4f9923..62ad23c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c
@@ -286,4 +286,3 @@ CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable = {
   (sizeof (F10MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *)F10MsrRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index b855b0b..28b2c13 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -408,4 +408,3 @@ F10PmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
index 024e760..c5ea416 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
@@ -544,4 +544,3 @@ typedef struct {
 /* Boost Offset Register F3x10C */
 #define F3x10C_REG 0x10C
 #define F3x10C_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, F3x10C_REG))
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c
index c8b54e2..4a94193 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -891,4 +891,3 @@ F10GetFrequencyXlatRegInfo (
 
   return AGESA_ERROR;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c
index ed2ff50..fa69917 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -1172,5 +1172,3 @@ F10GetNumberOfBoostedPstatesOnCore (
 
   return NumBoostStates;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c
index afcea1d..9e58b41 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c
@@ -831,4 +831,3 @@ F15OrEarlySamplesLoadMicrocode (
  *                           L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c
index 78057a7..8eb4764 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c
@@ -132,4 +132,3 @@ GetF15OrMicrocodeEquivalenceTable (
     *OrEquivalenceTablePtr = CpuF15OrMicrocodeEquivalenceTable;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c
index 158cd80..4f9f32a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c
@@ -117,4 +117,3 @@ GetF15OrLogicalIdAndRev (
   *OrIdPtr = CpuF15OrLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_15_OR;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c
index 4173492..e4fb855 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c
@@ -109,4 +109,3 @@ GetF15OrMicroCodePatchesStruct (
   *NumberOfElements = CpuF15OrNumberOfMicrocodePatches;
   *OrUcodePtr = &CpuF15OrMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c
index b1c09f2..64acdff 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c
@@ -229,6 +229,3 @@ F15OrDisUcodeWorkaroundForErratum671 (
     LibAmdMsrWrite (0xC0011000, &MsrData, StdHeader);
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c
index ce07817..616e0f8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c
@@ -959,4 +959,3 @@ CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable = {
   (sizeof (F15OrPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   F15OrPciRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c
index 311e210..51224e6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c
@@ -373,4 +373,3 @@ F15OrFpCfgInit (
     LibAmdMsrWrite (MSR_FP_CFG, &FpCfg, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c
index ed2e460..a0fc667 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c
@@ -936,4 +936,3 @@ F15OrSyncInternalNode1SbiAddr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c
index b1aa42f..0acb09c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c
@@ -419,4 +419,3 @@ updateCpuFeatureList (
     thisCoreFeatureList++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c
index 4a2251a..e5acb12 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c
@@ -917,4 +917,3 @@ F15OrGetFrequencyXlatRegInfo (
 
   return AGESA_ERROR;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
index fcd149b..6db26f3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
@@ -178,4 +178,3 @@ F15CpuAmdCoreIdPositionInInitialApicId (
   InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
   return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
index 528d4ba..1f3c595 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
@@ -220,4 +220,3 @@ IsException (
 
   return FALSE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
index 4a83c76..6866c0f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
@@ -195,4 +195,3 @@ GetF15CacheInfo (
   }
   *NumberOfElements = 1;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c
index e914029..57bb024 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c
@@ -133,4 +133,3 @@ CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable = {
   (sizeof (F15MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *)F15MsrRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
index 6242410..dcc4aad 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
@@ -438,4 +438,3 @@ F15PmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/cpuFamRegisters.h
index 4800a23..da0f4de 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/cpuFamRegisters.h
@@ -256,4 +256,3 @@
 // TBD
 
 #endif      // _CPU_FAM_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
index ca60b2b..6761607 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
@@ -748,5 +748,3 @@ IsPowerOfTwo (
   }
   return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h
index 1d2318c..2203379 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h
@@ -136,4 +136,3 @@ AllocateExecutionCache (
   );
 
 #endif  // _CPU_CACHE_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c
index ddfeb68..4d015c6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -360,4 +360,3 @@ CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
  *                          L O C A L      F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c
index 2385752..e77b6ca 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c
@@ -859,4 +859,3 @@ IntToString (
   }
   *(String + SizeInByte * 2) = 0x0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c
index b4d0e0f..49d8983 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c
@@ -614,4 +614,3 @@ STATIC
   }
   return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
 } // MakeMemEntry()
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c
index 4e37541..33d4ad0 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c
@@ -281,4 +281,3 @@ CreateHestBank (
     HestBankPtr++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
index 16c3baa..ee68992 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h
@@ -1293,4 +1293,3 @@ GetPerformanceFeatures (
   );
 
 #endif  // _CPU_TABLE_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.h
index 464dcfb..1395524 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.h
@@ -301,4 +301,3 @@ GetIdtr (
   );
 
 #endif  /* _CPU_APIC_UTILITIES_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.h
index c83fb07..f04e134 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.h
@@ -302,4 +302,3 @@ McaInitialization (
   );
 
 #endif  // _CPU_EARLY_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h
index 4cb929b..f64e7dd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h
@@ -1005,4 +1005,3 @@ GetEmptyArray (
   );
 
 #endif  // _CPU_FAMILY_TRANSLATION_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.h
index ba63768..a0a457e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.h
@@ -236,4 +236,3 @@ SyncAllApMtrrToBsc (
   IN       AMD_CONFIG_PARAMS *StdHeader
   );
 #endif  // _CPU_POST_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h
index b400236..69ab4e1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h
@@ -90,4 +90,3 @@ typedef struct {
 
 
 #endif  // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h
index e0959fc..1e2d218 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h
@@ -406,4 +406,3 @@ typedef enum {
 } CPUID_REG;
 
 #endif      // _CPU_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c
index 28d11ff..f9755af 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c
@@ -232,4 +232,3 @@ SetWarmResetAtEarly (
  *                            L O C A L    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
index f42c35d..bef0eda 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
@@ -881,5 +881,3 @@ HeapGetCurrentBase (
   ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE));
   return ReturnPtr;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c
index 4fdbda1..2237ee4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c
@@ -178,5 +178,3 @@ AmdInitEnv (
   IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
   return  AmdInitEnvStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c
index a62af89..857a14e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c
@@ -293,4 +293,3 @@ AmdInitLate (
   IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader);
   return  AmdInitLateStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c
index 0362054..572826e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c
@@ -166,5 +166,3 @@ AmdInitMid (
   IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader);
   return AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c
index 415b33d..1891ec3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c
@@ -338,4 +338,3 @@ AmdInitPost (
 
   return  AmdInitPostStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c
index 7013f67..7650ecb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c
@@ -250,4 +250,3 @@ AmdInitResetConstructor (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c
index 2d1afe8..661a88b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c
@@ -157,4 +157,3 @@ AmdLateRunApTaskInitializer (
   AmdApExeParams->RelatedBlockLength = 0;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c
index 5e52f3c..3643d01 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c
@@ -136,4 +136,3 @@ CommonPlatformConfigInit (
   }
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.h
index 2d54a7d..bdf1986 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.h
@@ -63,4 +63,3 @@ CommonPlatformConfigInit (
   );
 
 #endif // _COMMON_INITS_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c
index 8c79f9e..85d19df 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c
@@ -210,4 +210,3 @@ FchTaskDummy (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.h
index ce1fb4c..58d803e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.h
@@ -193,4 +193,3 @@ AmdLateRunApTaskInitializer (
   IN OUT   AP_EXE_PARAMS     *AmdApExeParams
   );
 #endif // _CREATE_STRUCT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
index 5f00ec5..05fea3a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c
@@ -439,4 +439,3 @@ S3RestoreStateFromTable (
   IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c
index 60949c4..f455812 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c
@@ -482,4 +482,3 @@ CONST NORTHBRIDGE ROMDATA HtFam10RevENbNonCoherentOnly =
   MakeKey,
   NULL
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c
index ed921a2..4e2586b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c
@@ -399,4 +399,3 @@ Fam10RevDBufferOptimizations (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.h
index 1448bea..55b7e4e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.h
@@ -60,4 +60,3 @@ Fam15NorthBridgeFreqMask (
   IN       PLATFORM_CONFIGURATION *PlatformConfig,
   IN       NORTHBRIDGE            *Nb
   );
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c
index 251fc9b..452eabd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c
@@ -370,4 +370,3 @@ Fam15BufferOptimizations (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.h
index 25cbfdf..c26eaa6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.h
@@ -76,5 +76,3 @@ CoherentDiscovery (
   );
 
 #endif  /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.h
index 988a4cf..34f91ee 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.h
@@ -77,5 +77,3 @@ RegangLinks (
   );
 
 #endif  /* _HT_FEAT_GANGING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.h
index f672cc4..0e0e67e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.h
@@ -86,5 +86,3 @@ MakeHopCountTable (
   );
 
 #endif  /* _HT_FEAT_ROUTING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.h
index d8c1d9d..35866d8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.h
@@ -76,5 +76,3 @@ SubLinkRatioFixup (
   );
 
 #endif  /* _HT_FEAT_SUBLINKS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c
index 5e9fe0e..4cabce7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c
@@ -417,4 +417,3 @@ TrafficDistribution (
       );
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.h
index 8fda546..bd99288 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.h
@@ -75,5 +75,3 @@ TrafficDistribution (
   );
 
 #endif  /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c
index 05028db..ab57cee 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c
@@ -147,4 +147,3 @@ HtIdsGetPortOverride (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h
index 74c2a9c..661575e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h
@@ -175,4 +175,3 @@ HandleSpecialNodeCase (
   IN       STATE_DATA  *State,
   IN       NORTHBRIDGE *Nb
   );
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h
index 1dd4748..d2e39d3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h
@@ -141,4 +141,3 @@ GraphGetBc (
   );
 
 #endif  /* _HT_GRAPH_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c
index 1b9b094..3bde506 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c
@@ -196,4 +196,3 @@ GraphGetBc (
   ASSERT ((NodeA < size) && (NodeB < size));
   return Graph[1 + (NodeA*size + NodeB)*2];
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c
index 35f6ddf..345c6c5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c
@@ -93,4 +93,3 @@ CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
   0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x90, 0xFF,  0x00, 0x77, // Node6
   0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x66,  0x60, 0xFF  // Node7
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c
index c075e15..b0c67cc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c
@@ -391,4 +391,3 @@ GetOverrideBusNumbers (
   // SecBus, SubBus are not valid if Result is FALSE.
   return result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c
index 74d0c14..430b513 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c
@@ -245,4 +245,3 @@ NewNorthBridge (
   // Set the config handle for passing to the library.
   Nb->ConfigHandle = State->ConfigHandle;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h
index d72eb2e..76dba4f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h
@@ -122,4 +122,3 @@ typedef enum {
 #define IDS_CPB_BOOST_DIS_IGNORE  0xFFFFFFFF
 
 #endif //_IDS_LIB_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h
index 55d3161..bf2e1f7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h
@@ -77,5 +77,3 @@ MemFInterleaveChannels (
   );
 
 #endif  /* _MFCHI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h
index c4c5dff..f37d417 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -77,5 +77,3 @@ MemFInterleaveBanks (
   );
 
 #endif  /* _MFCSI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c
index 3138f3f..39b3a3b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c
@@ -620,4 +620,3 @@ MemFDMISupport2 (
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h
index 8895d51..6a73b0f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h
@@ -77,5 +77,3 @@ MemFInitECC (
   );
 
 #endif  /* _MFECC_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 023a0c1..de9d716 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -204,4 +204,3 @@ MemFRASExcludeDIMM (
   NBPtr->SwitchDCT (NBPtr, ReserveDCT);
   return RetVal;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index 6ce81de..28c87b3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -160,5 +160,3 @@ MemFInterleaveRegion (
     }
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
index 6c57d8b..f38ae5f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
@@ -77,5 +77,3 @@ MemFInterleaveRegion (
   );
 
 #endif  /* _MFINTLVRN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index 0d62654..5de93d6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -149,4 +149,3 @@ MemFMctMemClr_Sync (
   }
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h
index ec7cc4e..a9bbe65 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h
@@ -75,5 +75,3 @@ MemFInterleaveNodes (
   );
 
 #endif  /* _MFNDI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h
index bc8daa7..dcce98b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h
@@ -76,5 +76,3 @@ MemFOnlineSpare (
   );
 
 #endif  /* _MFSPR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c
index f224828..cc8b7d9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c
@@ -390,9 +390,3 @@ SetTableValues (
     }
   }
 }
-
-
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c
index 924a5ae..f975bd7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c
@@ -185,4 +185,3 @@ MemErrHandle (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c
index b126dda..43559c2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c
@@ -238,4 +238,3 @@ MemMStandardTrainingUsingAdjacentDies (
   }
   return (BOOLEAN) (Die == mmPtr->DieCount);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c
index 16f59ae..749ce76 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c
@@ -243,4 +243,3 @@ MemMUmaAlloc (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm
index 61656df..6f1cdfa 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm
@@ -494,4 +494,3 @@ MemUMFenceInstr PROC CALLCONV PUBLIC
 MemUMFenceInstr ENDP
 
     END
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c
index 4df1a63..6c14798 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c
@@ -490,4 +490,3 @@ memNEnableTrainSequenceC32 (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h
index cd687f0..a440ccb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h
@@ -208,5 +208,3 @@ MemNForceLvDimmVoltageC32 (
   );
 
 #endif  /* _MNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c
index f479ce0..707170f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c
@@ -132,4 +132,3 @@ MemNPlatformSpecificFormFactorInitC32 (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c
index 296f1cd..3734f13 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c
@@ -495,4 +495,3 @@ memNEnableTrainSequenceDA (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.h
index ded80be..0db9a77 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.h
@@ -205,5 +205,3 @@ MemNPlatformSpecificFormFactorInitNi (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c
index 3163533..725b217 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c
@@ -136,4 +136,3 @@ MemNPlatformSpecificFormFactorInitDA (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c
index a107cd8..3fba586 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c
@@ -195,6 +195,3 @@ MemNPowerDownCtlDA (
     }
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c
index 19e47f9..8c6c55b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c
@@ -83,4 +83,3 @@ MemPNodeMemBoundaryDA (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c
index 7e8e210..7142ea6 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c
@@ -511,4 +511,3 @@ MemNProgramCycTimingsDr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c
index 6970f5b..71e2fe4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c
@@ -136,6 +136,3 @@ MemNPlatformSpecificFormFactorInitDr (
  *
  *----------------------------------------------------------------------------
  */
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c
index 5227e06..8a08074 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c
@@ -194,6 +194,3 @@ MemNPowerDownCtlDR (
     }
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c
index 68c31ee..2bde66c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c
@@ -166,4 +166,3 @@ MemPNodeMemBoundaryDr (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c
index 588f27a..1f618fb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c
@@ -131,4 +131,3 @@ MemNPlatformSpecificFormFactorInitHy (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c
index 16f6b13..b450c83 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c
@@ -493,4 +493,3 @@ memNEnableTrainSequenceHy (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h
index a2379fc..1f694fe 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h
@@ -208,5 +208,3 @@ MemNBeforeDQSTrainingHy (
   );
 
 #endif  /* _MNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c
index 563c5e8..8bdbe4c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c
@@ -131,4 +131,3 @@ MemNTechBlockSwitchOr (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c
index 26ec28d..37bbfa9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c
@@ -215,4 +215,3 @@ MemNFixupSysAddrOr (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h
index 7ac0dc9..18ec0b4 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h
@@ -357,5 +357,3 @@ MemNAdjustWrDqsBeforeSeedScalingOr (
   );
 
 #endif  /* _MNOR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
index d154e2f..1758c73 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c
@@ -846,4 +846,3 @@ MemNAdjustWrDqsBeforeSeedScalingOr (
   * (INT16 *) WrDqsBias = (INT16) (0x20 * MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly));
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c
index 65addd5..6c8b3fc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c
@@ -96,4 +96,3 @@ MemNInitEarlySampleSupportOr (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c
index 17ff526..3b0cc86 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c
@@ -500,4 +500,3 @@ memNEnableTrainSequencePh (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.h
index 225dae4..35d64cd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.h
@@ -125,5 +125,3 @@ MemNFinalizeMctPh (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c
index d95e210..f47aca9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c
@@ -138,4 +138,3 @@ MemNPlatformSpecificFormFactorInitPh (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c
index cec68c1..0b8bb67 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c
@@ -500,4 +500,3 @@ memNEnableTrainSequenceRb (
   }
   return Retval;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.h
index ad7a32c..2e98431 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.h
@@ -120,5 +120,3 @@ memNEnableTrainSequenceRb (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 #endif  /* _MNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c
index 99bf9bd..2925552 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c
@@ -138,4 +138,3 @@ MemNPlatformSpecificFormFactorInitRb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c
index a3d90b8..223d3a9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c
@@ -157,4 +157,3 @@ MemPDoPsSDA2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c
index 7b2d67f..0512dba 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c
@@ -162,4 +162,3 @@ MemPDoPsRDr2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c
index 0ae2a7c..74afdae 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c
@@ -201,4 +201,3 @@ MemPDoPsRDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c
index 215072c..ccccb59 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c
@@ -188,4 +188,3 @@ MemPDoPsSDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c
index 9359e5c..2ae206f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c
@@ -162,4 +162,3 @@ MemPDoPsUDr2 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c
index 84007fe..94188de 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c
@@ -157,4 +157,3 @@ MemPDoPsUDr3 (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c
index 8f522b9..a72af55 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c
@@ -220,4 +220,3 @@ CONST PSC_TBL_ENTRY MaxFreqTblEntSOAM3 = {
    sizeof (MaxFreqOrAM3SODIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
    (VOID *)&MaxFreqOrAM3SODIMM
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c
index f4464e9..221eeb2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c
@@ -225,4 +225,3 @@ CONST PSC_TBL_ENTRY OrDdr3CSTriEnt = {
    sizeof (OrDdr3CSTri) / sizeof (UINT8),
    (VOID *)&OrDdr3CSTri
 };
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c
index 9225069..fa6f852 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c
@@ -1222,4 +1222,3 @@ MemPCheckTblDrvOverrideConfigSpeedLimit (
 
   return FALSE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c
index f2a5bc4..c011f75 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c
@@ -229,5 +229,3 @@ MemConstructTechBlock2 (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h
index 54cac5d..c640699 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h
@@ -121,5 +121,3 @@ MemTGetDimmSpdBuffer2 (
   );
 
 #endif  /* _MT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c
index 8d4503b..3c9838d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c
@@ -158,6 +158,3 @@ MemTGetLD2 (
 
   return LD;
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h
index 2dda044..bf599f8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h
@@ -85,5 +85,3 @@ MemTGetLD2 (
   );
 
 #endif  /* _MTOT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h
index b115888..7c52311 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h
@@ -179,5 +179,3 @@
 
 
 #endif  /* _MTSPD2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h
index 710ccc9..36ccfe9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h
@@ -131,5 +131,3 @@ MemTGetDimmSpdBuffer3 (
   IN       UINT8 Dimm
   );
 #endif  /* _MT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h
index dcc3ad7..c01154f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h
@@ -87,5 +87,3 @@ MemTGetLD3 (
   );
 
 #endif  /* _MTOT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c
index 79fef4d..80ea81c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -316,4 +316,3 @@ FreqChgCtrlWrd3 (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h
index 6a5d75b..f09856d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h
@@ -84,5 +84,3 @@ MemTDramControlRegInit3 (
   );
 
 #endif  /* _MTRCI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h
index 80dd1cd..e87bb21 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h
@@ -93,5 +93,3 @@ MemTEMRS23 (
   );
 
 #endif  /* _MTSDI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c
index d61c065..b657fa3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -1188,4 +1188,3 @@ MemTGetDimmSpdBuffer3 (
   }
   return DimmPresent;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h
index e7a64df..f511101 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -173,5 +173,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
index d78a3fc..dda73dd 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c
@@ -913,4 +913,3 @@ MemTDataEyeSave (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h
index a8e36be..7d56a61 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h
@@ -114,5 +114,3 @@ typedef struct _SWEEP_INFO {
 
 
 #endif  /* _MTTEDGEDETECT_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c
index 696c46e..8f03a85 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c
@@ -343,4 +343,3 @@ MemTDqsTrainRcvrEnSw (
   IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n");
   return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfParallelTraining.h
index 73a530d..444c466 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfParallelTraining.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfParallelTraining.h
@@ -110,5 +110,3 @@ MemFParallelTraining (
  );
 
 #endif  /* _MFPARALLELTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfStandardTraining.h
index 0ba042f..8b3ac9a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfStandardTraining.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfStandardTraining.h
@@ -78,5 +78,3 @@ MemFStandardTraining (
   );
 
 #endif  /* _MFSTANDARDTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h
index 85ec85b..b13ef0f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h
@@ -80,5 +80,3 @@ MemFMctMemClr_Sync (
   );
 
 #endif  /* _MFMEMCLR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h
index 1a8ba10..76295e0 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h
@@ -77,5 +77,3 @@ MemFInitTableDrive (
   IN       UINT8     time
   );
 #endif  /* _MFTDS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h
index 084c0fd..65e74bf 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h
@@ -1303,5 +1303,3 @@ AmdMemFunctionListDef (
   IN OUT   VOID *pMemData
   );
 #endif  /* _MM_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h
index 7b9a86e..54a607a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h
@@ -1740,4 +1740,3 @@ MemNInitializeRdDqs__VictimContinuousWritesUnb (
   );
 
 #endif  /* _MN_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mu.h
index c68f321..1fff15c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mu.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/mu.h
@@ -228,5 +228,3 @@ MemUnsToMemClk (
   IN       UINT32 NumberOfns
   );
 #endif  /* _MU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c
index 4593c60..399d7ed 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c
@@ -99,5 +99,3 @@ AmdCpuRecovery (
   LoadMicrocodePatch (&CpuRecoveryParams->StdHeader);
   return (AGESA_SUCCESS);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.h
index a0fe607..45b1197 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.h
@@ -73,4 +73,3 @@ AmdCpuRecovery (
   );
 
 #endif // _CPU_RECOVERY_H_
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c
index 2fdce7b..104aaba 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c
@@ -165,4 +165,3 @@ AmdHtInitRecovery (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.h
index 2a2f277..3143197 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.h
@@ -105,5 +105,3 @@ MemRecNInitializeMctC32 (
   );
 
 #endif  /* _MRNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
index f60b28b..a9ca2d2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
@@ -57,5 +57,3 @@ RDATA_GROUP (G2_PEI)
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.h
index 1ecac2d..2ecdca1 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.h
@@ -105,5 +105,3 @@ MemRecNInitializeMctDA (
   );
 
 #endif  /* _MRNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.h
index 6e03cb8..68ea31c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.h
@@ -105,5 +105,3 @@ MemRecNInitializeMctDR (
   );
 
 #endif  /* _MRNDR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.h
index b3fcad2..d0ae974 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.h
@@ -105,5 +105,3 @@ MemRecNInitializeMctHy (
   );
 
 #endif  /* _MRNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnprotohy.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
index 5773c1f..94a4386 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
@@ -57,5 +57,3 @@ RDATA_GROUP (G2_PEI)
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c
index 8fcfc96..1fc18c8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c
@@ -795,4 +795,3 @@ MemRecNIsIdSupportedOr (
     return FALSE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.h
index 6fbf8a6..75be984 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.h
@@ -125,5 +125,3 @@ MemRecNSetMaxLatencyOr (
   );
 
 #endif  /* _MRNOR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnprotoor.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnprotoor.c
index b06c17d..93f5582 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnprotoor.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnprotoor.c
@@ -57,5 +57,3 @@ RDATA_GROUP (G3_DXE)
  *
  *-----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.h
index 8fe4ade..b87d8d9 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.h
@@ -92,5 +92,3 @@ MemRecNSwitchChannelPh (
   );
 
 #endif  /* _MRNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.h
index 9915c76..2451a2e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.h
@@ -92,5 +92,3 @@ MemRecNSwitchChannelRb (
   );
 
 #endif  /* _MRNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c
index 44abf5e..dae2290 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c
@@ -186,4 +186,3 @@ MemRecNSetTrainDlyNb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c
index 2333be7..44ddddc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c
@@ -1574,4 +1574,3 @@ MemRecNCompareTestPatternUnb (
   Pass = ~Pass;
   return Pass;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c
index e102af4..d60ef9a 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c
@@ -155,4 +155,3 @@ MemNRecTrainingFlowUnb (
 
   MemRecTTrainRcvrEnHwSeedless (NBPtr->TechPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
index 24dccee..604aacb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
@@ -127,5 +127,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c
index 84e7ab6..852b6a5 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c
@@ -326,4 +326,3 @@ MemRecTProgramRcvrEnDly (
   );
   return MaxDly;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
index 2e0f1a4..d1d2836 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c
@@ -312,4 +312,3 @@ MemRecTProgramRcvrEnDly (
 
   return MaxDly;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c
index 7f53991..f2ddc6f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -110,5 +110,3 @@ MemRecTTrainDQSPosSw (
  *
  *----------------------------------------------------------------------------
  */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrdef.c
index 7d270ec..c2e27dc 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrdef.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrdef.c
@@ -125,4 +125,3 @@ SetMemRecError (
     MCTPtr->ErrCode = Errorval;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrt3.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrt3.h
index d5fe3ea..974474c 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrt3.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mrt3.h
@@ -116,5 +116,3 @@ MemRecTDramControlRegInit3 (
   );
 
 #endif  /* _MRT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm
index 5520d8e..f10e244 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm
@@ -184,4 +184,3 @@ MemRecUFlushPattern ENDP
 
 
     END
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.h b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.h
index a2cd553..07a4d5e 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.h
@@ -136,5 +136,3 @@ RecGetMaxDimmsPerChannel (
   );
 
 #endif  /* _MRU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mruc.c
index e385b26..1fb9cbb 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mruc.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mruc.c
@@ -267,4 +267,3 @@ MemRecFindPSOverrideEntry (
   }
   return NULL;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15/cpcar.inc b/src/vendorcode/amd/agesa/f15/cpcar.inc
index 544cc64..14addb8 100644
--- a/src/vendorcode/amd/agesa/f15/cpcar.inc
+++ b/src/vendorcode/amd/agesa/f15/cpcar.inc
@@ -1465,6 +1465,3 @@ end_of_f15h_data:
     .endif
 node_core_f15_exit:
 ENDM
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc
index c88709c..2df00c4 100644
--- a/src/vendorcode/amd/agesa/f15/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15/gcccar.inc
@@ -1624,4 +1624,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h
index 9a285b4..3c6f43e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h
@@ -156,4 +156,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
index d762022..41d549e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
@@ -1990,4 +1990,3 @@
  *        SYNCFLOOD_L.
  *
  */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h
index f27ebba..43dfccc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h
@@ -141,4 +141,3 @@
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc
index 550475a..6a4b8ad 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc
@@ -458,4 +458,3 @@ ENDIF
 IFNDEF   BIT63
     BIT63                       EQU    8000000000000000h
 ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
index b0b12b8..8f8033d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
@@ -125,4 +125,3 @@ GetF15TnMicrocodeEquivalenceTable (
     *TnEquivalenceTablePtr = CpuF15TnMicrocodeEquivalenceTable;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
index d95edf3..91ed06f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
@@ -285,4 +285,3 @@ F15TnNbPstateForceBeforeApLaunchAtEarly (
     LibAmdMsrWrite (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c
index 8157b57..c1ec378 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c
@@ -104,4 +104,3 @@ GetF15TnLogicalIdAndRev (
   *TnIdPtr = CpuF15TnLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_15_TN;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
index c0ca136..0a23aa2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
@@ -108,4 +108,3 @@ GetF15TnMicroCodePatchesStruct (
   *NumberOfElements = CpuF15TnNumberOfMicrocodePatches;
   *TnUcodePtr = &CpuF15TnMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
index db8a563..f86781c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
@@ -294,4 +294,3 @@ SetForceSmcCheckFlwStDis (
 
   return;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
index 16487bf..3870df2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
@@ -175,6 +175,3 @@ F15TnPmPwrPlaneInit (
     LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
index 2412924..57dafab 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
@@ -385,4 +385,3 @@ Update800MHzHtcPstateTo900MHz (
     LibAmdMsrWrite ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
index 57ca08b..ee17821 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
@@ -998,7 +998,3 @@ F15TnCmnCalculateCurrentInmA (
 
   IDS_HDT_CONSOLE (CPU_TRACE, "    CurrentInmA=%d\n", *CurrentInmA);
 }
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
index 27bc273..e92efbb 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
@@ -456,4 +456,3 @@ F15TnPmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
index ab99ba1..5d23825 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
@@ -736,4 +736,3 @@ F15TnGetFrequencyXlatRegInfo (
   IDS_HDT_CONSOLE (CPU_TRACE, "  CpuFidPtr=%d, CpuDidPtr1=0x%x, CpuDidPtr2=0x%x\n", *CpuFidPtr, *CpuDidPtr1, *CpuDidPtr2);
   return AGESA_ERROR;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
index 7cd57a1..7539bff 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
@@ -177,4 +177,3 @@ F15CpuAmdCoreIdPositionInInitialApicId (
   InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
   return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c
index 0450263..17fbcdd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c
@@ -219,4 +219,3 @@ IsException (
 
   return FALSE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
index df868ff..73c7da4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
@@ -194,4 +194,3 @@ GetF15CacheInfo (
   }
   *NumberOfElements = 1;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c
index 42498fc..085bd5c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c
@@ -248,4 +248,3 @@ CONST CRAT_FAMILY_SERVICES ROMDATA F15CratSupport =
     F15GenerateCratCacheEntry,
     F15GenerateCratTLBEntry
 };
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c
index e268ef5..b845007 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c
@@ -131,4 +131,3 @@ CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable = {
   (sizeof (F15MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *)F15MsrRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
index c63d555..ca743c3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
@@ -436,4 +436,3 @@ F15PmPwrChkCopyPstate (
   LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
   LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h
index 861878b..827b804 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h
@@ -245,4 +245,3 @@
 
 
 #endif      // _CPU_FAM_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
index fcd7bf4..4c9a816 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
@@ -747,5 +747,3 @@ IsPowerOfTwo (
   }
   return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h
index f10a6af..92fd0eb 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h
@@ -135,4 +135,3 @@ AllocateExecutionCache (
   );
 
 #endif  // _CPU_CACHE_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c
index 67ae390..ede32e7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c
@@ -339,4 +339,3 @@ AcpiCditHBufferFind (
 
   return;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c
index bee26ad..07ca116 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -359,4 +359,3 @@ CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
  *                          L O C A L      F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c
index 945aee1..a145ab9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c
@@ -505,4 +505,3 @@ AddOneCratEntry (
   }
   return CurrentEntry;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c
index 2d62f83..e252573 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c
@@ -837,4 +837,3 @@ IntToString (
   }
   *(String + SizeInByte * 2) = 0x0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c
index dcd3d71..ef35109 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c
@@ -613,4 +613,3 @@ STATIC
   }
   return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
 } // MakeMemEntry()
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c
index 1275d8d..4ace789 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c
@@ -280,4 +280,3 @@ CreateHestBank (
     HestBankPtr++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
index c21cb9c..f7df494 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h
@@ -1291,4 +1291,3 @@ GetPerformanceFeatures (
   );
 
 #endif  // _CPU_TABLE_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c
index e1a39bc..8c79190 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c
@@ -924,4 +924,3 @@ SetRegisterForHtLinkPciEntry (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h
index f198c5b..8dd80a4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h
@@ -300,4 +300,3 @@ GetIdtr (
   );
 
 #endif  /* _CPU_APIC_UTILITIES_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h
index c441063..43fc456 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h
@@ -301,4 +301,3 @@ McaInitialization (
   );
 
 #endif  // _CPU_EARLY_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h
index f7d3b86..7c7683e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h
@@ -1004,4 +1004,3 @@ GetEmptyArray (
   );
 
 #endif  // _CPU_FAMILY_TRANSLATION_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h
index db80c56..944999b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h
@@ -235,4 +235,3 @@ SyncAllApMtrrToBsc (
   IN       AMD_CONFIG_PARAMS *StdHeader
   );
 #endif  // _CPU_POST_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h
index 0f151eb..4b17c05 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h
@@ -90,4 +90,3 @@ typedef struct {
 
 
 #endif  // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h
index f3e7116..c61d0a8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h
@@ -415,4 +415,3 @@ typedef enum {
 } CPUID_REG;
 
 #endif      // _CPU_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c
index 60a9d69..5fa069e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c
@@ -231,4 +231,3 @@ SetWarmResetAtEarly (
  *                            L O C A L    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
index 2e45471..7665439 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
@@ -880,5 +880,3 @@ HeapGetCurrentBase (
   ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE));
   return ReturnPtr;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c
index 7e538f0..0b3eb9c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c
@@ -113,4 +113,3 @@ AmdAddMmioMapping (
     return AGESA_UNSUPPORTED;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h
index 9b9ab3b..df6cd36 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h
@@ -139,4 +139,3 @@ AmdAddMmioMapping (
   );
 
 #endif // _MMIO_MAP_MANAGER_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c
index 8097e43..506ba7d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c
@@ -182,5 +182,3 @@ AmdInitEnv (
   IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
   return  AmdInitEnvStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c
index d907a33..2fc57b2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c
@@ -301,4 +301,3 @@ AmdInitLate (
 
   return  AmdInitLateStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c
index 5807dc5..f9dc1e1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c
@@ -170,5 +170,3 @@ AmdInitMid (
 
   return AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c
index f1cee5e..d9a1e57 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c
@@ -343,4 +343,3 @@ AmdInitPost (
 
   return  AmdInitPostStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
index 5cb2adc..a83a846 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
@@ -253,4 +253,3 @@ AmdInitResetConstructor (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c
index b11fca2..3467b8f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c
@@ -156,4 +156,3 @@ AmdLateRunApTaskInitializer (
   AmdApExeParams->RelatedBlockLength = 0;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c
index 799018b..7931908 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c
@@ -137,4 +137,3 @@ CommonPlatformConfigInit (
   }
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h
index 681bc4a..ac0908c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h
@@ -62,4 +62,3 @@ CommonPlatformConfigInit (
   );
 
 #endif // _COMMON_INITS_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c
index 4563d6b..4ab63de 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c
@@ -209,4 +209,3 @@ FchTaskDummy (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h
index 66a7bbf..6215631 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h
@@ -192,4 +192,3 @@ AmdLateRunApTaskInitializer (
   IN OUT   AP_EXE_PARAMS     *AmdApExeParams
   );
 #endif // _CREATE_STRUCT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
index b8716f2..327551b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
@@ -438,4 +438,3 @@ S3RestoreStateFromTable (
   IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c
index 02114e9..8bdbd4d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c
@@ -56,4 +56,3 @@ FchInitLateAzalia  (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c
index 1b7ff7c..339687f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c
@@ -507,5 +507,3 @@ ConfigureAzaliaSetConfigD4Dword (
     ++TempAzaliaCodecEntryPtr;
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c
index 78fa228..f2ac104 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c
@@ -58,4 +58,3 @@ FchInitResetAzalia  (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c
index 1aaa56c..646e951 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c
@@ -240,4 +240,3 @@ ReadFchSleepType (
   LibAmdIoRead (AccessWidth16, Value16, &Value16, StdHeader);
   return (UINT8) ((Value16 >> 10) & 7);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h
index 8e1ef01..2b10792 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h
@@ -64,4 +64,3 @@
 #define BOOT_TIME_FLAG_INT19                  0xFC
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c
index 6711b8d..31121f7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c
@@ -44,4 +44,3 @@
 #include "FchPlatform.h"
 #include "heapManager.h"
 #define FILECODE PROC_FCH_COMMON_FCHCOMMON_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c
index bd2e286..2dffc13 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c
@@ -68,4 +68,3 @@ FchSmmAcpiOn (
   //
   RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGAC, AccessWidth8, ~(BIT6), 0);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h
index 00283de..54fd968 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h
@@ -454,4 +454,3 @@ BOOLEAN  IsLpcRom (OUT VOID);
 VOID  SbSleepTrapControl (IN BOOLEAN SleepTrap);
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c
index 99ed53d..4949d73 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c
@@ -141,4 +141,3 @@ RwMem (
   Result = (Result & Mask) | Data;
   WriteMem (Address, OpFlag, &Result);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c
index 6d286e8..9d9a6f5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c
@@ -90,5 +90,3 @@ RwPci (
   rMask = ~Mask;
   LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h
index 10e7377..f769bdc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h
@@ -1550,5 +1550,3 @@ FCH_MISC_REGF0                   EQU     0F0h
 #ifndef FCH_DEADLOOP
   #define FCH_DEADLOOP()    { volatile UINTN __i; __i = 1; while (__i); }
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
index feb661d..15ed180 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
@@ -100,4 +100,3 @@ FchInitGecController (
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, (UINT32)~BIT0, BIT0);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c
index f67c74e..747aec5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c
@@ -60,6 +60,3 @@ FchInitEnvGec (
 {
   FchInitGecController (FchDataPtr);
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c
index 74beafd..40702bf 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c
@@ -57,5 +57,3 @@ FchInitLateGec (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c
index 8af1496..3a85a98 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c
@@ -64,4 +64,3 @@ FchInitResetGec (
   RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG9C, AccessWidth32, 0, \
     UserOptions.FchBldCfg->CfgGecShadowRomBase + 1, ((FCH_RESET_DATA_BLOCK *) FchDataPtr)->StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
index 5ccfaa2..fe20bcc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
@@ -283,6 +283,3 @@ StressResetModeLate (
   while (LocalCfgPtr->HwAcpi.StressResetMode) {
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
index 33adf86..b1df6cf 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
@@ -138,4 +138,3 @@ ProgramFchHwAcpiResetP (
     LocalCfgPtr->SataClkMode = 0x0a;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c
index fbf9845..feaa77b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c
@@ -105,4 +105,3 @@ FchInitEnvHwAcpi (
   ProgramSpecificFchInitEnvAcpiMmio (FchDataPtr);
   HpetInit (LocalCfgPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
index ebb53be..56b9609 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
@@ -175,4 +175,3 @@ IsGCPU (
     return FALSE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c
index 298a70d..f54c727 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c
@@ -198,5 +198,3 @@ FchInitResetHwAcpi (
     ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->OemResetProgrammingTablePtr), StdHeader);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
index 8bd890b..9800c56 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
@@ -186,4 +186,3 @@ FchECfancontrolservice (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
index 3c1beeb..c9326c4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
@@ -245,4 +245,3 @@ HwmCaculate (
     LocalCfgPtr->Hwm.HwmCurrent.Voltage[Index] = (ValueWord >> 6) * 512 / LocalCfgPtr->Hwm.HwmCalibrationFactor;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c
index e3e6c53..81b09de 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c
@@ -59,4 +59,3 @@ FchInitEnvHwm (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c
index 02f5421..7ce02d6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c
@@ -67,5 +67,3 @@ FchInitLateHwm (
     FchECfancontrolservice (LocalCfgPtr);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c
index 7e64120..e99fe05 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c
@@ -59,4 +59,3 @@ FchInitResetHwm (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c
index bf2bed9..d3bbac2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c
@@ -115,6 +115,3 @@ FchInitEnvIde (
   //
   RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, (UINT32)~BIT0, 0, StdHeader);
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c
index 970b821..d81f857 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c
@@ -55,5 +55,3 @@ FchInitLateIde (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c
index 45876dd..0fc9b00 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c
@@ -58,4 +58,3 @@ FchInitMidIde (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
index b08821c..00b112f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
@@ -123,4 +123,3 @@ SoftwareToggleImcStrapping (
   LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
   FchStall (0xffffffff, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c
index df88f9f..9d0e31c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c
@@ -57,5 +57,3 @@ FchInitLateEc (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c
index cc4b146..9954cc7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c
@@ -111,6 +111,3 @@ FchInitResetEc (
   RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB3, AccessWidth8, (UINT32)~BIT6, BIT6);
   ExitEcConfig (StdHeader);
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c
index 45ec7d9..2f6f0fc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c
@@ -149,4 +149,3 @@ ValidateImcFirmware (
     return  TRUE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c
index 1421b5f..e41048e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c
@@ -78,4 +78,3 @@ ImcDisarmSurebootTimer (
   ImcDisableSurebootTimer (LocalCfgPtr);
   LocalCfgPtr->Imc.ImcSureBootTimer = 0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c
index 5631bcd..bff1175 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c
@@ -75,4 +75,3 @@ FchInitResetImc (
     ImcSleep (FchDataPtr);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
index 5a9899a..51dcdc5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
@@ -346,5 +346,3 @@ FCH_DATA_BLOCK   InitEnvCfgDefault = {
     }
   }
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
index ba267c3..6f9f0ea 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
@@ -154,5 +154,3 @@ FCH_RESET_DATA_BLOCK   InitResetCfgDefault = {
   },
   NULL                   // OemResetProgrammingTablePtr
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
index 98004f1..f79016d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c
@@ -111,5 +111,3 @@ FchEnvConstructor (
   EnvParams->FchInterface = FchInterfaceDefault;
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c
index 1978815..5c49bdd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c
@@ -113,4 +113,3 @@ FchResetConstructor (
   ResetParams->FchInterface = FchResetInterfaceDefault;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c
index 75fdf8a..0a51584 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c
@@ -99,4 +99,3 @@ FchInitS3LateRestore (
   AgesaStatus = FchTaskLauncher (&FchInitS3LateTaskTable[0], FchDataPtr, TpFchInitS3LateDispatching);
   FchDataPtr->Misc.S3Resume = 0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c
index e0a833d..2bd559c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c
@@ -61,4 +61,3 @@ FchTaskLauncher (
   }
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c
index ba45bd7..c6216e1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c
@@ -192,5 +192,3 @@ FchInitEnvCreatePrivateData (
   FchParams->Sd.SdClockControl           = UserOptions.FchBldCfg->CfgFchSdClockControl;
   return FchParams;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c
index 3d8f093..dbeeffa 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c
@@ -87,4 +87,3 @@ FchInitResetLoadPrivateDefault (
 
   return FchParams;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c
index 60f8bd5..53a92ff 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c
@@ -56,5 +56,3 @@ FchInitLateIr (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
index 28ab426..775813f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
@@ -104,4 +104,3 @@ FchInitEnvPcib (
     RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x40 , AccessWidth8, (UINT32)~BIT3, BIT3, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
index 173a278..5ea38bc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
@@ -133,4 +133,3 @@ FchInitResetPcibPort80Enable (
     StdHeader
     );
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c
index fa494f5..b93767f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c
@@ -76,4 +76,3 @@ FchInitEnvAbSpecial (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c
index 2f25bd4..c45a5b8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c
@@ -64,4 +64,3 @@ FchInitLateAb (
 
   FchAbLateProgram (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c
index 707d6da..a63791d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c
@@ -59,4 +59,3 @@ FchInitMidAb (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c
index 551bc07..6339dfa 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c
@@ -61,4 +61,3 @@ FchInitResetAb (
 {
   FchProgramAbPowerOnReset (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
index d83afcd..2809a6c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
@@ -115,4 +115,3 @@ FchProgramAbPowerOnReset (
   RwAlink (FCH_AX_INDXP_REGA4, 0xFFFFFFFE, AbValue, StdHeader);
 
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
index ed8af5e..7bcdab4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
@@ -120,4 +120,3 @@ FchResetPcie (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
index d717369..e9f39ff 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
@@ -193,4 +193,3 @@ FchGppDynamicPowerSaving (
     RwAlink (FCH_RCINDXC_REG65, 0xFFFFFFFF, ((GppData32 & 0x0F) == 0x0F) ? GppData32 | 0x0CFF0000 : GppData32, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c
index 4c77358..d9cfbcb 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c
@@ -286,4 +286,3 @@ FchInitLateGpp (
       RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c
index 1c36dc6..391b981 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c
@@ -95,5 +95,3 @@ FchInitResetGpp (
     }
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c
index 4e942de..188aa40 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c
@@ -64,4 +64,3 @@ FchInitEnvPcie (
   //
   ProgramPcieNativeMode (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c
index 490a07a..4d89960 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c
@@ -57,5 +57,3 @@ FchInitLatePcie (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c
index 257c295..7017fb6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c
@@ -59,5 +59,3 @@ FchInitResetPcie (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c
index a5d6f86..63e49ce 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c
@@ -64,4 +64,3 @@ FchInitMidSataAhci (
   LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
   SataAhciSetDeviceNumMsi (LocalCfgPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
index 26ff51d..bfc2827 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
@@ -277,4 +277,3 @@ FchInitEnvSataRaidProgram (
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0, SataSSIDValue, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
index 10dbc1c..95cfaea 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
@@ -135,5 +135,3 @@ FchInitResetSataProgram (
     RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, 0xFFFFFFFF, 0x04, StdHeader);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
index 673cc15..07bf07d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
@@ -670,4 +670,3 @@ FchSataSetPortGenMode (
     RwPci (((SATA_BUS_DEV_FUN << 16) + 0x80), AccessWidth16, (UINT32)~BIT8, 0, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c
index 6fcded3..6b1b267 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c
@@ -73,4 +73,3 @@ FchInitEnvSataRaid  (
 
   FchInitEnvSataRaidProgram  (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c
index 79adb51..b551a3c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c
@@ -61,5 +61,3 @@ FchInitLateSataRaid (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c
index 55e77d6..28a5f8b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c
@@ -65,5 +65,3 @@ SataRaidSetDeviceNumMsi (
 
   SataSetDeviceNumMsi (LocalCfgPtr);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c
index 619d568..33c78fe 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c
@@ -71,4 +71,3 @@ FchInitMidSataRaid (
   SataBar5setting (LocalCfgPtr, &Bar5);
   ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c
index 9eede3e..285f2ea 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c
@@ -102,4 +102,3 @@ FchInitEnvSata (
 
   SataDisableWriteAccess (StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c
index 0ca07eb..13591f5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c
@@ -85,4 +85,3 @@ SataSetIrqIntResource (
 
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c
index a684e61..b8498f7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c
@@ -67,5 +67,3 @@ FchInitLateSataIde (
   SataBar5setting (LocalCfgPtr, &Bar5);
   ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c
index ea4428e..785e8c4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c
@@ -115,4 +115,3 @@ FchInitLateSata (
   //
   SataDisableWriteAccess (StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c
index ce38ee2..c7ee7a1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c
@@ -257,4 +257,3 @@ FchSataDriveFpga (
 }
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c
index 0ff59bd..9d4266e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c
@@ -62,4 +62,3 @@ FchInitResetSata (
 {
   FchInitResetSataProgram ( FchDataPtr );
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c
index 1f67a6e..b3a378d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c
@@ -44,4 +44,3 @@
 #include "FchPlatform.h"
 #include "Filecode.h"
 #define FILECODE PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c
index 6abf53d..4dd0e5c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c
@@ -63,4 +63,3 @@ FchInitEnvSd (
 
   FchInitEnvSdProgram (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c
index fead02f..02bae71 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c
@@ -56,5 +56,3 @@ FchInitLateSd (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c
index d8ce215..82d9fd0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c
@@ -58,4 +58,3 @@ FchInitMidSd (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
index b1ae0c8..5fc28a0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
@@ -89,4 +89,3 @@ FchInitEnvLpcProgram (
   //
   RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 2, AccessWidth8, 0xF7, BIT3);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c
index 9093138..3fd2342 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c
@@ -92,4 +92,3 @@ FchInitEnvLpc (
     RwPci ((LPC_BUS_DEV_FUN << 16) + 0x78 , AccessWidth32, (UINT32)~BIT1, (UINT32)BIT1, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c
index 37c79c1..656b370 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c
@@ -68,4 +68,3 @@ FchInitResetLpc (
   FchInitResetLpcProgram (FchDataPtr);
 
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c
index 7ea106e..3bd35d3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c
@@ -512,5 +512,3 @@ FchDummy2 (
 {
   ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c
index 608eb2d..c7b4576 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c
@@ -156,4 +156,3 @@ EhciInitAfterPciInit (
 {
   FchEhciInitAfterPciInit ( Value, FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c
index fcd5104..d2551f1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c
@@ -59,4 +59,3 @@ FchInitResetEhci (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
index ebea631..3fd93ce 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
@@ -180,4 +180,3 @@ FchEhciInitAfterPciInit (
     RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, FchDataPtr->StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
index 4d4b46e..c8f12b6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
@@ -100,4 +100,3 @@ FchSetUsbEnableReg (
 
   RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEF , AccessWidth8, 0, UsbModeReg);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
index d06c476..c0ba695 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
@@ -45,4 +45,3 @@
 //
 // Declaration of local functions
 //
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
index 11cff77..41c0dc6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
@@ -122,4 +122,3 @@ FchInitResetXhciProgram (
     RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c
index 21adbc3..7786098 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c
@@ -59,4 +59,3 @@ FchInitResetOhci (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c
index e3c101b..87ab579 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c
@@ -71,4 +71,3 @@ FchInitEnvUsb (
   FchSetUsbEnableReg (FchDataPtr);
   RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEE, AccessWidth8, (UINT32)~(BIT2), 0 );
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c
index fd8c59e..aad7cc4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c
@@ -58,4 +58,3 @@ FchInitLateUsb (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c
index 2395e96..36e870e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c
@@ -65,4 +65,3 @@ FchInitMidUsb (
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, (UINT32)~BIT0, 0);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c
index fd8c217..c3e1100 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c
@@ -59,4 +59,3 @@ FchInitResetUsb (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c
index fe9e214..1494ab9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c
@@ -60,4 +60,3 @@ FchInitLateUsbXhci (
 {
   FchInitLateUsbXhciProgram ( FchDataPtr );
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c
index ff5eca1..d64f2ec 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c
@@ -44,5 +44,3 @@
 #include "FchPlatform.h"
 #include "Filecode.h"
 #define FILECODE PROC_FCH_USB_XHCIRECOVERY_FILECODE
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c
index 4a8e56b..be99221 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c
@@ -72,4 +72,3 @@ FchInitResetXhci (
  * @param[in] FchDataPtr Fch configuration structure pointer.
  *
  */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h
index d690514..85de60e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h
@@ -88,4 +88,3 @@ typedef struct  {
 #pragma pack (pop)
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h
index 4ea7ef1..4c3e11d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h
@@ -40974,5 +40974,3 @@ typedef union {
 #define D0F0xBC_x1F480_TYPE                                     TYPE_D0F0xBC
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
index 659300a..aa775bd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
@@ -154,4 +154,3 @@ GnbLibTimeStamp (
     );
   return TimeStamp;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index 7f701f0..976477a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -518,4 +518,3 @@ GnbLibLocateService (
   }
   return AGESA_UNSUPPORTED;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
index db203fa..8a5c7d2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -126,5 +126,3 @@ GnbLibCpuPciIndirectWrite (
     GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
   } while ((OffsetRegisterValue & BIT31) == 0);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
index b8cca2b..1cb42b4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -156,4 +156,3 @@ GnbLocateHeapBuffer (
   }
   return LocHeapParams.BufferPtr;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
index 79e2656..cd5eeb3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -119,4 +119,3 @@ GnbLibIoRead (
 {
   LibAmdIoRead (Width, Address, Value, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
index 8e679bf..e5f4fc3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -119,7 +119,3 @@ GnbLibMemRead (
 {
   LibAmdMemRead (Width, Address, Value, StdHeader);
 }
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
index c9713f5..b91ed4e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
@@ -512,4 +512,3 @@ PcieFmGetSbConfigInfo (
   }
   return Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
index 49fd4cb..cfafd74 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -132,5 +132,3 @@ GfxConfigPostInterface (
   IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status);
   return  Status;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
index ce50a97..6da8b62 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
@@ -448,4 +448,3 @@ GfxLibCalculateDidTN (
   }
   return Did;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
index 7e3e659..0dcd270 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
@@ -274,4 +274,3 @@ GfxIntegratedEnumerateAudioConnectors (
   IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Exit\n");
   return Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
index e556ece..0349f75 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
@@ -321,6 +321,3 @@ GnbBapmCalculateCoeffsTN (
   }
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Exit\n");
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
index d4519b7..dd766ce 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
@@ -258,5 +258,3 @@ GnbCreateIvhdrTN (
 
 
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
index 4cac1cb..4fd6176 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
@@ -98,4 +98,3 @@ GnbPostInterfaceTN (
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Exit [0x%x]\n", Status);
   return  Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
index 87aaa95..f678161 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
@@ -165,5 +165,3 @@ DefinitionBlock (
     }
   } //End of Scope(\_SB)
 }   //End of DefinitionBlock
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
index 60ea236..345c49d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
@@ -461,4 +461,3 @@ TN_COMPLEX_CONFIG ComplexDataTN = {
     {0, 0, 0, 0, 0, 0}
   }
 };
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
index da962d5..15019e6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
@@ -972,4 +972,3 @@ PcieGetSbConfigInfoTN (
   LibAmdMemCopy (SbPort, &DefaultSbPortTN, sizeof (DefaultSbPortTN), StdHeader);
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
index 767268e..a6cd98f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
@@ -780,4 +780,3 @@ PcieEarlyInterfaceTN (
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
index 995f3c0..28d5cd0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
@@ -92,4 +92,3 @@ PcieEnvInterfaceTN (
   S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreTNS3Script_ID, 0, NULL);
   return  AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
index 49fdff3..6943eb7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
@@ -608,5 +608,3 @@ PcieOscInitTN (
   }
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Exit\n");
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
index 38b8fba..c4008a5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
@@ -51,4 +51,3 @@ PciePowerGateTN (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
index b6b98e0..8e715f5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
@@ -331,4 +331,3 @@ GnbIommuIvrsTableDump (
   IDS_HDT_CONSOLE (GNB_TRACE, "\n");
   IDS_HDT_CONSOLE (GNB_TRACE, "<----------  IVRS Table End -------------> \n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
index 807a78e..70e513c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
@@ -237,4 +237,3 @@ GnbIvmdAddEntry (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
index 9080571..346f35c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
@@ -401,5 +401,3 @@ GnbLocateLowestVidCode (
   ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0);
   return PpFuseArray->SclkVid[MinVidIndex];
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
index f5d5bd5..45546cc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
@@ -96,4 +96,3 @@ GnbLocateLowestVidCode (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
index 84a02d1..8b5038b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
@@ -590,4 +590,3 @@ GnbEnableIommuMmioV4 (
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Exit\n");
   return Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl
index ade2200..b120ef4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl
@@ -43,4 +43,3 @@
 */
 
   Name (varStringBuffer, Buffer (256) {})
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
index 0e2e73e..e8e99c4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
@@ -756,5 +756,3 @@ Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16})
       Store ("PcieClkPmConfigure Exit", Debug)
     }
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl
index 909630a..ed5860b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl
@@ -58,4 +58,3 @@
     AD01,
     varPcieBase
   )
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl
index 9dba662..5a7ec16 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl
@@ -259,4 +259,3 @@
       Store (Local0, ABDA)
     }
   }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl
index 70c074d..999c0c4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl
@@ -79,4 +79,3 @@
   Method (procPcieGetPortInfo, 1, NotSerialized) {
     return (DeRefOf (Index (varPortInfo, Arg0)))
   }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
index 9d4b959..576c664 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
@@ -131,5 +131,3 @@ GnbGetHostPciAddress (
   ASSERT (Handle != NULL);
   return Handle->Address;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
index ccec56d..445ba71 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
@@ -71,4 +71,3 @@ GnbGetHostPciAddress (
 #define GnbIsGnbConnectedToSb(Handle) (Handle != NULL ? ((Handle)->Address.AddressValue == 0x0) : FALSE)
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
index 1d16964..b603495 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
@@ -54,4 +54,3 @@ PcieLocateConfigurationData (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 6466862..5240563 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -797,4 +797,3 @@ PcieUserConfigConfigDump (
   }
   IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
index ab68e15..48e75de 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
@@ -218,4 +218,3 @@ PcieUserDescriptorConfigDump (
 #define PcieConfigGetStdHeader(Descriptor)         ((AMD_CONFIG_PARAMS *)((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header)))->StdHeader)
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
index 9de483c..312fccc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -245,4 +245,3 @@ PcieInputParserGetEngineDescriptor (
     return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
index b61e31b..e015725 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
@@ -80,4 +80,3 @@ PcieInputParserGetLengthOfPcieEnginesList (
   IN      CONST PCIe_COMPLEX_DESCRIPTOR       *Complex
   );
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
index 26515e3..d2e1b67 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -642,4 +642,3 @@ PcieIsDescriptorLinkWidthValid (
 
   return Result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
index e361f5d..517d43e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
@@ -53,5 +53,3 @@ PcieMapTopologyOnComplex (
  );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
index e627a8b..0bd1a73 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
@@ -188,4 +188,3 @@ PcieAspmGetMaxExitLatencyCallback (
   }
   return SCAN_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
index 5d534c3..184a79b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -227,4 +227,3 @@ PciePortRegisterRMW (
   Value = (Value & (~AndMask)) | OrMask;
   PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
index f9f5520..32f2c73 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
@@ -114,5 +114,3 @@ PciePollLinkForL0Exit (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
index 2a40c09..aa961a1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
@@ -393,5 +393,3 @@ PciePwrClockGating (
   }
   IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl
index a9b2b43..c1e0152 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl
@@ -57,4 +57,3 @@
     Increment (varCurrenLinkSpeedLocal2)
     return (varCurrenLinkSpeedLocal2)
   }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
index 92ec4c5..7525c29 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
@@ -254,4 +254,3 @@ PcieSiliconHidePorts (
   IDS_HDT_CONSOLE (GNB_TRACE, "Write D0F0x64_x0C.Value = %x\n", D0F0x64_x0C.Value);
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Exit\n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
index 4ed8e78..2894dff 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
@@ -214,4 +214,3 @@
     // ServiceId
     procNbSmuServiceRequest (0xB, 0x3)
   }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
index 45d762b..f31dbcc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
@@ -137,5 +137,3 @@ PcieWrapSetTxOffCtrlForLaneMux (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
index 8791091..3fd7bf2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
@@ -60,5 +60,3 @@ PcieInitPortForIommuV4 (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl
index a06f6a9..fa877c43 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl
@@ -74,5 +74,3 @@
 
     Store ("NbSmuServiceRequest Exit", Debug)
   }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
index e84be01..0251a82 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
@@ -73,5 +73,3 @@ PcieTopologySetLinkReversalV4 (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
index 47ed417..4b15cec 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
@@ -60,4 +60,3 @@ PcieTrainingSetPortState (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
index 0232991..96cf22c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
@@ -371,5 +371,3 @@ PcieIsDeskewCardDetected (
   }
   return FALSE;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
index a7f69f1..cd7bce5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
@@ -138,5 +138,3 @@ SbPcieInitAspm (
   GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader);
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htGraph.h
index b19c70a..c04fc59 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htGraph.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htGraph.h
@@ -140,4 +140,3 @@ GraphGetBc (
   );
 
 #endif  /* _HT_GRAPH_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c
index 2417ba1..466d035 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c
@@ -390,4 +390,3 @@ GetOverrideBusNumbers (
   // SecBus, SubBus are not valid if Result is FALSE.
   return result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c
index 89c4176..e071e2e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c
@@ -244,4 +244,3 @@ NewNorthBridge (
   // Set the config handle for passing to the library.
   Nb->ConfigHandle = State->ConfigHandle;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm
index fc00e67..d7f7794 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm
@@ -339,4 +339,3 @@ SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
 SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
 
 END
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c
index ac03192..8cb393a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c
@@ -411,5 +411,3 @@ CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock =
   IDS_FAMILY_ALL,
   IdsSubRestoreCmos
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h
index d106fca..578fdb9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h
@@ -80,4 +80,3 @@ IdsSubSaveBspNvHeapToCmos (
 #define IDS_NV_TO_CMOS_BYTE_IGNORED   0xFF
 #define IDS_NV_TO_CMOS_WORD_IGNORED   0xFFFF
 #endif  //_IDSNVTOCMOS_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
index 119cccf..348f94d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
@@ -198,5 +198,3 @@ IdsCarCorruptionCheck (
     }
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c
index 322339d..3dd6e0c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c
@@ -648,4 +648,3 @@ AmdIdsDebugPrintAll (
   AmdIdsDebugPrintProcess (TRACE_MASK_ALL, Format, Marker);
   VA_END (Marker);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h
index 7774c01..ed927a7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h
@@ -75,4 +75,3 @@ GetDebugPrintList (
 
 
 #endif //_IDS_DEBUGPRINT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c
index d05164d..0ce64ba 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c
@@ -746,6 +746,3 @@ CONST IDS_DEBUG_PRINT ROMDATA  IdsDebugPrintHdtoutInstance =
   AmdIdsHdtOutInitPrivateData,
   AmdIdsHdtOutPrint
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h
index 5dff545..6dd0195 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h
@@ -116,4 +116,3 @@ AmdIdsHdtOutSupport (
   );
 
 #endif //_IDS_HDTOUT_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c
index 3d875fa..bf4a373 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c
@@ -140,6 +140,3 @@ CONST IDS_DEBUG_PRINT ROMDATA  IdsDebugPrintRedirectIoInstance =
   AmdIdsRedirectIoInitPrivateData,
   AmdIdsRedirectIoPrint
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c
index b43ba7e..be6ef7e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c
@@ -179,6 +179,3 @@ CONST IDS_DEBUG_PRINT ROMDATA  IdsDebugPrintSerialInstance =
   AmdIdsSerialInitPrivateData,
   AmdIdsSerialPrint
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c
index 4ecc791..a427d7d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c
@@ -299,4 +299,3 @@ IdsUpdateExceptionVector (
   }
   return IDS_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c
index 517b19b..c36405a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c
@@ -49,4 +49,3 @@
 
 
 #define FILECODE PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h
index 3b43410..1b464d1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h
@@ -46,4 +46,3 @@
 #endif
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c
index 5e76e9a..7f4ea3c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c
@@ -389,5 +389,3 @@ CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn =
     AMD_FAMILY_15_TN,
     IdsRegSetGmmxF15Tn
   );
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h
index d3e6cce..52572e5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h
@@ -46,4 +46,3 @@
 #endif
 
 #endif  //_IDS_F15_TN_ALLSERVICE_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h
index d510820..8f89b3b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h
@@ -281,4 +281,3 @@ typedef enum {
 } IdsNvGnbNbIOMMU;
 
 #endif // _IDSF15TNNVDEF_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h
index 904e72d..6c82da4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h
@@ -414,4 +414,3 @@ IdsLibDataMaskSet32 (
 #define IDS_CPB_BOOST_DIS_IGNORE  0xFFFFFFFFul
 
 #endif //_IDS_LIB_H_
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
index 50aa2ee..97e9541 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
@@ -927,6 +927,3 @@ IdsLibDataMaskSet32 (
   *Value &= AndMask;
   *Value |= OrMask;
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c
index a79a27e..a7a9e6c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c
@@ -285,5 +285,3 @@ IdsRegSetPciIndirect (
   LibAmdPciWrite (PPciIndirectReg->Width, PciIndexPortAddr, &IndexValue, StdHeader);
   LibAmdPciWrite (PPciIndirectReg->Width, PciDataPortAddr, &Value, StdHeader);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h
index 85a0623..95f281c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h
@@ -149,5 +149,3 @@ IdsRegSetPciIndirect (
 );
 
 #endif  //_IDSREGACC_H_
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c
index c915806..73f2fd8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c
@@ -217,5 +217,3 @@ IdsPerfAnalyseTimestamp (
   }
   return status;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.h
index 474c2fa..63f38f0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.h
@@ -76,5 +76,3 @@ MemFInterleaveChannels (
   );
 
 #endif  /* _MFCHI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.h
index 8da11aa..fa2943f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -76,5 +76,3 @@ MemFInterleaveBanks (
   );
 
 #endif  /* _MFCSI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c
index 6620030..348d669 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c
@@ -647,4 +647,3 @@ MemFDMISupport2 (
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.h
index 64ffb27..2334839 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.h
@@ -76,5 +76,3 @@ MemFInitECC (
   );
 
 #endif  /* _MFECC_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 070ccd7..104e7ce 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -203,4 +203,3 @@ MemFRASExcludeDIMM (
   NBPtr->SwitchDCT (NBPtr, ReserveDCT);
   return RetVal;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
index c707e6d..b66f3f4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -159,5 +159,3 @@ MemFInterleaveRegion (
     }
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
index 41ed7a9..a874b93 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
@@ -76,5 +76,3 @@ MemFInterleaveRegion (
   );
 
 #endif  /* _MFINTLVRN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index dc7f01b..6bdade4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -148,4 +148,3 @@ MemFMctMemClr_Sync (
   }
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/TABLE/mftds.c
index d72d46d..791513f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/TABLE/mftds.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/TABLE/mftds.c
@@ -327,9 +327,3 @@ SetTableValues (
     }
   }
 }
-
-
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c
index 57ecb6f..3939595 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c
@@ -184,4 +184,3 @@ MemErrHandle (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c
index 770d36d..9a95765 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c
@@ -129,4 +129,3 @@ MemMStandardTraining (
   }
   return (BOOLEAN) (Die == mmPtr->DieCount);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c
index 2aacc91..f318ba7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c
@@ -242,4 +242,3 @@ MemMUmaAlloc (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm
index 5cbba92..4bf3e79 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm
@@ -493,4 +493,3 @@ MemUMFenceInstr PROC CALLCONV PUBLIC
 MemUMFenceInstr ENDP
 
     END
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c
index c5bf49f..23cfada 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c
@@ -126,4 +126,3 @@ MemNTechBlockSwitchTN (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
index 63195e0..4631057 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
@@ -500,4 +500,3 @@ MemNTrainingFlowUnb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpStn3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpStn3.c
index a66a686..b438733 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpStn3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mpStn3.c
@@ -172,5 +172,3 @@ CONST PSC_TBL_ENTRY TNMaxFreqTblEntSO = {
    sizeof (MaxFreqTNSODIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
    (VOID *)&MaxFreqTNSODIMM
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c
index 2f6ef5d..3fb8f9c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c
@@ -1216,4 +1216,3 @@ MemPCheckTblDrvOverrideConfigSpeedLimit (
 
   return FALSE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.h
index 0fbced2..a6add92 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.h
@@ -130,5 +130,3 @@ MemTGetDimmSpdBuffer3 (
   IN       UINT8 Dimm
   );
 #endif  /* _MT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.h
index b648c99..0484a71 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.h
@@ -86,5 +86,3 @@ MemTGetLD3 (
   );
 
 #endif  /* _MTOT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c
index 2d30833..230442b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -315,4 +315,3 @@ FreqChgCtrlWrd3 (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.h
index 36a6e49..2236bb8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.h
@@ -83,5 +83,3 @@ MemTDramControlRegInit3 (
   );
 
 #endif  /* _MTRCI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.h
index 04437fa..29f5539 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.h
@@ -92,5 +92,3 @@ MemTEMRS23 (
   );
 
 #endif  /* _MTSDI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
index acfd71d..c972961 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -1191,4 +1191,3 @@ MemTGetDimmSpdBuffer3 (
   }
   return DimmPresent;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h
index ab46e4a..aa73763 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -172,5 +172,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
index 46e591a..034a092 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c
@@ -903,4 +903,3 @@ MemTDataEyeSave (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.h
index f11c435..c9fe07a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.h
@@ -113,5 +113,3 @@ typedef struct _SWEEP_INFO {
 
 
 #endif  /* _MTTEDGEDETECT_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c
index 4ad3ea8..1889332 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c
@@ -342,4 +342,3 @@ MemTDqsTrainRcvrEnSw (
   IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n");
   return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h
index b85398a..664361b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h
@@ -109,5 +109,3 @@ MemFParallelTraining (
  );
 
 #endif  /* _MFPARALLELTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfStandardTraining.h
index 4e9f6b7..d03a92d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfStandardTraining.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfStandardTraining.h
@@ -77,5 +77,3 @@ MemFStandardTraining (
   );
 
 #endif  /* _MFSTANDARDTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfmemclr.h
index 4653646..5516cbe 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfmemclr.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfmemclr.h
@@ -79,5 +79,3 @@ MemFMctMemClr_Sync (
   );
 
 #endif  /* _MFMEMCLR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mftds.h
index 84bac73..ad69125 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mftds.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mftds.h
@@ -76,5 +76,3 @@ MemFInitTableDrive (
   IN       UINT8     time
   );
 #endif  /* _MFTDS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h
index 49ebb0a..b711823 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h
@@ -1347,5 +1347,3 @@ AmdMemFunctionListDef (
   IN OUT   VOID *pMemData
   );
 #endif  /* _MM_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
index 4be78a3..a9cfe66 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
@@ -1790,4 +1790,3 @@ MemNGetMemoryWidthUnb (
   );
 
 #endif  /* _MN_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mnreg.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mnreg.h
index 64a7f99..d9a3723 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mnreg.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mnreg.h
@@ -326,4 +326,3 @@ typedef struct {
  */
 
 #endif  /* _MNREG_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mu.h
index 2c6941d..2d58d9c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mu.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mu.h
@@ -233,5 +233,3 @@ MemUnsToMemClk (
   IN       UINT32 NumberOfns
   );
 #endif  /* _MU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/cpcar.inc b/src/vendorcode/amd/agesa/f15tn/cpcar.inc
index 7d17e99..818a327 100644
--- a/src/vendorcode/amd/agesa/f15tn/cpcar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/cpcar.inc
@@ -1524,6 +1524,3 @@ end_of_f15h_data:
     .endif
 node_core_f15_exit:
 ENDM
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index d6dd49a..6f47729 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -1933,4 +1933,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h
index a28dd5e..6ec20ba 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h
@@ -141,4 +141,3 @@
 #define OPTION_MICROSERVER                  TRUE
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h
index 987677e..057dcd9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h
@@ -1294,4 +1294,3 @@ NOTE: Members with type casting should use OvrdDfltCpuSrvc<ServiceName> instead
 //
 // Message out the final table definitions
 //
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h
index 923b621..0f0f5a7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h
@@ -542,4 +542,3 @@
 #define DfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable      NullCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
 #define DfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable       NullCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
 #define DfltCpuSrvcPatchLoaderIsSharedByCU                    NullCpuSrvcPatchLoaderIsSharedByCU
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
index db5588d..de248eb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
@@ -190,4 +190,3 @@ AddOneCratEntry (
   );
 
 #endif  // _OPTION_CRAT_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h
index 2b47e15..0ffaeb6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h
@@ -124,4 +124,3 @@ CONST S_MAKE_CRAT_ENTRY ROMDATA MakeCratEntryTable[] =
   {NULL}
 };
 #endif  // _OPTION_CRAT_INSTALL_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
index 1295888..f20f109 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
@@ -2362,4 +2362,3 @@ CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
 #if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
   CONST INT32 _fltused = 0;
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
index 7f03e13..348f7c7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
@@ -418,4 +418,3 @@ HeapGetBaseAddressInTempMem (
 {
   return UserOptions.CfgHeapDramAddress;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc
index 9d2870b..fb19e1a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc
@@ -459,4 +459,3 @@ ENDIF
 IFNDEF   BIT63
     BIT63                       EQU    8000000000000000h
 ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
index 02e5df9..4a75178 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
@@ -117,4 +117,3 @@ GetF16KbMicrocodeEquivalenceTable (
     *KbEquivalenceTablePtr = stu1;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c
index 97affa0..91699c0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c
@@ -104,4 +104,3 @@ GetF16KbLogicalIdAndRev (
   *KbIdPtr = CpuF16KbLogicalIdAndRevArray;
   *LogicalFamily = AMD_FAMILY_16_KB;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
index 4790709..61f11a8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
@@ -108,4 +108,3 @@ GetF16KbMicroCodePatchesStruct (
   *NumberOfElements = CpuF16KbNumberOfMicrocodePatches;
   *KbUcodePtr = &CpuF16KbMicroCodePatchArray[0];
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
index 253d518..6fed82a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
@@ -1127,4 +1127,3 @@ SetTdpLimitDis (
     LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&PciData, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
index 38913c1..6fa4a6e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
@@ -609,5 +609,3 @@ F16KbGetPllValueInTime (
     *PllLockTimePtr = 0;
   IDS_HDT_CONSOLE (CPU_TRACE, "    PllLockTimePtr=%d\n", *PllLockTimePtr);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c
index a953793..52682a4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c
@@ -108,5 +108,3 @@ CONST REGISTER_TABLE ROMDATA F16KbSharedMsrWorkaroundTable = {
   //(sizeof (F16KbSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *) &F16KbSharedMsrWorkarounds,
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
index ed94e79..4c625ec 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
@@ -1011,5 +1011,3 @@ F16KbCmnCalculateCurrentInmA (
 
   IDS_HDT_CONSOLE (CPU_TRACE, "    CurrentInmA=%d\n", *CurrentInmA);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
index 2330f18..0c1dda7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
@@ -121,4 +121,3 @@ CONST APM_FAMILY_SERVICES ROMDATA F16ApmSupport =
   (PF_APM_IS_SUPPORTED) CommonReturnTrue,
   F16InitializeApm
 };
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
index 444315a..85161c6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
@@ -163,4 +163,3 @@ F16SetBrandIdRegistersAtEarly (
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c
index b89daaa..3e42851 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c
@@ -126,4 +126,3 @@ GetF16CacheInfo (
   *NumberOfElements = 1;
   *CacheInfoPtr = &CpuF16CacheInfo;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c
index 5299228..9ed2c53 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c
@@ -101,4 +101,3 @@ CONST REGISTER_TABLE ROMDATA F16MsrUnknownRegisterTable = {
   (sizeof (F16MsrUnknownRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
   (TABLE_ENTRY_FIELDS *)F16MsrUnknownRegisters,
 };
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c
index 8774824..abe9aaf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c
@@ -413,5 +413,3 @@ F16CpuAmdCoreIdPositionInInitialApicId (
   InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
   return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h
index e635fb0..4c24674 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h
@@ -141,4 +141,3 @@ F16GetAgesaWarmResetFlag (
   );
 
 #endif  // _CPU_F16_UTILITES_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h
index cfd0dae..ca2340d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h
@@ -122,4 +122,3 @@
 #define AMD_F16_ALL      (AMD_F16_KB_ALL)
 
 #endif      // _CPU_FAM_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
index b5a38b8..0d282a5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
@@ -747,5 +747,3 @@ IsPowerOfTwo (
   }
   return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.h
index 24cc757..3db7118 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.h
@@ -135,4 +135,3 @@ AllocateExecutionCache (
   );
 
 #endif  // _CPU_CACHE_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c
index e02e870..919ead5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c
@@ -344,4 +344,3 @@ AcpiCditHBufferFind (
 
   return;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c
index b00e979..cf81622 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -371,4 +371,3 @@ CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
  *                          L O C A L      F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c
index 552713d..322df43 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c
@@ -510,4 +510,3 @@ AddOneCratEntry (
   }
   return CurrentEntry;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c
index 6ff30d2..e2fd3dd 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c
@@ -869,4 +869,3 @@ IntToString (
   }
   *(String + SizeInByte * 2) = 0x0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c
index 9d6ca3d..5c72b5c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c
@@ -615,4 +615,3 @@ STATIC
   }
   return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
 } // MakeMemEntry()
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c
index f41dca9..74f966e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c
@@ -285,4 +285,3 @@ CreateHestBank (
     HestBankPtr++;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c
index a27140b..aebe517 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c
@@ -924,4 +924,3 @@ SetRegistersFromTablesAfterApLaunch (
   AGESA_TESTPOINT (TpProcCpuProcessRegisterTables, StdHeader);
   SetRegistersFromTables (&EarlyParams->PlatformConfig, PERFORM_TP_AFTER_AP_LAUNCH, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
index 1f6341a..1a77d6d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h
@@ -1311,4 +1311,3 @@ GetPerformanceFeatures (
   );
 
 #endif  // _CPU_TABLE_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.h
index ee1a564..91aff3e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.h
@@ -300,4 +300,3 @@ GetIdtr (
   );
 
 #endif  /* _CPU_APIC_UTILITIES_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h
index ddbb571..c5611cf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h
@@ -287,4 +287,3 @@ McaInitialization (
   );
 
 #endif  // _CPU_EARLY_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h
index 309fc18..6cc35b3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h
@@ -1049,4 +1049,3 @@ GetEmptyArray (
   );
 
 #endif  // _CPU_FAMILY_TRANSLATION_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c
index 9e0451d..3572f1a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c
@@ -286,4 +286,3 @@ RunLateApTaskOnAllCore0s (
   }
   return AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.h
index 2d192fe..996119c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.h
@@ -230,4 +230,3 @@ SyncAllApMtrrToBsc (
   IN       AMD_CONFIG_PARAMS *StdHeader
   );
 #endif  // _CPU_POST_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSystemTables.h
index 64baf46..b206f3f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSystemTables.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSystemTables.h
@@ -90,4 +90,3 @@ typedef struct {
 
 
 #endif  // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h
index e59bb88..3b5377f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h
@@ -495,4 +495,3 @@ typedef enum {
 } CPUID_REG;
 
 #endif      // _CPU_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c
index 6aa5a76..e8f56ab 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c
@@ -231,4 +231,3 @@ SetWarmResetAtEarly (
  *                            L O C A L    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
index 42a6afa..1484dfc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
@@ -885,5 +885,3 @@ HeapGetCurrentBase (
   ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE));
   return ReturnPtr;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h
index 542faa6..270e911 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h
@@ -140,4 +140,3 @@ AmdAddMmioMapping (
   );
 
 #endif // _MMIO_MAP_MANAGER_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c
index 83de69b..dbb9863 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c
@@ -184,5 +184,3 @@ AmdInitEnv (
   IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
   return  AmdInitEnvStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c
index 92aeb47..9eb2bc6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c
@@ -320,4 +320,3 @@ AmdInitLate (
 
   return  AmdInitLateStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c
index 2bd4034..3c5dba3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c
@@ -174,5 +174,3 @@ AmdInitMid (
 
   return AgesaStatus;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c
index 842b159..ba54d36 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c
@@ -346,4 +346,3 @@ AmdInitPost (
 
   return  AmdInitPostStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
index 30e194e..15b39fa 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
@@ -254,4 +254,3 @@ AmdInitResetConstructor (
 
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c
index b7e125e..f3f6506 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c
@@ -156,4 +156,3 @@ AmdLateRunApTaskInitializer (
   AmdApExeParams->RelatedBlockLength = 0;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c
index 8947137..ba50455 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c
@@ -140,4 +140,3 @@ CommonPlatformConfigInit (
   }
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.h
index d08cbf8..5a1b7e4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.h
@@ -62,4 +62,3 @@ CommonPlatformConfigInit (
   );
 
 #endif // _COMMON_INITS_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c
index ec1dadf..ef1d082 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c
@@ -259,4 +259,3 @@ FchTaskDummy (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h
index 6b67f5f..e5dd0c1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h
@@ -192,4 +192,3 @@ AmdLateRunApTaskInitializer (
   IN OUT   AP_EXE_PARAMS     *AmdApExeParams
   );
 #endif // _CREATE_STRUCT_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
index 9da575c..439c330 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
@@ -438,4 +438,3 @@ S3RestoreStateFromTable (
   IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaLate.c
index fa7c5bd..138ba2a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaLate.c
@@ -56,4 +56,3 @@ FchInitLateAzalia (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaReset.c
index 0966e9f..b75dfa6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaReset.c
@@ -58,4 +58,3 @@ FchInitResetF1 (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.c
index 905025f..85b069e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.c
@@ -239,4 +239,3 @@ ReadFchSleepType (
   LibAmdIoRead (AccessWidth16, Value16, &Value16, StdHeader);
   return (UINT8) ((Value16 >> 10) & 7);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchBiosRamUsage.h
index 60e40d6..5023b4e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchBiosRamUsage.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchBiosRamUsage.h
@@ -64,4 +64,3 @@
 #define BOOT_TIME_FLAG_INT19                  0xFC
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommon.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommon.c
index c8f948d..bcaac00 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommon.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommon.c
@@ -44,4 +44,3 @@
 #include "FchPlatform.h"
 #include "heapManager.h"
 #define FILECODE PROC_FCH_COMMON_FCHCOMMON_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h
index 42a9bef..ff3ebf9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h
@@ -436,4 +436,3 @@ FchPlatformSpiQe (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/MemLib.c
index 08bd0f9..9fc14fb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/MemLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/MemLib.c
@@ -142,4 +142,3 @@ RwMem (
   WriteMem (Address, OpFlag, &Result);
   ReadMem (Address, OpFlag, &Result);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/PciLib.c
index 6ef1bd0..056842f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/PciLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/PciLib.c
@@ -90,5 +90,3 @@ RwPci (
   rMask = ~Mask;
   LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h
index c370d4c..b929561 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h
@@ -1626,4 +1626,3 @@ FCH_MISC_REGF0                   EQU     0F0h
 #ifndef FCH_DEADLOOP
   #define FCH_DEADLOOP()    { volatile UINTN __i; __i = 1; while (__i); }
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiLateService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiLateService.c
index 2913e6f..f117067 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiLateService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiLateService.c
@@ -147,6 +147,3 @@ StressResetModeLate (
   while (LocalCfgPtr->HwAcpi.StressResetMode) {
   }
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
index 68c9be7..ca7c2be 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
@@ -121,5 +121,3 @@ ProgramFchHwAcpiResetP (
   RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader);
   RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiEnv.c
index c8c878f..47cce3a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiEnv.c
@@ -99,4 +99,3 @@ FchInitEnvHwAcpi (
   ProgramSpecificFchInitEnvAcpiMmio (FchDataPtr);
   HpetInit (LocalCfgPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c
index db46136..b6b0d93 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c
@@ -164,4 +164,3 @@ IsGCPU (
     return FALSE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
index c9b5ffc..aec3422 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
@@ -238,5 +238,3 @@ FchInitResetHwAcpi (
     ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->OemResetProgrammingTablePtr), StdHeader);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmEnvService.c
index ea4ee73..c46d153 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmEnvService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmEnvService.c
@@ -84,4 +84,3 @@ HwmInitRegister (
   RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccessWidth8, 0, 0x00);
   RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xB6, AccessWidth8, 0x0F, 0x00);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmLateService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmLateService.c
index f26dfc9..8800e38 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmLateService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmLateService.c
@@ -186,4 +186,3 @@ FchECfancontrolservice (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/HwmLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/HwmLate.c
index 0adfd48..bcabd87 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/HwmLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/HwmLate.c
@@ -70,5 +70,3 @@ FchInitLateHwm (
   ImcWakeup (LocalCfgPtr);
     FchECfancontrolservice (LocalCfgPtr);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeEnv.c
index 16d9eff..c7f8da0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeEnv.c
@@ -58,6 +58,3 @@ FchInitEnvIde (
   )
 {
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeLate.c
index 2e2099d..3c0b41c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeLate.c
@@ -55,5 +55,3 @@ FchInitLateIde (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeMid.c
index cc4e088..22cb1f8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeMid.c
@@ -58,4 +58,3 @@ FchInitMidIde (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Family/Yangtze/YangtzeImcService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Family/Yangtze/YangtzeImcService.c
index c176d1e..637f053 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Family/Yangtze/YangtzeImcService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Family/Yangtze/YangtzeImcService.c
@@ -94,4 +94,3 @@ SoftwareToggleImcStrapping (
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD6 + 1, AccessWidth8, 0x7F, 0);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcLate.c
index 8bdb4c2..0d0c97b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcLate.c
@@ -57,5 +57,3 @@ FchInitLateEc (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcEnv.c
index 73d12c0..8bb9eac 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcEnv.c
@@ -137,4 +137,3 @@ ValidateImcFirmware (
     return  TRUE;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLate.c
index 340da0f..586e989 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLate.c
@@ -78,4 +78,3 @@ ImcDisarmSurebootTimer (
   ImcDisableSurebootTimer (LocalCfgPtr);
   LocalCfgPtr->Imc.ImcSureBootTimer = 0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcReset.c
index b9aee7b..64a7d54 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcReset.c
@@ -64,4 +64,3 @@ FchInitResetImc (
       RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD6 + 1, AccessWidth8, 0x7F, 0);
     }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
index f638e71..a12c810 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
@@ -355,5 +355,3 @@ FCH_DATA_BLOCK   InitEnvCfgDefault = {
     }
   }
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/ResetDefYangtze.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/ResetDefYangtze.c
index 77cb199..e0284aa 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/ResetDefYangtze.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/ResetDefYangtze.c
@@ -181,5 +181,3 @@ FCH_RESET_DATA_BLOCK   InitResetCfgDefault = {
   FALSE,                 // QeEnabled
   NULL                   // OemResetProgrammingTablePtr
 };
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
index f1ce3ab..e641167 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c
@@ -110,5 +110,3 @@ FchEnvConstructor (
   EnvParams->FchInterface = FchInterfaceDefault;
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitReset.c
index 97f60dd..d674268 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitReset.c
@@ -112,4 +112,3 @@ FchResetConstructor (
   ResetParams->FchInterface = FchResetInterfaceDefault;
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c
index e47611d..06041b4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c
@@ -99,4 +99,3 @@ FchInitS3LateRestore (
   AgesaStatus = FchTaskLauncher (&FchInitS3LateTaskTable[0], FchDataPtr, TpFchInitS3LateDispatching);
   FchDataPtr->Misc.S3Resume = 0;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchTaskLauncher.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchTaskLauncher.c
index cbf2dc79..a292080 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchTaskLauncher.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchTaskLauncher.c
@@ -66,4 +66,3 @@ FchTaskLauncher (
   }
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c
index 4bea9fb..5ae84c0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c
@@ -192,5 +192,3 @@ FchInitEnvCreatePrivateData (
   FchParams->Sd.SdClockControl           = UserOptions.FchBldCfg->CfgFchSdClockControl;
   return FchParams;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c
index 9cbffd7..f548797 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c
@@ -87,4 +87,3 @@ FchInitResetLoadPrivateDefault (
 
   return FchParams;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbEnv.c
index f8afabc..ae6ca53 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbEnv.c
@@ -76,4 +76,3 @@ FchInitEnvAbSpecial (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbLate.c
index 7cbd3a3..e18b3ac 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbLate.c
@@ -64,4 +64,3 @@ FchInitLateAb (
 
   FchAbLateProgram (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbMid.c
index ee53b58..1647b4a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbMid.c
@@ -59,4 +59,3 @@ FchInitMidAb (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbReset.c
index 0b96daf..da008e3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbReset.c
@@ -61,4 +61,3 @@ FchInitResetAb (
 {
   FchProgramAbPowerOnReset (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbResetService.c
index 506521d..dac2304 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbResetService.c
@@ -68,4 +68,3 @@ FchProgramAbPowerOnReset (
   RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE0, AccessWidth32, 00, ALINK_ACCESS_INDEX);
 
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieEnv.c
index b77d2ee..d96036e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieEnv.c
@@ -64,4 +64,3 @@ FchInitEnvPcie (
   //
   ProgramPcieNativeMode (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieLate.c
index a3639c7..46535a5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieLate.c
@@ -57,5 +57,3 @@ FchInitLatePcie (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieReset.c
index e874420..a7ee917 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieReset.c
@@ -59,5 +59,3 @@ FchInitResetPcie (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciMid.c
index dcffca5..37eb4b1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciMid.c
@@ -64,4 +64,3 @@ FchInitMidSataAhci (
   LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
   SataAhciSetDeviceNumMsi (LocalCfgPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c
index 0ae0993..82e3611 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c
@@ -220,5 +220,3 @@ FchProgramSataPhy (
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, 0x010, StdHeader);
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c
index 9b14467..88d79f4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c
@@ -121,5 +121,3 @@ FchInitResetSataProgram (
 
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
index 9f526d8..fb6e948 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
@@ -705,4 +705,3 @@ FchSataSetPortGenMode (
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDC, AccessWidth8, 0x7F, 0x80);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidEnv.c
index d91a572..d3a1967 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidEnv.c
@@ -71,4 +71,3 @@ FchInitEnvSataRaid  (
   StdHeader = LocalCfgPtr->StdHeader;
 
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLate.c
index 0de856d..ac28dd1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLate.c
@@ -61,5 +61,3 @@ FchInitLateSataRaid (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLib.c
index 26daf80..085d711 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLib.c
@@ -65,5 +65,3 @@ SataRaidSetDeviceNumMsi (
 
   SataSetDeviceNumMsi (LocalCfgPtr);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidMid.c
index 68af1ba..677805c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidMid.c
@@ -71,4 +71,3 @@ FchInitMidSataRaid (
   SataBar5setting (LocalCfgPtr, &Bar5);
   ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnv.c
index a5d83cf..7699a78 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnv.c
@@ -101,4 +101,3 @@ FchInitEnvSata (
 
   SataDisableWriteAccess (StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnvLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnvLib.c
index 7c6f7aa..8b51b10 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnvLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnvLib.c
@@ -85,4 +85,3 @@ SataSetIrqIntResource (
 
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLate.c
index 0366ea4..17aa2db 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLate.c
@@ -67,5 +67,3 @@ FchInitLateSataIde (
   SataBar5setting (LocalCfgPtr, &Bar5);
   ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLate.c
index b732baa..87bb516 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLate.c
@@ -113,4 +113,3 @@ FchInitLateSata (
   //
   SataDisableWriteAccess (StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c
index 0b88aa7..3ad04b3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c
@@ -255,4 +255,3 @@ FchSataDriveFpga (
 }
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataReset.c
index 70452dc..b9d898c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataReset.c
@@ -60,4 +60,3 @@ FchInitResetSata (
 {
   FchInitResetSataProgram ( FchDataPtr );
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c
index a56100a..af702ab 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c
@@ -44,4 +44,3 @@
 #include "FchPlatform.h"
 #include "Filecode.h"
 #define FILECODE PROC_FCH_SD_FAMILY_YANGTZE_YANGTZESDRESETSERVICE_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c
index 8f2d9ad..84161d4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c
@@ -44,4 +44,3 @@
 #include "FchPlatform.h"
 #include "Filecode.h"
 #define FILECODE PROC_FCH_SD_FAMILY_YANGTZE_YANGTZESDSERVICE_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdEnv.c
index c959d5b..f2a0c68 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdEnv.c
@@ -62,4 +62,3 @@ FchInitEnvSd (
 
   FchInitEnvSdProgram (FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdLate.c
index bb14e01..a05a447 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdLate.c
@@ -56,5 +56,3 @@ FchInitLateSd (
   )
 {
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdMid.c
index b5cd869..7f55326 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdMid.c
@@ -58,4 +58,3 @@ FchInitMidSd (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c
index e2f37bb..974ef4b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c
@@ -86,4 +86,3 @@ FchInitEnvLpcProgram (
 
   RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG28, AccessWidth32, (UINT32)~(BIT21 + BIT20 + BIT19), 0);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
index ab71bb9..2753ccf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
@@ -813,4 +813,3 @@ FchPlatformSpiQe (
   }
   return FALSE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcEnv.c
index 4ddbe59..96ea7ab 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcEnv.c
@@ -91,4 +91,3 @@ FchInitEnvLpc (
     RwPci ((LPC_BUS_DEV_FUN << 16) + 0x78, AccessWidth32, (UINT32)~BIT1, BIT1, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcReset.c
index 8cbd8eb..11c7280 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcReset.c
@@ -67,4 +67,3 @@ FchInitResetLpc (
   FchInitResetLpcProgram (FchDataPtr);
 
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciMid.c
index dca9dc4..84fc2e3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciMid.c
@@ -155,4 +155,3 @@ EhciInitAfterPciInit (
 {
   FchEhciInitAfterPciInit ( Value, FchDataPtr);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciReset.c
index d716606..ad377b1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciReset.c
@@ -59,4 +59,3 @@ FchInitResetEhci (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c
index 8959420..f85c5e6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c
@@ -186,4 +186,3 @@ FchEhciInitAfterPciInit (
     RwPmio (FCH_PMIOA_REGF4, AccessWidth8, (UINT32)~BIT2, BIT2, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciLateService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciLateService.c
index 15a1997..fa260ff 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciLateService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciLateService.c
@@ -45,4 +45,3 @@
 //
 // Declaration of local functions
 //
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciResetService.c
index 5652974..3a2137a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciResetService.c
@@ -115,4 +115,3 @@ FchInitResetXhciProgram (
     WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciReset.c
index 5926acb..f0ba292 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciReset.c
@@ -59,4 +59,3 @@ FchInitResetOhci (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbEnv.c
index 712c8c4..bf5b1ea 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbEnv.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbEnv.c
@@ -66,4 +66,3 @@ FchInitEnvUsb (
   FchSetUsbEnableReg (FchDataPtr);
   RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEE, AccessWidth8, (UINT32)~(BIT2), 0 );
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbLate.c
index 7a84ed7..bc2841a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbLate.c
@@ -64,4 +64,3 @@ FchInitLateUsb (
   StdHeader = LocalCfgPtr->StdHeader;
   RwPmio (FCH_PMIOA_REGF4, AccessWidth8, (UINT32)~BIT0, BIT0, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbMid.c
index 6b95148..a6e88f0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbMid.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbMid.c
@@ -65,4 +65,3 @@ FchInitMidUsb (
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, (UINT32)~BIT0, 0);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbReset.c
index d538f90..fc9230c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbReset.c
@@ -59,4 +59,3 @@ FchInitResetUsb (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciLate.c
index 37926c2..d252c8d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciLate.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciLate.c
@@ -59,4 +59,3 @@ FchInitLateUsbXhci (
 {
   FchInitLateUsbXhciProgram ( FchDataPtr );
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciReset.c
index 3cb5663..f6f291a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciReset.c
@@ -80,4 +80,3 @@ FchInitRecoveryXhci (
   )
 {
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h
index add5509..f451141 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h
@@ -96,4 +96,3 @@ typedef struct  {
 #pragma pack (pop)
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h
index 4458039..3e77ee3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h
@@ -1441,5 +1441,3 @@ typedef union {
 
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h
index 2968360..e655dfc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h
@@ -100,4 +100,3 @@ typedef struct {
 
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index 34990c5..1991dd5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -527,4 +527,3 @@ GnbLibLocateService (
   }
   return AGESA_UNSUPPORTED;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
index 0430fba..0e417a5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -139,5 +139,3 @@ GnbLibCpuPciIndirectWrite (
     GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
   } while ((OffsetRegisterValue & BIT31) == 0);
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
index 91af4bb..863e4cf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -173,4 +173,3 @@ GnbLocateHeapBuffer (
   }
   return LocHeapParams.BufferPtr;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
index 4e4fa7a..76b879b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -119,4 +119,3 @@ GnbLibIoRead (
 {
   LibAmdIoRead (Width, Address, Value, StdHeader);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
index ad6433b..ab04927 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -119,7 +119,3 @@ GnbLibMemRead (
 {
   LibAmdMemRead (Width, Address, Value, StdHeader);
 }
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c
index bbbede8..01839fc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c
@@ -153,5 +153,3 @@ GnbFmTimeStamp (
   }
   return 0;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
index f42e306..4465fdc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
@@ -512,4 +512,3 @@ PcieFmGetSbConfigInfo (
   }
   return Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
index 1ae93d4..721c216 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
@@ -241,5 +241,3 @@ GfxFmIsVbiosPosted (
   }
   return TRUE;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
index d7c2207..75b2105 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -131,5 +131,3 @@ GfxConfigPostInterface (
   IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status);
   return  Status;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
index 7b5f3ef..2b984d8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
@@ -501,4 +501,3 @@ GfxIntInfoTableDebugDumpV3 (
   IDS_HDT_CONSOLE (GFX_MISC, "    ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 0x%X\n", SystemInfoTableV3Ptr->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11);
   IDS_HDT_CONSOLE (GFX_MISC, "GfxIntInfoTableDebugDumpV3 Exit\n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c
index 7523736..8a1b1a0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c
@@ -188,5 +188,3 @@ GfxIsVbiosPostedKB (
 
   return (((D0F0xBC_xC0200000 >> 16) & 1) == 0) ? TRUE : FALSE;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c
index 476c7845..60ebd62 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c
@@ -158,4 +158,3 @@ GfxMidInterfaceKB (
   IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceKB Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
index 41b7b17..25a7c57 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
@@ -1018,5 +1018,3 @@ GnbLoadF1TableKB (
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadF1TableKB Exit [0x%x]\n", Status);
   return Status;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c
index ce6eda2..577ae2d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c
@@ -117,4 +117,3 @@ GnbPostInterfaceKB (
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceKB Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
index c5eb8a1..5868af2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c
@@ -257,4 +257,3 @@ GnbUraStreamSetKB (
     StreamSetAddress += StepLength;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c
index 2d75fce..cf142cf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c
@@ -118,5 +118,3 @@ GnbUraLocateRegTblKB (
   *UraTableAddress = (UINT32)((UINTN)(&UraTableKB));
   return;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c
index bc87dde..9994311 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c
@@ -622,5 +622,3 @@ PcieGetSbConfigInfoKB (
 {
   return AGESA_UNSUPPORTED;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c
index f0624d4..3f5de54 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c
@@ -935,4 +935,3 @@ PcieEarlyInterfaceKB (
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceKB Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c
index 9656f26..71135dc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c
@@ -91,4 +91,3 @@ PcieEnvInterfaceKB (
   S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreKBS3Script_ID, 0, NULL);
   return  AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c
index 61b0725..297d629 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c
@@ -460,4 +460,3 @@ PcieTopologySelectMasterPllKB (
 
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c
index 3a7c6ac..853cc8f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c
@@ -220,5 +220,3 @@ GnbNbIoapicInterface (
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbNbIoapicInterface Exit\n");
   return Status;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
index 4295657..26a17b8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
@@ -96,4 +96,3 @@ GnbLocateLowestVidCode (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
index b26679b..96ac880 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
@@ -383,4 +383,3 @@ GnbEnableIommuMmioV4 (
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Exit\n");
   return Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c
index 0fb763b..0194dc0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c
@@ -460,4 +460,3 @@ PcieAlibUpdatePciePortDataCallback (
     PortData->PcieLocalOverrideSpeed = PcieGen1;
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
index d498ad0..e63abc4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
@@ -131,5 +131,3 @@ GnbGetHostPciAddress (
   ASSERT (Handle != NULL);
   return Handle->Address;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
index 8fc9847..0d08a95 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
@@ -71,4 +71,3 @@ GnbGetHostPciAddress (
 #define GnbIsGnbConnectedToSb(Handle) (Handle != NULL ? ((Handle)->Address.AddressValue == 0x0) : FALSE)
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
index b38287c..83b0005 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
@@ -54,4 +54,3 @@ PcieLocateConfigurationData (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 8e5e3dd..7bef40e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -796,4 +796,3 @@ PcieUserConfigConfigDump (
   }
   IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n");
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
index 45e5e46..05dff9e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
@@ -218,4 +218,3 @@ PcieUserDescriptorConfigDump (
 #define PcieConfigGetStdHeader(Descriptor)         ((AMD_CONFIG_PARAMS *)((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header)))->StdHeader)
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
index 274dabb..c27927e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -274,4 +274,3 @@ PcieInputParserGetEngineDescriptor (
     return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
index c050ec5..613679b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
@@ -80,4 +80,3 @@ PcieInputParserGetLengthOfPcieEnginesList (
   IN      CONST PCIe_COMPLEX_DESCRIPTOR       *Complex
   );
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
index cb24a9b..7229183 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -642,4 +642,3 @@ PcieIsDescriptorLinkWidthValid (
 
   return Result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
index 9cd49db..21248c4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
@@ -53,5 +53,3 @@ PcieMapTopologyOnComplex (
  );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
index 3fc8561..d31e080 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -270,4 +270,3 @@ PciePortRegisterRMW (
   Value = (Value & (~AndMask)) | OrMask;
   PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
index 67c66bb..accff72 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
@@ -114,5 +114,3 @@ PciePollLinkForL0Exit (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
index 00ffd58..67d58d6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
@@ -131,5 +131,3 @@ PcieWrapSetTxOffCtrlForLaneMux (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
index b6f485f..dd57b3a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
@@ -60,5 +60,3 @@ PcieInitPortForIommuV4 (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
index 52002ff..3c1288d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
@@ -73,5 +73,3 @@ PcieTopologySetLinkReversalV4 (
   );
 
 #endif
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c
index 0b2be80..8c85226 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c
@@ -195,4 +195,3 @@ PcieSiliconEnablePortsV5 (
     EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
index edf8772..d4e4a64 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
@@ -373,4 +373,3 @@ PcieMaxPayloadInterface (
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieMaxPayloadInterface Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c
index 36044ac..02f1c53 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c
@@ -798,4 +798,3 @@ PcieTraining (
   IDS_PERF_TIMESTAMP (TP_ENDGNBPCIETRAINING, GnbLibGetHeader (Pcie));
   return Status;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h
index c31f73a..c6e35aa 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h
@@ -60,4 +60,3 @@ PcieTrainingSetPortState (
   );
 
 #endif
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c
index 159ea3e..2c256ac 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c
@@ -371,5 +371,3 @@ PcieIsDeskewCardDetected (
   }
   return FALSE;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
index cc8cbf8..c3c3315 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
@@ -138,5 +138,3 @@ SbPcieInitAspm (
   GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader);
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
index 2f40389..cec5234 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
@@ -327,4 +327,3 @@ GnbSmuFirmwareLoadV7 (
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV7 Exit\n");
   return AGESA_SUCCESS;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c
index 1c124d3..02c2135 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c
@@ -390,4 +390,3 @@ GetOverrideBusNumbers (
   // SecBus, SubBus are not valid if Result is FALSE.
   return result;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c
index 293274a..4d40d3c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c
@@ -248,4 +248,3 @@ NewNorthBridge (
   // Set the config handle for passing to the library.
   Nb->ConfigHandle = State->ConfigHandle;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm
index a6a97a2..1e21f1f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm
@@ -339,4 +339,3 @@ SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
 SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
 
 END
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
index d75bf3e..966d866 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
@@ -207,5 +207,3 @@ IdsCarCorruptionCheck (
     }
   }
 }
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c
index 4163d82..4aa565b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c
@@ -651,4 +651,3 @@ AmdIdsDebugPrintAll (
   AmdIdsDebugPrintProcess (TRACE_MASK_ALL, Format, Marker);
   VA_END (Marker);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.h b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.h
index fc1ac8d..21968b3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.h
@@ -77,4 +77,3 @@ GetDebugPrintList (
 
 
 #endif //_IDS_DEBUGPRINT_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c
index bde0514..e7153ea 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c
@@ -750,6 +750,3 @@ CONST IDS_DEBUG_PRINT ROMDATA  IdsDebugPrintHdtoutInstance =
   AmdIdsHdtOutInitPrivateData,
   AmdIdsHdtOutPrint
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.h b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.h
index ff41fb5..5677843 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.h
@@ -116,4 +116,3 @@ AmdIdsHdtOutSupport (
   );
 
 #endif //_IDS_HDTOUT_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpSerial.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpSerial.c
index 43d6bf6..b6dd7e3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpSerial.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpSerial.c
@@ -180,6 +180,3 @@ CONST IDS_DEBUG_PRINT ROMDATA  IdsDebugPrintSerialInstance =
   AmdIdsSerialInitPrivateData,
   AmdIdsSerialPrint
 };
-
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c
index fddf8eb..edeacd3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c
@@ -304,5 +304,3 @@ CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF16Kb =
     AMD_FAMILY_16_KB,
     IdsRegSetGmmxF16Kb
   );
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h
index 3288143..e4369f0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h
@@ -46,4 +46,3 @@
 #endif
 
 #endif  //_IDS_F16_KB_ALLSERVICE_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h
index c08bdb3..5776952 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h
@@ -284,4 +284,3 @@ typedef enum {
 } IdsNvGnbNbIOMMU;
 
 #endif // _IDSF16KBNVDEF_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/IdsLib.h
index 355cd1f..aa58b3f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/IdsLib.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/IdsLib.h
@@ -430,4 +430,3 @@ IdsLibDataMaskSet32 (
 #define IDS_CPB_BOOST_DIS_IGNORE  0xFFFFFFFFul
 
 #endif //_IDS_LIB_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c
index 50306bb..985fb56 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c
@@ -1010,6 +1010,3 @@ IdsLibDataMaskSet32 (
   *Value &= AndMask;
   *Value |= OrMask;
 }
-
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsRegAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsRegAcc.h
index 1b9e02c..4e18f58 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsRegAcc.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsRegAcc.h
@@ -165,5 +165,3 @@ IdsRegSetDr (
 
 
 #endif  //_IDSREGACC_H_
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.h
index b660f05..c472aff 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -76,5 +76,3 @@ MemFInterleaveBanks (
   );
 
 #endif  /* _MFCSI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.h
index a25b12e..2fabb04 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.h
@@ -76,5 +76,3 @@ MemFInitECC (
   );
 
 #endif  /* _MFECC_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index 475b04f..a9c3500 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -203,4 +203,3 @@ MemFRASExcludeDIMM (
   NBPtr->SwitchDCT (NBPtr, ReserveDCT);
   return RetVal;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c
index 5a0c675..1c0f2d4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -150,4 +150,3 @@ MemFMctMemClr_Sync (
   }
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/mftds.c
index accc96b0..1eb09f8 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/mftds.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/mftds.c
@@ -393,9 +393,3 @@ SetTableValues (
     }
   }
 }
-
-
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c
index 426ce58..cf003dd 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c
@@ -184,4 +184,3 @@ MemErrHandle (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c
index bb8bccb..14f424d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c
@@ -341,4 +341,3 @@ MemM2DTrainingWithAggressor (
 
   return (BOOLEAN) (Die == mmPtr->DieCount);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c
index 163fecd..e998a68 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c
@@ -259,4 +259,3 @@ MemMUmaAlloc (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm
index 8f14379..cc4f8ed 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm
@@ -493,4 +493,3 @@ MemUMFenceInstr PROC CALLCONV PUBLIC
 MemUMFenceInstr ENDP
 
     END
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c
index 29aebe3..3e5d34c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c
@@ -126,4 +126,3 @@ MemNTechBlockSwitchKB (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
index b76d9e8..6dc2be5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
@@ -626,4 +626,3 @@ MemNRegAccessFenceKB (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c
index 1b5350a..02db74d 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c
@@ -265,4 +265,3 @@ MemNSetOtherTimingKB (
   IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrrd     : %02x           Twrrd     : %02x\n", (UINT8) CDDTwrrd, (UINT8) Twrrd );
   IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO    : %02x           TrwtTO    : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO );
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c
index f9e62d0..0695458 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c
@@ -605,4 +605,3 @@ MemNSetEccExclusionRangeUnb (
  *
  *----------------------------------------------------------------------------
  */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
index 9499278..8e30e18 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
@@ -1646,4 +1646,3 @@ MemNAmpVoltageDispUnb (
   // FALSE return to skip normal voltage display if wanted
   return FALSE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c
index e52c216..3003b67 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c
@@ -1238,4 +1238,3 @@ MemNAgressorContinuousWritesUnb (
   NBPtr->TechPtr->ChipSel = CurrChipSel;
   NBPtr->SwitchDCT (NBPtr, CurrDct);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.h
index d737449..2312e66 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.h
@@ -130,5 +130,3 @@ MemTGetDimmSpdBuffer3 (
   IN       UINT8 Dimm
   );
 #endif  /* _MT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.h
index 05f0c41..7f3b185 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.h
@@ -86,5 +86,3 @@ MemTGetLD3 (
   );
 
 #endif  /* _MTOT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c
index bc7a5a0..66d5186 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -315,4 +315,3 @@ FreqChgCtrlWrd3 (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.h
index 7b2db43..c8f82b6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.h
@@ -83,5 +83,3 @@ MemTDramControlRegInit3 (
   );
 
 #endif  /* _MTRCI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.h
index 69461e3..b5954ea 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.h
@@ -92,5 +92,3 @@ MemTEMRS23 (
   );
 
 #endif  /* _MTSDI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c
index 5e20a3f..95cda11 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -1199,4 +1199,3 @@ MemTGetDimmSpdBuffer3 (
   }
   return DimmPresent;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h
index bf13c7f..e2832f2 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -176,5 +176,3 @@
 
 
 #endif  /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
index 01e63f8..9980fd7 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c
@@ -903,4 +903,3 @@ MemTDataEyeSave (
 
   return TRUE;
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.h
index 113f864..c49a614 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.h
@@ -113,5 +113,3 @@ typedef struct _SWEEP_INFO {
 
 
 #endif  /* _MTTEDGEDETECT_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c
index 7fcf6d0..1216a53 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c
@@ -342,4 +342,3 @@ MemTDqsTrainRcvrEnSw (
   IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n");
   return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
 }
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h
index 3124079..abdc63a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h
@@ -109,5 +109,3 @@ MemFParallelTraining (
  );
 
 #endif  /* _MFPARALLELTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfStandardTraining.h
index a8e076a..d62d3a9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfStandardTraining.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfStandardTraining.h
@@ -77,5 +77,3 @@ MemFStandardTraining (
   );
 
 #endif  /* _MFSTANDARDTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfmemclr.h
index 4babfa3..0c30e89 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfmemclr.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfmemclr.h
@@ -79,5 +79,3 @@ MemFMctMemClr_Sync (
   );
 
 #endif  /* _MFMEMCLR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mftds.h
index e830bfb..1b69a47 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mftds.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mftds.h
@@ -76,5 +76,3 @@ MemFInitTableDrive (
   IN       UINT8     time
   );
 #endif  /* _MFTDS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h
index bdb759e..2c72b1c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h
@@ -1496,5 +1496,3 @@ MemMRestoreScrubber (
   IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
   );
 #endif  /* _MM_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
index feddf9f..06a26f3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
@@ -1593,4 +1593,3 @@ MemNIntermediateMemclkFreqValUnb (
   IN OUT   VOID *OptParam
   );
 #endif  /* _MN_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnpmu.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnpmu.h
index 2f26c62..ecb88f3 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnpmu.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnpmu.h
@@ -239,4 +239,3 @@ MemNCalcMR2 (
   );
 
 #endif  /* _MNPMU_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnreg.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnreg.h
index 6b8cf8d..a5f326b 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnreg.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnreg.h
@@ -530,4 +530,3 @@ typedef union {
  */
 
 #endif  /* _MNREG_H_ */
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mu.h
index f415e52..7f1c488 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mu.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mu.h
@@ -239,5 +239,3 @@ MemUnsToMemClk (
   IN       UINT32 NumberOfns
   );
 #endif  /* _MU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index 90c8cc6..d5b8122 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -1298,4 +1298,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/cimx/rd890/HotplugFirmware.h b/src/vendorcode/amd/cimx/rd890/HotplugFirmware.h
index a0b416f..260bec8 100644
--- a/src/vendorcode/amd/cimx/rd890/HotplugFirmware.h
+++ b/src/vendorcode/amd/cimx/rd890/HotplugFirmware.h
@@ -1394,4 +1394,3 @@ SMU_FIRMWARE_HEADER Fm = {
   &FmBlockArray[0]
 };
 #endif
-
diff --git a/src/vendorcode/amd/cimx/rd890/nbHtInterface.c b/src/vendorcode/amd/cimx/rd890/nbHtInterface.c
index ecb5e0d..c0deb13 100644
--- a/src/vendorcode/amd/cimx/rd890/nbHtInterface.c
+++ b/src/vendorcode/amd/cimx/rd890/nbHtInterface.c
@@ -122,4 +122,3 @@ NbHtInit (
   CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBHT_TRACE), "[NBHT]NbHtInit Exit [0x%x]\n", Status));
   return  Status;
 }
-
diff --git a/src/vendorcode/amd/cimx/rd890/nbInit.c b/src/vendorcode/amd/cimx/rd890/nbInit.c
index 8a5c5db..7451d8a 100644
--- a/src/vendorcode/amd/cimx/rd890/nbInit.c
+++ b/src/vendorcode/amd/cimx/rd890/nbInit.c
@@ -413,5 +413,3 @@ NbLibInitializer (
   pNbConfig->UnitIdClumping = 3;
   return AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c
index 8394835..6cdaffd 100644
--- a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c
+++ b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c
@@ -118,4 +118,3 @@ NbMaskedMemoryInit (
   LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG88, AccessS3SaveWidth32, 0x0, 0xffffffff, pConfig);
   return Status;
 }
-
diff --git a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit32.S b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit32.S
index 3c148aa..ae8b6c0 100644
--- a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit32.S
+++ b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit32.S
@@ -114,4 +114,3 @@ DoneInit:
         pop     %ebp
         ret
 NbInitMaskedMemoryLength = ( . - NbInitMaskedMemory)
-
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c b/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
index 17ae4f7..2977399 100644
--- a/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
@@ -502,4 +502,3 @@ PcieForcePortsVisibleOrDisable (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/cimx/rd890/nbRecovery.c b/src/vendorcode/amd/cimx/rd890/nbRecovery.c
index 71c6959..15c3bbe 100644
--- a/src/vendorcode/amd/cimx/rd890/nbRecovery.c
+++ b/src/vendorcode/amd/cimx/rd890/nbRecovery.c
@@ -188,5 +188,3 @@ MiscRecoveryInitializer (
 {
   return  AGESA_SUCCESS;
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.c b/src/vendorcode/amd/cimx/sb700/ACPILIB.c
index 807b166..d56ee7a 100644
--- a/src/vendorcode/amd/cimx/sb700/ACPILIB.c
+++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.c
@@ -117,4 +117,3 @@ UINT8  ACPI_GetTableChecksum(
 {
 	return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length);
 }
-
diff --git a/src/vendorcode/amd/cimx/sb700/AZALIA.c b/src/vendorcode/amd/cimx/sb700/AZALIA.c
index cc72858..f384a5c 100644
--- a/src/vendorcode/amd/cimx/sb700/AZALIA.c
+++ b/src/vendorcode/amd/cimx/sb700/AZALIA.c
@@ -301,4 +301,3 @@ void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32
 		++tempAzaliaCodecEntryPtr;
 	}
 }
-
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c
index 7d5b4f4..49e77eb 100644
--- a/src/vendorcode/amd/cimx/sb700/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c
@@ -569,4 +569,3 @@ void c3PopupSetting(AMDSBCFG* pConfig){
         RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7);
 
 }
-
diff --git a/src/vendorcode/amd/cimx/sb700/SBPOR.c b/src/vendorcode/amd/cimx/sb700/SBPOR.c
index 6c5740b..180ccac 100644
--- a/src/vendorcode/amd/cimx/sb700/SBPOR.c
+++ b/src/vendorcode/amd/cimx/sb700/SBPOR.c
@@ -438,4 +438,3 @@ void AMDFamily15CpuLdtStopReq(void) {
   }
 
 }
-
diff --git a/src/vendorcode/amd/cimx/sb800/ACPILIB.c b/src/vendorcode/amd/cimx/sb800/ACPILIB.c
index bc11209..dadacf8 100644
--- a/src/vendorcode/amd/cimx/sb800/ACPILIB.c
+++ b/src/vendorcode/amd/cimx/sb800/ACPILIB.c
@@ -163,4 +163,3 @@ GetSbAcpiPmBase (
 {
   ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase);
 }
-
diff --git a/src/vendorcode/amd/cimx/sb800/AMDLIB.c b/src/vendorcode/amd/cimx/sb800/AMDLIB.c
index 90e9e27..acdf951 100644
--- a/src/vendorcode/amd/cimx/sb800/AMDLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/AMDLIB.c
@@ -89,4 +89,3 @@ rwAlink (
   }
   writeAlink (Index, (readAlink (Index) & AndMask) | OrMask );
 }
-
diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c
index ccb4f90..cf24586 100644
--- a/src/vendorcode/amd/cimx/sb800/AZALIA.c
+++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c
@@ -509,4 +509,3 @@ configureAzaliaSetConfigD4Dword (
     ++tempAzaliaCodecEntryPtr;
   }
 }
-
diff --git a/src/vendorcode/amd/cimx/sb800/ECLIB.c b/src/vendorcode/amd/cimx/sb800/ECLIB.c
index 54d87e7..fc8fe63 100644
--- a/src/vendorcode/amd/cimx/sb800/ECLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/ECLIB.c
@@ -153,4 +153,3 @@ RWEC8 (
 }
 
 // #endif
-
diff --git a/src/vendorcode/amd/cimx/sb800/ECfan.h b/src/vendorcode/amd/cimx/sb800/ECfan.h
index 3fd5fea..d1c197a 100644
--- a/src/vendorcode/amd/cimx/sb800/ECfan.h
+++ b/src/vendorcode/amd/cimx/sb800/ECfan.h
@@ -66,5 +66,3 @@ VOID ReadECmsg (IN UINT8  Address, IN UINT8 OpFlag, OUT VOID* Value);
 #define MSG_REGB  0x8D
 #define MSG_REGC  0x8E
 #define MSG_REGD  0x8F
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/ECfanLIB.c b/src/vendorcode/amd/cimx/sb800/ECfanLIB.c
index 9ac6c88..9dde36c 100644
--- a/src/vendorcode/amd/cimx/sb800/ECfanLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/ECfanLIB.c
@@ -92,5 +92,3 @@ WaitForEcLDN9MailboxCmdAck (
     SbStall (1000); // Wait for 1ms
   }
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c
index d1715bc..77bb3c8 100644
--- a/src/vendorcode/amd/cimx/sb800/GEC.c
+++ b/src/vendorcode/amd/cimx/sb800/GEC.c
@@ -141,5 +141,3 @@ gecInitLatePost (
     return;   //return if GEC controller is disabled.
   }
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/MEMLIB.c b/src/vendorcode/amd/cimx/sb800/MEMLIB.c
index 5531c62..08bea1e 100644
--- a/src/vendorcode/amd/cimx/sb800/MEMLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/MEMLIB.c
@@ -92,5 +92,3 @@ RWMEM (
   Result = (Result & Mask) | Data;
   WriteMEM (Address, OpFlag, &Result);
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index c2f2162..7c5c8a6 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -671,5 +671,3 @@ sataInitLatePost (
     RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00);
   }
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/SB800.h b/src/vendorcode/amd/cimx/sb800/SB800.h
index 861a770..53b366d 100644
--- a/src/vendorcode/amd/cimx/sb800/SB800.h
+++ b/src/vendorcode/amd/cimx/sb800/SB800.h
@@ -1899,4 +1899,3 @@ SB_MISC_REGF0                   EQU     0F0h
 
 
 #pragma pack (pop)
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBDEF.h b/src/vendorcode/amd/cimx/sb800/SBDEF.h
index 79310fd..d56a414 100644
--- a/src/vendorcode/amd/cimx/sb800/SBDEF.h
+++ b/src/vendorcode/amd/cimx/sb800/SBDEF.h
@@ -258,4 +258,3 @@ void GetSbAcpiMmioBase (OUT unsigned int* AcpiMmioBase);
 void GetSbAcpiPmBase (OUT  unsigned short* AcpiPmBase);
 
 // #endif
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
index eb21770..12d9a54 100644
--- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
@@ -254,5 +254,3 @@ CallBackToOEM (
 
   return Result;
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h b/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
index 6b8c8d4..f22f7a1 100644
--- a/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
+++ b/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
@@ -520,4 +520,3 @@ void azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);
  */
   void  hwmInit (IN AMDSBCFG* pConfig);
 #endif
-
diff --git a/src/vendorcode/amd/cimx/sb800/SMM.c b/src/vendorcode/amd/cimx/sb800/SMM.c
index 894ec2a..c2be244 100644
--- a/src/vendorcode/amd/cimx/sb800/SMM.c
+++ b/src/vendorcode/amd/cimx/sb800/SMM.c
@@ -79,8 +79,3 @@ softwareSMIservice (
   )
 {
 }
-
-
-
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/USB.c b/src/vendorcode/amd/cimx/sb800/USB.c
index 14794cd..451b1d0 100644
--- a/src/vendorcode/amd/cimx/sb800/USB.c
+++ b/src/vendorcode/amd/cimx/sb800/USB.c
@@ -428,4 +428,3 @@ usbSetPllDuringS3 (
   RWPCI ((UINT32) (USB3_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);
 
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/AcpiLib.c b/src/vendorcode/amd/cimx/sb900/AcpiLib.c
index 2b8a389..fe584fb 100644
--- a/src/vendorcode/amd/cimx/sb900/AcpiLib.c
+++ b/src/vendorcode/amd/cimx/sb900/AcpiLib.c
@@ -176,4 +176,3 @@ SetAcpiPma (
   WriteIo8 (pmaBase, pmaControl);
   RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, ~BIT7, pmaControl << 7);
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/AmdLib.c b/src/vendorcode/amd/cimx/sb900/AmdLib.c
index 415b4ba..0cdebe7 100644
--- a/src/vendorcode/amd/cimx/sb900/AmdLib.c
+++ b/src/vendorcode/amd/cimx/sb900/AmdLib.c
@@ -86,4 +86,3 @@ rwAlink (
   }
   writeAlink (Index, ((readAlink (Index) & AndMask) | OrMask) );
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.c b/src/vendorcode/amd/cimx/sb900/AmdSbLib.c
index 72023af..31f77fc 100644
--- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.c
+++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.c
@@ -333,4 +333,3 @@ SbEnableUsbIrq1Irq12ToPicApic (
 {
   ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) |= (BIT1);
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h
index cf9589b..958dd55 100644
--- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h
+++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h
@@ -109,4 +109,3 @@ void SbFlashUsbSmi (void);
 
 /**< SbEnableUsbIrq1Irq12ToPicApic - Reserved  */
 void SbEnableUsbIrq1Irq12ToPicApic (void);
-
diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c
index 9a32018..eab64c7 100644
--- a/src/vendorcode/amd/cimx/sb900/Azalia.c
+++ b/src/vendorcode/amd/cimx/sb900/Azalia.c
@@ -514,4 +514,3 @@ configureAzaliaSetConfigD4Dword (
     ++tempAzaliaCodecEntryPtr;
   }
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/EcFan.h b/src/vendorcode/amd/cimx/sb900/EcFan.h
index c3d0f36..e8dbd5a 100644
--- a/src/vendorcode/amd/cimx/sb900/EcFan.h
+++ b/src/vendorcode/amd/cimx/sb900/EcFan.h
@@ -62,5 +62,3 @@ void ReadECmsg (IN unsigned char  Address, IN unsigned char OpFlag, OUT void* Va
 #define MSG_REGB  0x8D
 #define MSG_REGC  0x8E
 #define MSG_REGD  0x8F
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/EcFanLib.c b/src/vendorcode/amd/cimx/sb900/EcFanLib.c
index 57feae1..4d2313f 100644
--- a/src/vendorcode/amd/cimx/sb900/EcFanLib.c
+++ b/src/vendorcode/amd/cimx/sb900/EcFanLib.c
@@ -282,4 +282,3 @@ imcThermalZoneEnable (
     }
   }
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/EcFanc.c b/src/vendorcode/amd/cimx/sb900/EcFanc.c
index 2cc8106..098e093 100644
--- a/src/vendorcode/amd/cimx/sb900/EcFanc.c
+++ b/src/vendorcode/amd/cimx/sb900/EcFanc.c
@@ -185,5 +185,3 @@ hwmImcInit (
     sbECfancontrolservice (pConfig);
   }
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/EcLib.c b/src/vendorcode/amd/cimx/sb900/EcLib.c
index 44e196b..851cdc7 100644
--- a/src/vendorcode/amd/cimx/sb900/EcLib.c
+++ b/src/vendorcode/amd/cimx/sb900/EcLib.c
@@ -150,4 +150,3 @@ RWEC8 (
 }
 
 // #endif
-
diff --git a/src/vendorcode/amd/cimx/sb900/Gec.c b/src/vendorcode/amd/cimx/sb900/Gec.c
index cab95b5..6cc7cff 100644
--- a/src/vendorcode/amd/cimx/sb900/Gec.c
+++ b/src/vendorcode/amd/cimx/sb900/Gec.c
@@ -137,5 +137,3 @@ gecInitLatePost (
   }
   TRACE ((DMSG_SB_TRACE, "Exiting Prepare GEC controller to boot to OS\n"));
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/Gpp.c b/src/vendorcode/amd/cimx/sb900/Gpp.c
index 5bc6e18..9b1da73 100644
--- a/src/vendorcode/amd/cimx/sb900/Gpp.c
+++ b/src/vendorcode/amd/cimx/sb900/Gpp.c
@@ -1106,4 +1106,3 @@ sbPcieGppEarlyInit (
   sbGppDynamicPowerSaving (pConfig);
   outPort80 (0x9F);
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/GppHp.c b/src/vendorcode/amd/cimx/sb900/GppHp.c
index d87b904..d14e69f 100644
--- a/src/vendorcode/amd/cimx/sb900/GppHp.c
+++ b/src/vendorcode/amd/cimx/sb900/GppHp.c
@@ -163,4 +163,3 @@ sbGppHotplugSmiCallback (
     sbGppHotUnplugSmiProcess (pConfig, HpPort);
   }
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/Hudson-2.h b/src/vendorcode/amd/cimx/sb900/Hudson-2.h
index 0b9830e..f4b59d8 100644
--- a/src/vendorcode/amd/cimx/sb900/Hudson-2.h
+++ b/src/vendorcode/amd/cimx/sb900/Hudson-2.h
@@ -2065,4 +2065,3 @@ SB_MISC_REGF0                   EQU     0F0h
 //#define SB_XHCI1_OVER_CURRENT_CONTROL                           0x66666666
 
 #pragma pack (pop)
-
diff --git a/src/vendorcode/amd/cimx/sb900/MemLib.c b/src/vendorcode/amd/cimx/sb900/MemLib.c
index 801f049..9f1c1b9 100644
--- a/src/vendorcode/amd/cimx/sb900/MemLib.c
+++ b/src/vendorcode/amd/cimx/sb900/MemLib.c
@@ -89,5 +89,3 @@ RWMEM (
   Result = (Result & Mask) | Data;
   WriteMEM (Address, OpFlag, &Result);
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/OEM.h b/src/vendorcode/amd/cimx/sb900/OEM.h
index 8c9b9a6..37c11bd 100644
--- a/src/vendorcode/amd/cimx/sb900/OEM.h
+++ b/src/vendorcode/amd/cimx/sb900/OEM.h
@@ -230,4 +230,3 @@
  *
  */
 #define PCIB_SSID                    0x780F1022
-
diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c
index 9d1655c..94c9a6b 100644
--- a/src/vendorcode/amd/cimx/sb900/Sata.c
+++ b/src/vendorcode/amd/cimx/sb900/Sata.c
@@ -1038,5 +1038,3 @@ sataInitLatePost (
     RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00);
   }
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h b/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h
index 7c89da0..d53c7d4 100644
--- a/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h
+++ b/src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h
@@ -50,4 +50,3 @@
 #define BOOT_TIME_FLAG_INT19          0xFC
 
 #endif
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c
index 1767ea1..75ddd2d 100644
--- a/src/vendorcode/amd/cimx/sb900/SbCmn.c
+++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c
@@ -1541,4 +1541,3 @@ RecordSmiStatus (
   SwSmiValue = ReadIo8 (0xb0);
   ACPIMMIO8 (0xfed10040) = SwSmiValue;
 }
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbDef.h b/src/vendorcode/amd/cimx/sb900/SbDef.h
index 91fec4a..5f0a6d2 100644
--- a/src/vendorcode/amd/cimx/sb900/SbDef.h
+++ b/src/vendorcode/amd/cimx/sb900/SbDef.h
@@ -419,4 +419,3 @@ unsigned char IsUmiOneLaneGen1Mode ( OUT void );
  */
 void RecordSmiStatus ( OUT void );
 // #endif
-
diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c
index 958e44b..52ff59c 100644
--- a/src/vendorcode/amd/cimx/sb900/SbMain.c
+++ b/src/vendorcode/amd/cimx/sb900/SbMain.c
@@ -291,5 +291,3 @@ CallBackToOEM (
   TRACE ((DMSG_SB_TRACE, "SB Hook Status [ % x]\n", Result));
   return Result;
 }
-
-
diff --git a/src/vendorcode/amd/cimx/sb900/Smm.c b/src/vendorcode/amd/cimx/sb900/Smm.c
index 51a4ccc..decac49 100644
--- a/src/vendorcode/amd/cimx/sb900/Smm.c
+++ b/src/vendorcode/amd/cimx/sb900/Smm.c
@@ -81,8 +81,3 @@ softwareSMIservice (
 {
   TRACE ((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
 }
-
-
-
-
-
diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig
index 567d5a9..d3f8590 100644
--- a/src/vendorcode/google/Kconfig
+++ b/src/vendorcode/google/Kconfig
@@ -17,4 +17,3 @@
 ##
 
 source src/vendorcode/google/chromeos/Kconfig
-

