[coreboot-gerrit] Patch set updated for coreboot: f51a891 Capitalize CPU, RAM and ROM
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Sun Jul 27 23:23:38 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6383
-gerrit
commit f51a8911e6d6e9f0b40a8e8950656d291327ddc4
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Jul 27 17:12:45 2014 +0200
Capitalize CPU, RAM and ROM
Change-Id: I06dd453afbc5067152b064e8818d5fddde572d89
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
Makefile.inc | 4 ++--
documentation/CorebootBuildingGuide.tex | 16 +++++++--------
documentation/Kconfig.tex | 6 +++---
documentation/RFC/config.tex | 2 +-
payloads/libpayload/arch/x86/rom_media.c | 2 +-
payloads/libpayload/libcbfs/cbfs.c | 4 ++--
src/arch/armv7/ramstage.ld | 8 ++++----
src/arch/x86/lib/c_start.S | 2 +-
src/arch/x86/lib/rom_media.c | 2 +-
src/arch/x86/lib/walkcbfs.S | 2 +-
src/arch/x86/ramstage.ld | 8 ++++----
src/cpu/Makefile.inc | 2 +-
src/cpu/amd/agesa/family10/model_10_init.c | 2 +-
src/cpu/amd/agesa/family12/model_12_init.c | 2 +-
src/cpu/amd/agesa/family14/model_14_init.c | 2 +-
src/cpu/amd/agesa/family15/model_15_init.c | 2 +-
src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +-
src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +-
src/cpu/amd/agesa/s3_resume.c | 2 +-
src/cpu/amd/car/post_cache_as_ram.c | 4 ++--
src/cpu/amd/geode_gx1/geode_gx1_init.c | 2 +-
src/cpu/amd/geode_gx2/cache_as_ram.inc | 2 +-
src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +-
src/cpu/amd/geode_lx/cache_as_ram.inc | 2 +-
src/cpu/amd/geode_lx/cpubug.c | 2 +-
src/cpu/amd/geode_lx/geode_lx_init.c | 2 +-
src/cpu/amd/model_10xxx/init_cpus.c | 2 +-
src/cpu/amd/model_10xxx/model_10xxx_init.c | 2 +-
src/cpu/amd/model_fxx/fidvid.c | 2 +-
src/cpu/amd/model_fxx/init_cpus.c | 4 ++--
src/cpu/amd/model_fxx/model_fxx_init.c | 8 ++++----
src/cpu/amd/sc520/raminit.c | 4 ++--
src/cpu/amd/sc520/sc520.c | 2 +-
src/cpu/dmp/vortex86ex/biosdata_ex.inc | 4 ++--
src/cpu/intel/Makefile.inc | 2 +-
src/cpu/intel/ep80579/ep80579_init.c | 2 +-
src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 8 ++++----
src/cpu/intel/haswell/cache_as_ram.inc | 2 +-
src/cpu/intel/haswell/haswell_init.c | 2 +-
src/cpu/intel/haswell/romstage.c | 6 +++---
src/cpu/intel/haswell/smmrelocate.c | 2 +-
src/cpu/intel/hyperthreading/intel_sibling.c | 10 ++++-----
src/cpu/intel/microcode/Makefile.inc | 2 +-
src/cpu/intel/model_1067x/model_1067x_init.c | 4 ++--
src/cpu/intel/model_106cx/model_106cx_init.c | 4 ++--
src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++----
src/cpu/intel/model_206ax/cache_as_ram.inc | 2 +-
src/cpu/intel/model_206ax/model_206ax_init.c | 8 ++++----
src/cpu/intel/model_65x/model_65x_init.c | 2 +-
src/cpu/intel/model_67x/model_67x_init.c | 2 +-
src/cpu/intel/model_68x/model_68x_init.c | 2 +-
src/cpu/intel/model_69x/model_69x_init.c | 2 +-
src/cpu/intel/model_6bx/model_6bx_init.c | 2 +-
src/cpu/intel/model_6dx/model_6dx_init.c | 2 +-
src/cpu/intel/model_6ex/model_6ex_init.c | 4 ++--
src/cpu/intel/model_6fx/model_6fx_init.c | 4 ++--
src/cpu/intel/model_6xx/model_6xx_init.c | 2 +-
src/cpu/intel/model_f0x/model_f0x_init.c | 2 +-
src/cpu/intel/model_f1x/model_f1x_init.c | 2 +-
src/cpu/intel/model_f2x/model_f2x_init.c | 4 ++--
src/cpu/intel/model_f3x/model_f3x_init.c | 4 ++--
src/cpu/intel/model_f4x/model_f4x_init.c | 4 ++--
src/cpu/via/c3/c3_init.c | 2 +-
src/cpu/via/c7/c7_init.c | 4 ++--
src/cpu/via/nano/nano_init.c | 2 +-
src/cpu/x86/16bit/entry16.inc | 4 ++--
src/cpu/x86/16bit/reset16.lds | 2 +-
src/cpu/x86/lapic/lapic_cpu_init.c | 24 +++++++++++-----------
src/cpu/x86/mp_init.c | 6 +++---
src/cpu/x86/mtrr/earlymtrr.c | 2 +-
src/cpu/x86/sipi_vector.S | 4 ++--
src/cpu/x86/smm/smm_module_loader.c | 8 ++++----
src/cpu/x86/smm/smm_stub.S | 8 ++++----
src/cpu/x86/smm/smmrelocate.S | 4 ++--
src/device/cpu_device.c | 2 +-
src/device/oprom/realmode/x86_asm.S | 2 +-
src/device/oprom/yabel/debug.h | 2 +-
src/drivers/pc80/vga/vga.c | 2 +-
src/include/console/post_codes.h | 6 +++---
src/include/cpu/x86/cache.h | 2 +-
src/include/cpu/x86/msr.h | 2 +-
src/include/rmodule.h | 2 +-
src/lib/cbfs.c | 4 ++--
src/lib/cbmem_console.c | 2 +-
src/lib/selfboot.c | 2 +-
src/lib/thread.c | 2 +-
src/mainboard/amd/dinar/romstage.c | 2 +-
src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +-
src/mainboard/asus/m2v/romstage.c | 2 +-
src/mainboard/emulation/qemu-i440fx/northbridge.c | 2 +-
src/mainboard/getac/p470/cmos.layout | 2 +-
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +-
src/mainboard/gigabyte/m57sli/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo/Makefile.inc | 2 +-
src/mainboard/google/bolt/Makefile.inc | 2 +-
src/mainboard/google/falco/Makefile.inc | 2 +-
src/mainboard/google/link/Makefile.inc | 2 +-
src/mainboard/google/peppy/Makefile.inc | 2 +-
src/mainboard/google/rambi/spd/Makefile.inc | 2 +-
src/mainboard/google/slippy/Makefile.inc | 2 +-
src/mainboard/hp/dl145_g1/dsdt.asl | 2 +-
src/mainboard/ibase/mb899/cmos.layout | 2 +-
src/mainboard/intel/d945gclf/cmos.layout | 2 +-
src/mainboard/iwave/iWRainbowG6/cmos.layout | 2 +-
src/mainboard/iwill/dk8_htx/romstage.c | 2 +-
src/mainboard/iwill/dk8s2/romstage.c | 2 +-
src/mainboard/iwill/dk8x/romstage.c | 2 +-
src/mainboard/kontron/986lcd-m/cmos.layout | 2 +-
src/mainboard/lenovo/t60/cmos.layout | 2 +-
src/mainboard/lenovo/x60/cmos.layout | 2 +-
src/mainboard/nvidia/l1_2pvv/romstage.c | 2 +-
src/mainboard/roda/rk886ex/cmos.layout | 2 +-
src/mainboard/roda/rk886ex/m3885.c | 6 +++---
src/mainboard/roda/rk9/cmos.layout | 2 +-
src/mainboard/roda/rk9/mainboard.c | 2 +-
src/mainboard/samsung/lumpy/Makefile.inc | 2 +-
src/mainboard/supermicro/h8dme/romstage.c | 2 +-
src/mainboard/supermicro/h8dmr/romstage.c | 2 +-
src/mainboard/supermicro/h8qgi/romstage.c | 2 +-
src/mainboard/supermicro/h8scm/romstage.c | 2 +-
src/mainboard/tyan/s2912/romstage.c | 2 +-
src/mainboard/tyan/s8226/romstage.c | 2 +-
src/northbridge/amd/amdk8/raminit.c | 4 ++--
src/northbridge/amd/amdk8/raminit_f.c | 2 +-
src/northbridge/amd/gx1/northbridge.c | 2 +-
src/northbridge/amd/gx2/northbridgeinit.c | 2 +-
src/northbridge/amd/lx/northbridge.c | 2 +-
src/northbridge/amd/lx/northbridgeinit.c | 2 +-
src/northbridge/dmp/vortex86ex/northbridge.c | 2 +-
src/northbridge/intel/e7501/northbridge.c | 2 +-
src/northbridge/intel/e7505/northbridge.c | 2 +-
src/northbridge/intel/e7520/northbridge.c | 2 +-
src/northbridge/intel/e7520/raminit.c | 8 ++++----
src/northbridge/intel/e7525/northbridge.c | 2 +-
src/northbridge/intel/e7525/raminit.c | 6 +++---
src/northbridge/intel/haswell/Kconfig | 4 ++--
src/northbridge/intel/i3100/northbridge.c | 2 +-
src/northbridge/intel/i3100/raminit.c | 2 +-
src/northbridge/intel/i855/northbridge.c | 2 +-
src/northbridge/intel/i855/raminit.c | 2 +-
src/northbridge/intel/i945/raminit.c | 4 ++--
src/northbridge/via/cn400/raminit.c | 2 +-
src/northbridge/via/cx700/lpc.c | 2 +-
src/northbridge/via/vt8601/northbridge.c | 2 +-
src/northbridge/via/vt8623/northbridge.c | 2 +-
src/northbridge/via/vt8623/raminit.c | 2 +-
src/northbridge/via/vx800/examples/chipset_init.c | 2 +-
src/northbridge/via/vx800/examples/romstage.c | 2 +-
src/northbridge/via/vx800/lpc.c | 2 +-
src/northbridge/via/vx800/northbridge.c | 2 +-
src/northbridge/via/vx900/northbridge.c | 2 +-
src/soc/intel/baytrail/baytrail/iosf.h | 2 +-
src/soc/intel/baytrail/romstage/romstage.c | 4 ++--
src/soc/intel/fsp_baytrail/baytrail/iosf.h | 2 +-
src/southbridge/amd/agesa/hudson/lpc.c | 2 +-
src/southbridge/amd/cimx/sb700/bootblock.c | 4 ++--
src/southbridge/amd/cimx/sb800/Kconfig | 2 +-
src/southbridge/amd/cimx/sb800/bootblock.c | 4 ++--
src/southbridge/amd/cimx/sb900/bootblock.c | 4 ++--
src/southbridge/amd/cs5535/chipsetinit.c | 2 +-
src/southbridge/amd/cs5536/cs5536.c | 2 +-
src/southbridge/amd/sb800/lpc.c | 2 +-
src/southbridge/intel/esb6300/lpc.c | 2 +-
src/southbridge/intel/i82371eb/fadt.c | 2 +-
src/southbridge/via/vt8231/lpc.c | 2 +-
src/southbridge/via/vt8235/lpc.c | 2 +-
.../amd/agesa/f10/Legacy/Proc/hobTransfer.c | 2 +-
src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c | 2 +-
src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c | 2 +-
.../GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c | 2 +-
.../Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c | 4 ++--
src/vendorcode/amd/cimx/sb800/SBPOR.c | 4 ++--
util/cbmem/cbmem.c | 10 ++++-----
util/mkelfImage/linux-i386/uniform_boot.h | 2 +-
util/romcc/tests/raminit_test.c | 22 ++++++++++----------
util/romcc/tests/raminit_test1.c | 22 ++++++++++----------
util/romcc/tests/raminit_test2.c | 22 ++++++++++----------
util/romcc/tests/simple_test3.c | 2 +-
util/romcc/tests/simple_test4.c | 2 +-
util/romcc/tests/simple_test5.c | 4 ++--
util/romcc/tests/simple_test56.c | 4 ++--
util/romcc/tests/simple_test61.c | 2 +-
util/vgabios/testbios.c | 2 +-
183 files changed, 307 insertions(+), 307 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 42ed707..56cc869 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -44,7 +44,7 @@ MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR))
export MAINBOARDDIR
## Final build results, which CBFSTOOL uses to create the final
-## rom image file, are placed under $(objcbfs).
+## ROM image file, are placed under $(objcbfs).
## These typically have suffixes .debug .elf .bin and .map
export objcbfs := $(obj)/cbfs/$(call strip_quotes,$(CONFIG_CBFS_PREFIX))
@@ -437,7 +437,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
mv $@.tmp $@
###########################################################################
-# Build the final rom image
+# Build the final ROM image
###########################################################################
COREBOOT_ROM_DEPENDENCIES:=
diff --git a/documentation/CorebootBuildingGuide.tex b/documentation/CorebootBuildingGuide.tex
index 5847dab..0059202 100644
--- a/documentation/CorebootBuildingGuide.tex
+++ b/documentation/CorebootBuildingGuide.tex
@@ -66,7 +66,7 @@ find errors in the following descriptions, contact
\begin{itemize}
\item 2009/04/19 replace LinuxBIOS with coreboot
\item 2004/06/02 url and language fixes from Ken Fuchs $<$kfuchs at winternet.com$>$
- \item 2004/02/10 acpi and option rom updates
+ \item 2004/02/10 acpi and option ROM updates
\item 2003/11/18 initial release
\end{itemize}
@@ -353,7 +353,7 @@ available in firmware image specific configuration files:
\begin{itemize}
\item \begin{verbatim}romimage\end{verbatim}
-The \texttt{romimage} definition describes a single rom build within the
+The \texttt{romimage} definition describes a single ROM build within the
final coreboot image. Normally there are two romimage definitions per
coreboot build: \texttt{normal} and \texttt{fallback}.
@@ -1022,7 +1022,7 @@ reset logic:
\end{itemize}
Some mainboards utilize an SMBUS hub or possibly other mechanisms to
-allow using a large number of SPDROMs and thus ram sockets. The result
+allow using a large number of SPDROMs and thus RAM sockets. The result
is that only the SPDROM information of one cpu node is visible at a
time. The following function, defined in \texttt{auto.c}, is called every time
before a memory controller is initialized and gets the memory controller
@@ -1468,7 +1468,7 @@ CONs:
\subsection{Running X86 Option ROMs}
Especially SCSI/RAID controllers and graphics adapters come with a
-special option rom. This option rom usually contains x86 binary code
+special option rom. This option ROM usually contains x86 binary code
that uses a legacy PCBIOS interface for device interaction. If this code
gets executed, the device becomes operable in Linux and other operating
systems.
@@ -1533,7 +1533,7 @@ Set to \texttt{1} to use Cache As Ram (CAR). Defaults to \texttt{0}
Before going over the new image types, derived from v3, we will quickly review the standard v2 image types. We are hoping this review will
aid comprehension.
-A coreboot rom file consists of one or more \textit{images}. All images consist of a part that runs in ROM, and a part that runs in RAM. The RAM can be in compressed form and is decompressed when needed by the ROM code. The main function of the ROM code is to get memory working. Both ROM and RAM consist of a very small amount of assembly code and mostly C code.
+A coreboot ROM file consists of one or more \textit{images}. All images consist of a part that runs in ROM, and a part that runs in RAM. The RAM can be in compressed form and is decompressed when needed by the ROM code. The main function of the ROM code is to get memory working. Both ROM and RAM consist of a very small amount of assembly code and mostly C code.
\subsection{romcc images (from emulation/qemu)}
ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only
@@ -1541,7 +1541,7 @@ one file; to get more than one file, one must include the C code via include sta
\subsubsection{How it is built}
Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CONFIG\_CRT0\_INCLUDES variable. crt0.s is then assembled.
-File for the ram part are compiled in a conventional manner.
+File for the RAM part are compiled in a conventional manner.
The final step is linking. The use of named sections is used very heavily in coreboot to control where different bits of code go. The reset vector must go in the top 16 bytes. The start portion of the ROM code must go in the top 64K bytes, since most chipsets only enable this much ROM at startup time. Here is a quick look at a typical image:
\begin{verbatim}
@@ -1558,7 +1558,7 @@ The final step is linking. The use of named sections is used very heavily in cor
The only sections that get loaded into a ROM are the Allocated ones. We can see the .ram, .rom, .reset and .id sections.
\subsubsection{layout}
-As we mentioned, the ROM file consists of multiple images. In the basic file, there are two full coreboot rom images. The build sequence for each is the same, and in fact the ldscript.ld files are almost identical. The only difference is in a few makefile variables, generated by the config tool.
+As we mentioned, the ROM file consists of multiple images. In the basic file, there are two full coreboot ROM images. The build sequence for each is the same, and in fact the ldscript.ld files are almost identical. The only difference is in a few makefile variables, generated by the config tool.
\begin{itemize}
\item CONFIG\_PAYLOAD\_SIZE. Each image may have a different payload size.
@@ -1579,7 +1579,7 @@ Each image (normal or fallback) is built completely independently and does not g
\subsubsection{boot sequence}
We boot and start at fffffff0. We then jump to the entry point at \_start. \_start does some machine init and an lgdt and jumps to \_\_protected\_start, at which point we are in protected mode. The code does a bit more machine setup and then starts executing the romcc code.
-If fallback has been built in, some setup needs to be done. On some machines, it is extensive. Full rom decoding must be enabled. This may in turn require additional PCI setup to enable decoding to be enabled (!). To decided which image to use, hardware registers (cold boot on the Opteron) or CMOS are checked. Finally, once the image to use has been decided, a jmp is performed, viz:
+If fallback has been built in, some setup needs to be done. On some machines, it is extensive. Full ROM decoding must be enabled. This may in turn require additional PCI setup to enable decoding to be enabled (!). To decided which image to use, hardware registers (cold boot on the Opteron) or CMOS are checked. Finally, once the image to use has been decided, a jmp is performed, viz:
\begin{verbatim}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
diff --git a/documentation/Kconfig.tex b/documentation/Kconfig.tex
index 2b2bf7f..bac8f2b 100644
--- a/documentation/Kconfig.tex
+++ b/documentation/Kconfig.tex
@@ -13,7 +13,7 @@ Most Kconfig files set variables, which can be set as part of the Kconfig dialog
For variables set by the user, see src/console/Kconfig.
-For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent.
+For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as RAM base. These are highly mainboard dependent.
Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally.
@@ -28,8 +28,8 @@ We define the common rules for which variation to use below.
\subsection{object file specification}
There are several different types of objects specified in the tree. They are:
\begin{description}
-\item[obj]objects for the ram part of the code
-\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
+\item[obj]objects for the RAM part of the code
+\item[driver]drivers for the RAM part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
\item[initobj]seperately-compiled code for the ROM section of coreboot
\end{description}
These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax.
diff --git a/documentation/RFC/config.tex b/documentation/RFC/config.tex
index 6d6c433..99fc67e 100644
--- a/documentation/RFC/config.tex
+++ b/documentation/RFC/config.tex
@@ -172,7 +172,7 @@ A sample file:
\begin{verbatim}
target x
-# over-ride the default rom size in the mainboard file
+# over-ride the default ROM size in the mainboard file
option CONFIG_ROM_SIZE=1024*1024
mainboard amd/solo
end
diff --git a/payloads/libpayload/arch/x86/rom_media.c b/payloads/libpayload/arch/x86/rom_media.c
index e338d1c..cd84d67 100644
--- a/payloads/libpayload/arch/x86/rom_media.c
+++ b/payloads/libpayload/arch/x86/rom_media.c
@@ -94,7 +94,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) {
media->context = (void*)romsize;
#if defined(CONFIG_ROM_SIZE)
if (CONFIG_ROM_SIZE != romsize)
- printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
+ printk(BIOS_INFO, "Warning: ROM size unmatch (%d/%d)\n",
CONFIG_ROM_SIZE, romsize);
#endif
}
diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
index c143abb..34d74bc 100644
--- a/payloads/libpayload/libcbfs/cbfs.c
+++ b/payloads/libpayload/libcbfs/cbfs.c
@@ -109,8 +109,8 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
/* They might have specified a dest address. If so, we can decompress.
* If not, there's not much hope of decompressing or relocating the rom.
- * in the common case, the expansion rom is uncompressed, we
- * pass 0 in for the dest, and all we have to do is find the rom and
+ * in the common case, the expansion ROM is uncompressed, we
+ * pass 0 in for the dest, and all we have to do is find the ROM and
* return a pointer to it.
*/
diff --git a/src/arch/armv7/ramstage.ld b/src/arch/armv7/ramstage.ld
index 42090f4..debacbe 100644
--- a/src/arch/armv7/ramstage.ld
+++ b/src/arch/armv7/ramstage.ld
@@ -75,9 +75,9 @@ SECTIONS
_erodata = .;
}
/* After the code we place initialized data (typically initialized
- * global variables). This gets copied into ram by startup code.
- * __data_start and __data_end shows where in ram this should be placed,
- * whereas __data_loadstart and __data_loadend shows where in rom to
+ * global variables). This gets copied into RAM by startup code.
+ * __data_start and __data_end shows where in RAM this should be placed,
+ * whereas __data_loadstart and __data_loadend shows where in ROM to
* copy from.
*/
.data : {
@@ -114,7 +114,7 @@ SECTIONS
_stack = CONFIG_STACK_BOTTOM;
_estack = CONFIG_STACK_TOP;
- /* The ram segment. This includes all memory used by the memory
+ /* The RAM segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S
index 675a09c..1258c71 100644
--- a/src/arch/x86/lib/c_start.S
+++ b/src/arch/x86/lib/c_start.S
@@ -265,7 +265,7 @@ gdtaddr:
* which is defined in entry32.inc
*
* When the machine is initially started, we use a very simple
- * gdt from rom (that in entry32.inc) which only contains those
+ * gdt from ROM (that in entry32.inc) which only contains those
* entries we need for protected mode.
*
* When we're executing code from RAM, we want to do more complex
diff --git a/src/arch/x86/lib/rom_media.c b/src/arch/x86/lib/rom_media.c
index ed2122c..664a1f7 100644
--- a/src/arch/x86/lib/rom_media.c
+++ b/src/arch/x86/lib/rom_media.c
@@ -84,7 +84,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) {
media->context = (void*)romsize;
#if defined(CONFIG_ROM_SIZE)
if (CONFIG_ROM_SIZE != romsize)
- printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
+ printk(BIOS_INFO, "Warning: ROM size unmatch (%d/%d)\n",
CONFIG_ROM_SIZE, romsize);
#endif
}
diff --git a/src/arch/x86/lib/walkcbfs.S b/src/arch/x86/lib/walkcbfs.S
index 60eb8b5..545336e 100644
--- a/src/arch/x86/lib/walkcbfs.S
+++ b/src/arch/x86/lib/walkcbfs.S
@@ -28,7 +28,7 @@ walkcbfs_asm:
mov CBFS_HEADER_ROMSIZE(%eax), %ecx
bswap %ecx
mov $0, %ebx
- sub %ecx, %ebx /* rom base address in ebx */
+ sub %ecx, %ebx /* ROM base address in ebx */
mov CBFS_HEADER_OFFSET(%eax), %ecx
bswap %ecx
add %ecx, %ebx /* address where we start looking for LARCHIVEs */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 1c8e8dc..75fc778 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -74,9 +74,9 @@ SECTIONS
_erodata = .;
}
/* After the code we place initialized data (typically initialized
- * global variables). This gets copied into ram by startup code.
- * __data_start and __data_end shows where in ram this should be placed,
- * whereas __data_loadstart and __data_loadend shows where in rom to
+ * global variables). This gets copied into RAM by startup code.
+ * __data_start and __data_end shows where in RAM this should be placed,
+ * whereas __data_loadstart and __data_loadend shows where in ROM to
* copy from.
*/
.data : {
@@ -105,7 +105,7 @@ SECTIONS
}
_eheap = .;
- /* The ram segment. This includes all memory used by the memory
+ /* The RAM segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 0f936d0..c31025d 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -52,7 +52,7 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
ifeq ($(cbfs_include_ucode),y)
-# Add CPU microcode to specified rom image $(1)
+# Add CPU microcode to specified ROM image $(1)
add-cpu-microcode-to-cbfs = \
$(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset)
else
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
index 6fbfd1a..05ec628 100644
--- a/src/cpu/amd/agesa/family10/model_10_init.c
+++ b/src/cpu/amd/agesa/family10/model_10_init.c
@@ -60,7 +60,7 @@ static void model_10_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
/* Set the processor name string */
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 635bd81..3c2b7ce 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -66,7 +66,7 @@ static void model_12_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
/* Set the processor name string */
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 60a88c7..25fa701 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -86,7 +86,7 @@ static void model_14_init(device_t dev)
wrmsr(MCI_STATUS + (i * 4), msr);
}
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
index a755e1c..9f711c3 100644
--- a/src/cpu/amd/agesa/family15/model_15_init.c
+++ b/src/cpu/amd/agesa/family15/model_15_init.c
@@ -71,7 +71,7 @@ static void model_15_init(device_t dev)
wrmsr(MCI_STATUS + (i * 4), msr);
}
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 64c78af..7163aa8 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -85,7 +85,7 @@ static void model_15_init(device_t dev)
}
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index ef31f96..e5efbbd 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -83,7 +83,7 @@ static void model_16_init(device_t dev)
}
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 1899408..1912ee6 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -269,7 +269,7 @@ static void set_resume_cache(void)
msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
wrmsr(SYSCFG_MSR, msr);
- /* Enable caching for 0 - coreboot ram using variable mtrr */
+ /* Enable caching for 0 - coreboot RAM using variable mtrr */
msr.lo = 0 | MTRR_TYPE_WRBACK;
msr.hi = 0;
wrmsr(MTRRphysBase_MSR(0), msr);
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 3a0763a..9b9c4ad 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -92,7 +92,7 @@ void post_cache_as_ram(void)
}
#endif
- /* copy data from cache as ram to
+ /* copy data from cache as RAM to
ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
*/
#if CONFIG_RAMTOP <= 0x100000
@@ -120,7 +120,7 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused)))
/* only global variable sysinfo in cache need to be offset */
print_debug("Done\n");
- print_debug("Disabling cache as ram now \n");
+ print_debug("Disabling cache as RAM now \n");
disable_cache_as_ram_bsp();
diff --git a/src/cpu/amd/geode_gx1/geode_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c
index 8fbf507..9c211c9 100644
--- a/src/cpu/amd/geode_gx1/geode_gx1_init.c
+++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c
@@ -81,7 +81,7 @@ static void geode_gx1_init(device_t dev)
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index 45a04f8..b6b1d54 100644
--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
@@ -175,7 +175,7 @@ done_cache_as_ram_main:
pop %esi
pop %edi
- /* Clear the cache out to ram */
+ /* Clear the cache out to RAM */
wbinvd
/* re-enable the cache */
movl %cr0, %eax
diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c
index b8f56db..b6bad4d 100644
--- a/src/cpu/amd/geode_gx2/geode_gx2_init.c
+++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c
@@ -22,7 +22,7 @@ static void geode_gx2_init(device_t dev)
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
//setup_lapic();
vsm_end_post_smi();
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index 45fd166..15cd758 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -201,7 +201,7 @@ done_cache_as_ram_main:
pop %esi
pop %edi
- /* Clear the cache out to ram */
+ /* Clear the cache out to RAM */
wbinvd
/* re-enable the cache */
movl %cr0, %eax
diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c
index ebadec7..c3d2572 100644
--- a/src/cpu/amd/geode_lx/cpubug.c
+++ b/src/cpu/amd/geode_lx/cpubug.c
@@ -81,7 +81,7 @@ static void disablememoryreadorder(void)
wrmsr(MC_CF8F_DATA, msr);
}
-/* For cpu version C3. Should be the only released version */
+/* For CPU version C3. Should be the only released version */
void cpubug(void)
{
pcideadlock();
diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c
index cd931a4..cdd72b5 100644
--- a/src/cpu/amd/geode_lx/geode_lx_init.c
+++ b/src/cpu/amd/geode_lx/geode_lx_init.c
@@ -44,7 +44,7 @@ static void geode_lx_init(device_t dev)
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
//setup_lapic();
// do VSA late init
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 10c0c8a..eb188a9 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -179,7 +179,7 @@ static u32 wait_cpu_state(u32 apicid, u32 state)
continue;
if ((readback & 0x3f) == state || (readback & 0x3f) == F10_APSTATE_RESET) {
timeout = 0;
- break; //target cpu is in stage started
+ break; //target CPU is in stage started
}
}
if (timeout) {
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index c6cf64a..10d3b53 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -66,7 +66,7 @@ static void model_10xxx_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
/* Set the processor name string */
diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c
index e68611b..464e5b3 100644
--- a/src/cpu/amd/model_fxx/fidvid.c
+++ b/src/cpu/amd/model_fxx/fidvid.c
@@ -402,7 +402,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
0)
continue;
if (((readback >> 24) & 0xff) == apicid)
- break; /* it is this cpu turn */
+ break; /* it is this CPU turn */
}
if (loop > 0) {
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 12d3a95..f846421 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -144,7 +144,7 @@ static u32 wait_cpu_state(u32 apicid, u32 state)
continue;
if ((readback & 0xff) == state) {
timeout = 0;
- break; //target cpu is in stage started
+ break; //target CPU is in stage started
}
}
if (timeout) {
@@ -271,7 +271,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set
}
//here don't need to wait
- lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the cpu is started
+ lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the CPU is started
if (apicid != bsp_apicid) {
u32 timeout = 1;
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 260e83e..55547b8 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -234,15 +234,15 @@ static void init_ecc_memory(unsigned node_id)
f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1));
if (!f1_dev) {
- die("Cannot find cpu function 1\n");
+ die("Cannot find CPU function 1\n");
}
f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2));
if (!f2_dev) {
- die("Cannot find cpu function 2\n");
+ die("Cannot find CPU function 2\n");
}
f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3));
if (!f3_dev) {
- die("Cannot find cpu function 3\n");
+ die("Cannot find CPU function 3\n");
}
/* See if we scrubbing should be enabled */
@@ -486,7 +486,7 @@ static void model_fxx_init(device_t dev)
/* Set the processor name string */
init_processor_name();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index f3f7071..3c2beb2 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -357,7 +357,7 @@ int sizemem(void)
}
#if 0
/* enable last bank and setup ending address
- * register for max ram in last bank
+ * register for max RAM in last bank
*/
*drcbendadr=0x0ff000000;
@@ -583,7 +583,7 @@ bad_reinit:
bad_ram:
print_info("bad ram!\n");
/* you are here because the read-after-write failed,
- * in most cases because: no ram in that bank!
+ * in most cases because: no RAM in that bank!
* set badbank to 1 and go to reinit
*/
ending_adr = 0;
diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index 808c33c..fbaf466 100644
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -111,7 +111,7 @@ static void pci_domain_set_resources(device_t dev)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
- printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+ printk(BIOS_DEBUG, "I would set RAM size to 0x%x Kbytes\n", (rambits)*8*1024);
tomk = rambits*8*1024;
#endif
tomk = 32 * 1024;
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc
index 4a2478e..86ef03a 100644
--- a/src/cpu/dmp/vortex86ex/biosdata_ex.inc
+++ b/src/cpu/dmp/vortex86ex/biosdata_ex.inc
@@ -28,8 +28,8 @@ DDR3
CPU/DRAM/PCI B6 B7 BB BC BD BF
200/200/33 30 03 0F 02 8F 07
300/300/33 48 03 0F 02 1F 07
-300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable
-300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable
+300/300/33 48 03 0F 3A DF 07 ; write leveling disable, CPU bypass disable
+300/300/33 48 03 0F 22 3F 07 ; CPU bypass disable
300/300/100 48 03 23 02 7F 07
400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing
400/200/100 60 43 23 02 4F 07
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 0392f69..8464876 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -1,5 +1,5 @@
# Note: From here on down, we are socket-centric. Socket choice determines
-# what other cpu files are included.
+# what other CPU files are included.
#
# Therefore: ONLY include Makefile.inc from socket directories!
diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c
index 433636d..0819132 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -38,7 +38,7 @@ static void ep80579_init(device_t dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
index d0b2d3d..157d564 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
@@ -315,7 +315,7 @@ static void intel_cores_init(device_t cpu)
struct device_path cpu_path;
device_t new;
- /* Build the cpu device path */
+ /* Build the CPU device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id =
cpu->path.apic.apic_id + i;
@@ -324,7 +324,7 @@ static void intel_cores_init(device_t cpu)
if (threads_per_core == 1)
cpu_path.apic.apic_id <<= 1;
- /* Allocate the new cpu device structure */
+ /* Allocate the new CPU device structure */
new = alloc_dev(cpu->bus, &cpu_path);
if (!new)
continue;
@@ -334,7 +334,7 @@ static void intel_cores_init(device_t cpu)
new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
- /* Start the new cpu */
+ /* Start the new CPU */
if (!start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
@@ -368,7 +368,7 @@ static void model_206ax_init(device_t cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 36d5654..c9ea10c 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -153,7 +153,7 @@ clear_mtrrs:
post_code(0x27)
#if CONFIG_CACHE_MRC_BIN
- /* Enable caching for ram init code to run faster */
+ /* Enable caching for RAM init code to run faster */
movl $MTRRphysBase_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 043ba3a..3ee72e1 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -740,7 +740,7 @@ static void haswell_init(device_t cpu)
/* Clear out pending MCEs */
configure_mca();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 9e27668..2c97e46 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -139,7 +139,7 @@ static void *setup_romstage_stack_after_car(void)
top_of_ram = get_top_of_ram();
/* Cache 8MiB below the top of ram. On haswell systems the top of
- * ram under 4GiB is the start of the TSEG region. It is required to
+ * RAM under 4GiB is the start of the TSEG region. It is required to
* be 8MiB aligned. Set this area as cacheable so it can be used later
* for ramstage before setting up the entire RAM as cacheable. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
@@ -148,7 +148,7 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
num_mtrrs++;
- /* Cache 8MiB at the top of ram. Top of ram on haswell systems
+ /* Cache 8MiB at the top of ram. Top of RAM on haswell systems
* is where the TSEG region resides. However, it is not restricted
* to SMM mode until SMM has been relocated. By setting the region
* to cacheable it provides faster access when relocating the SMM
@@ -320,7 +320,7 @@ void romstage_after_car(void)
struct ramstage_cache *ramstage_cache_location(long *size)
{
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
- * The top of ram is defined to be the TSEG base address. */
+ * The top of RAM is defined to be the TSEG base address. */
*size = RESERVED_SMM_SIZE;
return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET);
}
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 56d435c..606ac51 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -184,7 +184,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
return;
}
- printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+ printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
/* Determine if the processor supports saving state in MSRs. If so,
* enable it before the non-BSPs run so that SMM relocation can occur
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index 16d8959..5f205d0 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -8,7 +8,7 @@
#include <assert.h>
#if CONFIG_PARALLEL_CPU_INIT
-#error Intel hyper-threading requires serialized cpu init
+#error Intel hyper-threading requires serialized CPU init
#endif
static int first_time = 1;
@@ -63,7 +63,7 @@ void intel_sibling_init(device_t cpu)
cpu->path.apic.apic_id,
siblings);
- /* See if I am a sibling cpu */
+ /* See if I am a sibling CPU */
if (cpu->path.apic.apic_id & (siblings -1)) {
if (disable_siblings) {
cpu->enabled = 0;
@@ -71,16 +71,16 @@ void intel_sibling_init(device_t cpu)
return;
}
- /* I am the primary cpu start up my siblings */
+ /* I am the primary CPU start up my siblings */
for(i = 1; i < siblings; i++) {
struct device_path cpu_path;
device_t new;
- /* Build the cpu device path */
+ /* Build the CPU device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = cpu->path.apic.apic_id + i;
- /* Allocate new cpu device structure iff sibling CPU
+ /* Allocate new CPU device structure iff sibling CPU
* was not in static device tree.
*/
new = alloc_find_dev(cpu->bus, &cpu_path);
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index 1feb504..1cab11b 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1,5 +1,5 @@
################################################################################
-## One small file with the awesome super-power of updating the cpu microcode
+## One small file with the awesome super-power of updating the CPU microcode
## directly from CBFS. You have been WARNED!!!
################################################################################
ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 4779a51..e2fa564 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -326,7 +326,7 @@ static void model_1067x_init(device_t cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
/* Initialize the APIC timer */
@@ -351,7 +351,7 @@ static void model_1067x_init(device_t cpu)
/* PIC thermal sensor control */
configure_pic_thermal_sensors(tm2, quad);
- /* Start up my cpu siblings */
+ /* Start up my CPU siblings */
intel_sibling_init(cpu);
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 73ee5cd..4e89734 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -128,7 +128,7 @@ static void model_106cx_init(device_t cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
/* Enable virtualization */
@@ -142,7 +142,7 @@ static void model_106cx_init(device_t cpu)
/* TODO: PIC thermal sensor control */
- /* Start up my cpu siblings */
+ /* Start up my CPU siblings */
intel_sibling_init(cpu);
}
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index c310a67..3501d4d 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -368,13 +368,13 @@ static void intel_cores_init(device_t cpu)
struct device_path cpu_path;
device_t new;
- /* Build the cpu device path */
+ /* Build the CPU device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id =
cpu->path.apic.apic_id + (i % threads_per_core)
+ ((i / threads_per_core) << 2);
- /* Allocate the new cpu device structure */
+ /* Allocate the new CPU device structure */
new = alloc_dev(cpu->bus, &cpu_path);
if (!new)
continue;
@@ -384,7 +384,7 @@ static void intel_cores_init(device_t cpu)
new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
- /* Start the new cpu */
+ /* Start the new CPU */
if (!start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
@@ -421,7 +421,7 @@ static void model_2065x_init(device_t cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 1a19707..4036b0b 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -148,7 +148,7 @@ clear_mtrrs:
post_code(0x27)
#if CONFIG_CACHE_MRC_BIN
- /* Enable caching for ram init code to run faster */
+ /* Enable caching for RAM init code to run faster */
movl $MTRRphysBase_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 4e56414..b8aec4b 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -502,7 +502,7 @@ static void intel_cores_init(device_t cpu)
struct device_path cpu_path;
device_t new;
- /* Build the cpu device path */
+ /* Build the CPU device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id =
cpu->path.apic.apic_id + i;
@@ -511,7 +511,7 @@ static void intel_cores_init(device_t cpu)
if (threads_per_core == 1)
cpu_path.apic.apic_id <<= 1;
- /* Allocate the new cpu device structure */
+ /* Allocate the new CPU device structure */
new = alloc_dev(cpu->bus, &cpu_path);
if (!new)
continue;
@@ -521,7 +521,7 @@ static void intel_cores_init(device_t cpu)
new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
- /* Start the new cpu */
+ /* Start the new CPU */
if (!start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
@@ -557,7 +557,7 @@ static void model_206ax_init(device_t cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c
index a9f1811..3af0e9c 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -40,7 +40,7 @@ static void model_65x_init(device_t dev)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
index 467d3db..df3be0b 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -44,7 +44,7 @@ static void model_67x_init(device_t cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
}
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c
index d1b4463..adf808e 100644
--- a/src/cpu/intel/model_68x/model_68x_init.c
+++ b/src/cpu/intel/model_68x/model_68x_init.c
@@ -49,7 +49,7 @@ static void model_68x_init(device_t cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
}
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index 4339274..8e0c034 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -18,7 +18,7 @@ static void model_69x_init(device_t dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
index d166bfa..650da15 100644
--- a/src/cpu/intel/model_6bx/model_6bx_init.c
+++ b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -49,7 +49,7 @@ static void model_6bx_init(device_t cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
}
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 18c2fa4..f9ae4fc 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -18,7 +18,7 @@ static void model_6dx_init(device_t dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 8f9fbf8..4e7b6e2 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -159,7 +159,7 @@ static void model_6ex_init(device_t cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
/* Enable virtualization */
@@ -174,7 +174,7 @@ static void model_6ex_init(device_t cpu)
/* PIC thermal sensor control */
configure_pic_thermal_sensors();
- /* Start up my cpu siblings */
+ /* Start up my CPU siblings */
intel_sibling_init(cpu);
}
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 93635d4..4107898 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -182,7 +182,7 @@ static void model_6fx_init(device_t cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
/* Enable virtualization */
@@ -197,7 +197,7 @@ static void model_6fx_init(device_t cpu)
/* PIC thermal sensor control */
configure_pic_thermal_sensors();
- /* Start up my cpu siblings */
+ /* Start up my CPU siblings */
intel_sibling_init(cpu);
}
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 9b92dcc..74d053e 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -18,7 +18,7 @@ static void model_6xx_init(device_t dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index ca40515..e29b1e3 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -18,7 +18,7 @@ static void model_f0x_init(device_t dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index dbb5cd0..2cae97a 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -18,7 +18,7 @@ static void model_f1x_init(device_t dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index 53eb75e..55d631b 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -23,10 +23,10 @@ static void model_f2x_init(device_t cpu)
intel_update_microcode_from_cbfs();
}
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
- /* Start up my cpu siblings */
+ /* Start up my CPU siblings */
intel_sibling_init(cpu);
};
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index f8d9ca6..f566c33 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -23,10 +23,10 @@ static void model_f3x_init(device_t cpu)
intel_update_microcode_from_cbfs();
}
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
- /* Start up my cpu siblings */
+ /* Start up my CPU siblings */
intel_sibling_init(cpu);
};
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index 260b60a..b1a1e4f 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -23,10 +23,10 @@ static void model_f4x_init(device_t cpu)
intel_update_microcode_from_cbfs();
}
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
- /* Start up my cpu siblings */
+ /* Start up my CPU siblings */
intel_sibling_init(cpu);
};
diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c
index 7d94384..eb1de4b 100644
--- a/src/cpu/via/c3/c3_init.c
+++ b/src/cpu/via/c3/c3_init.c
@@ -32,7 +32,7 @@ static void c3_init(device_t dev)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c
index 510e66d..e09112c 100644
--- a/src/cpu/via/c7/c7_init.c
+++ b/src/cpu/via/c7/c7_init.c
@@ -205,7 +205,7 @@ static void c7_init(device_t dev)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
};
@@ -214,7 +214,7 @@ static struct device_operations cpu_dev_ops = {
};
/* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact
- * ID, the cpu mask (stepping) is masked out and the check is repeated. This
+ * ID, the CPU mask (stepping) is masked out and the check is repeated. This
* allows us to keep the table significantly smaller.
*/
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
index 417119f..7298386 100644
--- a/src/cpu/via/nano/nano_init.c
+++ b/src/cpu/via/nano/nano_init.c
@@ -183,7 +183,7 @@ static void nano_init(device_t dev)
/* Set up Memory Type Range Registers */
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
}
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index c82edfd..0d6c730 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -53,7 +53,7 @@ _start:
* If we are hyperthreaded or we have multiple cores it is bad,
* for SMP startup. On Opterons it causes a 5 second delay.
* Invalidating the cache was pure paranoia in any event.
- * If you cpu needs it you can write a cpu dependent version of
+ * If you CPU needs it you can write a CPU dependent version of
* entry16.inc.
*/
@@ -94,7 +94,7 @@ _start:
*
* Also load an IDT with NULL limit to prevent the 16bit IDT being used
* in protected mode before c_start.S sets up a 32bit IDT when entering
- * ram stage. In practise: CPU will shutdown on any exception.
+ * RAM stage. In practise: CPU will shutdown on any exception.
* See IA32 manual Vol 3A 19.26 Interrupts.
*/
diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds
index a31a580..362f43b 100644
--- a/src/cpu/x86/16bit/reset16.lds
+++ b/src/cpu/x86/16bit/reset16.lds
@@ -1,5 +1,5 @@
/*
- * _ROMTOP : The top of the rom used where we
+ * _ROMTOP : The top of the ROM used where we
* need to put the reset vector.
*/
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 09b6b9e..43bb4d4 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -91,7 +91,7 @@ static void copy_secondary_start_to_lowest_1M(void)
memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
#endif
- /* copy the _secondary_start to the ram below 1M*/
+ /* copy the _secondary_start to the RAM below 1M*/
memcpy((unsigned char *)AP_SIPI_VECTOR, (unsigned char *)_secondary_start, code_size);
printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n",
@@ -239,10 +239,10 @@ static int lapic_start_cpu(unsigned long apicid)
static atomic_t active_cpus = ATOMIC_INIT(1);
/* start_cpu_lock covers last_cpu_index and secondary_stack.
- * Only starting one cpu at a time let's me remove the logic
+ * Only starting one CPU at a time let's me remove the logic
* for select the stack from assembly language.
*
- * In addition communicating by variables to the cpu I
+ * In addition communicating by variables to the CPU I
* am starting allows me to verify it has started before
* start_cpu returns.
*/
@@ -298,12 +298,12 @@ int start_cpu(device_t cpu)
cpu->enabled = 0;
cpu->initialized = 0;
- /* Start the cpu */
+ /* Start the CPU */
result = lapic_start_cpu(apicid);
if (result) {
result = 0;
- /* Wait 1s or until the new cpu calls in */
+ /* Wait 1s or until the new CPU calls in */
for(count = 0; count < 100000 ; count++) {
if (secondary_stack == 0) {
result = 1;
@@ -507,23 +507,23 @@ void initialize_cpus(struct bus *cpu_bus)
struct device_path cpu_path;
struct cpu_info *info;
- /* Find the info struct for this cpu */
+ /* Find the info struct for this CPU */
info = cpu_info();
#if NEED_LAPIC == 1
/* Ensure the local apic is enabled */
enable_lapic();
- /* Get the device path of the boot cpu */
- cpu_path.type = DEVICE_PATH_APIC;
+ /* Get the device path of the boot CPU */
+ cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = lapicid();
#else
- /* Get the device path of the boot cpu */
- cpu_path.type = DEVICE_PATH_CPU;
- cpu_path.cpu.id = 0;
+ /* Get the device path of the boot CPU */
+ cpu_path.type = DEVICE_PATH_CPU;
+ cpu_path.cpu.id = 0;
#endif
- /* Find the device structure for the boot cpu */
+ /* Find the device structure for the boot CPU */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index e83c23d..5ed21d0 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -331,7 +331,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p)
device_t new;
int apic_id;
- /* Build the cpu device path */
+ /* Build the CPU device path */
cpu_path.type = DEVICE_PATH_APIC;
/* Assuming linear APIC space allocation. */
@@ -341,10 +341,10 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p)
}
cpu_path.apic.apic_id = apic_id;
- /* Allocate the new cpu device structure */
+ /* Allocate the new CPU device structure */
new = alloc_find_dev(cpu_bus, &cpu_path);
if (new == NULL) {
- printk(BIOS_CRIT, "Could not allocte cpu device\n");
+ printk(BIOS_CRIT, "Could not allocte CPU device\n");
max_cpus--;
}
cpus[i].dev = new;
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 0471a9e..15a6b6e 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -22,7 +22,7 @@ void set_var_mtrr(
#if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM
static void cache_ramstage(void)
{
- /* Enable caching for lower 1MB and ram stage using variable mtrr */
+ /* Enable caching for lower 1MB and RAM stage using variable mtrr */
disable_cache();
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index c08c391..fcb92f4 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -100,7 +100,7 @@ ap_start:
mov idt_ptr, %ebx
lidt (%ebx)
- /* Obtain cpu number. */
+ /* Obtain CPU number. */
movl ap_count, %eax
1:
movl %eax, %ecx
@@ -114,7 +114,7 @@ ap_start:
movl stack_top, %edx
subl %eax, %edx
mov %edx, %esp
- /* Save cpu number. */
+ /* Save CPU number. */
mov %ecx, %esi
/* Determine if one should check microcode versions. */
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index 478ae8c..171836e 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -52,7 +52,7 @@ extern unsigned char _binary_smmstub_start[];
/* This is the SMM handler that the stub calls. It is encoded as an rmodule. */
extern unsigned char _binary_smm_start[];
-/* Per cpu minimum stack size. */
+/* Per CPU minimum stack size. */
#define SMM_MINIMUM_STACK_SIZE 32
/*
@@ -79,7 +79,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num,
struct smm_entry_ins entry = { .jmp_rel = 0xe9 };
/* Each entry point has an IP value of 0x8000. The SMBASE for each
- * cpu is different so the effective address of the entry instruction
+ * CPU is different so the effective address of the entry instruction
* is different. Therefore, the relative displacement for each entry
* instruction needs to be updated to reflect the current effective
* IP. Additionally, the IP result from the jmp instruction is
@@ -130,7 +130,7 @@ static void *smm_stub_place_stacks(char *base, int size,
}
/* Place the staggered entry points for each CPU. The entry points are
- * staggered by the per cpu SMM save state size extending down from
+ * staggered by the per CPU SMM save state size extending down from
* SMM_ENTRY_OFFSET. */
static void smm_stub_place_staggered_entry_points(char *base,
const struct smm_loader_params *params, const struct rmodule *smm_stub)
@@ -264,7 +264,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params)
stub_params->runtime.smbase = (u32)smbase;
stub_params->runtime.save_state_size = params->per_cpu_save_state_size;
- /* Initialize the APIC id to cpu number table to be 1:1 */
+ /* Initialize the APIC id to CPU number table to be 1:1 */
for (i = 0; i < params->num_concurrent_stacks; i++)
stub_params->runtime.apic_id_to_cpu[i] = i;
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 083cb57..73e2da4 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -45,15 +45,15 @@ smbase:
.long 0
save_state_size:
.long 0
-/* apic_to_cpu_num is a table mapping the default APIC id to cpu num. If the
- * APIC id is found at the given index, the contiguous cpu number is index
+/* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the
+ * APIC id is found at the given index, the contiguous CPU number is index
* into the table. */
apic_to_cpu_num:
.fill CONFIG_MAX_CPUS,1,0xff
/* end struct smm_runtime */
.data
-/* Provide fallback stack to use when a valid cpu number cannot be found. */
+/* Provide fallback stack to use when a valid CPU number cannot be found. */
fallback_stack_bottom:
.skip 128
fallback_stack_top:
@@ -119,7 +119,7 @@ smm_trampoline32:
inc %ecx
cmp $CONFIG_MAX_CPUS, %ecx
jne 1b
- /* This is bad. One cannot find a stack entry because a cpu num could
+ /* This is bad. One cannot find a stack entry because a CPU num could
* not be assigned. Use the fallback stack and check this condition in
* C handler. */
movl $(fallback_stack_top), %esp
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index bdc9771..309c1cb 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -118,7 +118,7 @@
* 0xa0000-0xa0400 and the stub plus stack would need to go
* at 0xa8000-0xa8100 (example for core 0). That is not enough.
*
- * This means we're basically limited to 16 cpu cores before
+ * This means we're basically limited to 16 CPU cores before
* we need to move the SMM handler to TSEG.
*
* Note: Some versions of Pentium M need their SMBASE aligned to 32k.
@@ -239,7 +239,7 @@ skip_smrr:
outb %al, %dx
movb $'-', %al
outb %al, %dx
- /* calculate ascii of cpu number. More than 9 cores? -> FIXME */
+ /* calculate ascii of CPU number. More than 9 cores? -> FIXME */
movb %cl, %al
addb $'0', %al
outb %al, %dx
diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c
index e76b539..d128f36 100644
--- a/src/device/cpu_device.c
+++ b/src/device/cpu_device.c
@@ -42,7 +42,7 @@ device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled)
struct device_path cpu_path;
device_t cpu;
- /* Build the cpu device path */
+ /* Build the CPU device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = apic_id;
diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S
index 54cf374..e63dc55 100644
--- a/src/device/oprom/realmode/x86_asm.S
+++ b/src/device/oprom/realmode/x86_asm.S
@@ -147,7 +147,7 @@ __realmode_call:
mov %ax, %ds
lidt __realmode_idt
- /* initialize registers for option rom lcall */
+ /* initialize registers for option ROM lcall */
movl __registers + 0, %eax
movl __registers + 4, %ebx
movl __registers + 8, %ecx
diff --git a/src/device/oprom/yabel/debug.h b/src/device/oprom/yabel/debug.h
index 2e714a3..80ad03e 100644
--- a/src/device/oprom/yabel/debug.h
+++ b/src/device/oprom/yabel/debug.h
@@ -50,7 +50,7 @@ static inline void set_ci(void) {};
* ||||||||||-DEBUG_PRINT_INT10 - let INT10 (i.e. character output) calls print messages to Debug output
* |||||||||||-DEBUG_INTR - Print messages related to interrupt handling
* ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to accesse to certain areas of the virtual Memory (e.g. BDA (BIOS Data Area) or Interrupt Vectors)
- * |||||||||||||-DEBUG_MEM - Print memory access made by option rom (NOTE: this also includes accesses to fetch instructions)
+ * |||||||||||||-DEBUG_MEM - Print memory access made by option ROM (NOTE: this also includes accesses to fetch instructions)
* ||||||||||||||-DEBUG_IO - Print I/O access made by option rom
* 11000111111111 - Max Binary Value, Debug All (WARNING: - This could run for hours)
*/
diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c
index 9d64041..15c01d8 100644
--- a/src/drivers/pc80/vga/vga.c
+++ b/src/drivers/pc80/vga/vga.c
@@ -57,7 +57,7 @@ vga_fb_init(void)
vga_gr_write(0x07, 0x00);
vga_gr_write(0x08, 0xFF);
- /* o/e enable: ram enable */
+ /* o/e enable: RAM enable */
vga_misc_mask(0x22, 0x22);
}
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 0310db3..f26ef6e 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -83,14 +83,14 @@
#define POST_ENTRY_C_START 0x13
/**
- * \brief Pre call to ram stage main()
+ * \brief Pre call to RAM stage main()
*
- * POSTed right before ram stage main() is called from c_start.S
+ * POSTed right before RAM stage main() is called from c_start.S
*/
#define POST_PRE_HARDWAREMAIN 0x79
/**
- * \brief Entry into coreboot in ram stage main()
+ * \brief Entry into coreboot in RAM stage main()
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index a4d976f..84d4bfe 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -56,7 +56,7 @@ static inline void invd(void)
/* The following functions require the always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
- * ram, the cache as ram stack can no longer be used. Called
+ * ram, the cache as RAM stack can no longer be used. Called
* functions must be inlined to avoid stack usage. Also, the
* compiler must keep local variables register based and not
* allocated them from the stack. With gcc 4.5.0, some functions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 40926df..37c3b75 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -31,7 +31,7 @@ typedef struct msrinit_struct
/* The following functions require the always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
- * ram, the cache as ram stack can no longer be used. Called
+ * ram, the cache as RAM stack can no longer be used. Called
* functions must be inlined to avoid stack usage. Also, the
* compiler must keep local variables register based and not
* allocated them from the stack. With gcc 4.5.0, some functions
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index d229cf8..d1d2be0 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -44,7 +44,7 @@ int rmodule_load_alignment(const struct rmodule *m);
/* rmodule_calc_region() calculates the region size, offset to place an
* rmodule in memory, and load address offset based off of a region allocator
* with an alignment of region_alignment. This function helps place an rmodule
- * in the same location in ram it will run from. The offset to place the
+ * in the same location in RAM it will run from. The offset to place the
* rmodule into the region allocated of size region_size is returned. The
* load_offset is the address to load and relocate the rmodule.
* region_alignment must be a power of 2. */
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index dc08937..df2942a 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -97,8 +97,8 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
/* They might have specified a dest address. If so, we can decompress.
* If not, there's not much hope of decompressing or relocating the rom.
- * in the common case, the expansion rom is uncompressed, we
- * pass 0 in for the dest, and all we have to do is find the rom and
+ * in the common case, the expansion ROM is uncompressed, we
+ * pass 0 in for the dest, and all we have to do is find the ROM and
* return a pointer to it.
*/
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index 9d5419a..5b37652 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -40,7 +40,7 @@ static struct cbmem_console *cbmem_console_p CAR_GLOBAL;
#ifdef __PRE_RAM__
/*
* While running from ROM, before DRAM is initialized, some area in cache as
- * ram space is used for the console buffer storage. The size and location of
+ * RAM space is used for the console buffer storage. The size and location of
* the area are defined in the config.
*/
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index 8e9e0de..e3833ea 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -226,7 +226,7 @@ static int build_self_segment_list(
first_segment = segment = &cbfs_payload->segments;
while(1) {
- printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment);
+ printk(BIOS_DEBUG, "Loading segment from ROM address 0x%p\n", segment);
switch(segment->type) {
case PAYLOAD_SEGMENT_PARAMS:
printk(BIOS_DEBUG, " parameter section (skipped)\n");
diff --git a/src/lib/thread.c b/src/lib/thread.c
index 6508bfa..b8e1c91 100644
--- a/src/lib/thread.c
+++ b/src/lib/thread.c
@@ -48,7 +48,7 @@ static inline int thread_can_yield(const struct thread *t)
return (t != NULL && t->can_yield);
}
-/* Assumes current cpu info can switch. */
+/* Assumes current CPU info can switch. */
static inline struct thread *cpu_info_to_thread(const struct cpu_info *ci)
{
return ci->thread;
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 842b4f0..f517ad9 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43);
- print_debug("Disabling cache as ram ");
+ print_debug("Disabling cache as RAM ");
disable_cache_as_ram();
print_debug("done\n");
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index ec0682a..2ab2484 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -211,5 +211,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 30ba468..d62c07c 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -175,7 +175,7 @@ static void m2v_it8712f_gpio_init(void)
printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
/*
- * upper two bits of gpio_base+4 control ddr2 voltage:
+ * upper two bits of gpio_base+4 control DDR2 voltage:
* 11: 1.80V
* 01: 1.85V
* 10: 1.90V
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 0f8c0c2..c7ddfab 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -71,7 +71,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
fw_cfg_load_file("etc/e820", list);
for (i = 0; i < size/sizeof(*list); i++) {
switch (list[i].type) {
- case 1: /* ram */
+ case 1: /* RAM */
printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n",
list[i].address, list[i].length);
if (list[i].address == 0) {
diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout
index a48bbee..a38b85b 100644
--- a/src/mainboard/getac/p470/cmos.layout
+++ b/src/mainboard/getac/p470/cmos.layout
@@ -100,7 +100,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 10bbb6f..702e9a0 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -197,5 +197,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
sis_init_stage2();
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index b2e1d70..c12ca99 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -204,5 +204,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc
index d18c372..2f6caa1 100755
--- a/src/mainboard/gizmosphere/gizmo/Makefile.inc
+++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc
@@ -43,7 +43,7 @@ SPD_SOURCES = Elpida_EDJ2116DEBG
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/bolt/Makefile.inc b/src/mainboard/google/bolt/Makefile.inc
index e30d0ae..22f0be8 100644
--- a/src/mainboard/google/bolt/Makefile.inc
+++ b/src/mainboard/google/bolt/Makefile.inc
@@ -32,7 +32,7 @@ SPD_SOURCES = micron_4Gb_1600_1.35v_x16
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc
index b9a1e04..b107ec4 100644
--- a/src/mainboard/google/falco/Makefile.inc
+++ b/src/mainboard/google/falco/Makefile.inc
@@ -37,7 +37,7 @@ SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc
index b8899e3..7dabe1d 100644
--- a/src/mainboard/google/link/Makefile.inc
+++ b/src/mainboard/google/link/Makefile.inc
@@ -35,7 +35,7 @@ SPD_SOURCES += micron_4Gb_1600_1.35v_x16
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $^; do for c in $$(cat $$f); do echo -e -n "\\x$$c"; done; done > $@
diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc
index 21c4c96..b91aae9 100644
--- a/src/mainboard/google/peppy/Makefile.inc
+++ b/src/mainboard/google/peppy/Makefile.inc
@@ -38,7 +38,7 @@ SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc
index fb0335f..29e9a9a 100644
--- a/src/mainboard/google/rambi/spd/Makefile.inc
+++ b/src/mainboard/google/rambi/spd/Makefile.inc
@@ -36,7 +36,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc
index 9e3c310..b9159eb 100644
--- a/src/mainboard/google/slippy/Makefile.inc
+++ b/src/mainboard/google/slippy/Makefile.inc
@@ -34,7 +34,7 @@ SPD_SOURCES += Hynix_HMT425S6AFR6A
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl
index 05fa6de..598381f 100644
--- a/src/mainboard/hp/dl145_g1/dsdt.asl
+++ b/src/mainboard/hp/dl145_g1/dsdt.asl
@@ -176,7 +176,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
Notify (\_SB.PWRB, 0x02)
}
}
- OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?)
+ OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS RAM (?)
Field (KSB0, ByteAcc, NoLock, Preserve) {
KSBI, 8, // Index
KSBD, 8 // Data
diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout
index a738864..1b53709 100644
--- a/src/mainboard/ibase/mb899/cmos.layout
+++ b/src/mainboard/ibase/mb899/cmos.layout
@@ -109,7 +109,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout
index b3a292f..f667702 100644
--- a/src/mainboard/intel/d945gclf/cmos.layout
+++ b/src/mainboard/intel/d945gclf/cmos.layout
@@ -95,7 +95,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/iwave/iWRainbowG6/cmos.layout b/src/mainboard/iwave/iWRainbowG6/cmos.layout
index 0e15662..5b24e05 100644
--- a/src/mainboard/iwave/iWRainbowG6/cmos.layout
+++ b/src/mainboard/iwave/iWRainbowG6/cmos.layout
@@ -103,7 +103,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index a429568..7d5e00b 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -159,5 +159,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index d2371b5..c7af739 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -160,5 +160,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 50869f7..8378014 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -160,5 +160,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout
index 5756bd7..6f88ea3 100644
--- a/src/mainboard/kontron/986lcd-m/cmos.layout
+++ b/src/mainboard/kontron/986lcd-m/cmos.layout
@@ -112,7 +112,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout
index 4761696..beee681 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -100,7 +100,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout
index a74d793..6e58086 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -100,7 +100,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index df78a0c..f4b5768 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -189,5 +189,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout
index a48bbee..a38b85b 100644
--- a/src/mainboard/roda/rk886ex/cmos.layout
+++ b/src/mainboard/roda/rk886ex/cmos.layout
@@ -100,7 +100,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c
index 2489a3c..099f78d 100644
--- a/src/mainboard/roda/rk886ex/m3885.c
+++ b/src/mainboard/roda/rk886ex/m3885.c
@@ -240,7 +240,7 @@ void m3885_configure_multikey(void)
u8 reg8;
u8 kstate5_flags, offs, maxvars;
- /* ram bank 0 */
+ /* RAM bank 0 */
kstate5_flags = m3885_get_variable(0x0c);
m3885_set_variable(0x0c, kstate5_flags & ~(7 << 4));
@@ -250,7 +250,7 @@ void m3885_configure_multikey(void)
}
- /* ram bank 2 */
+ /* RAM bank 2 */
m3885_set_variable(0x0c, (kstate5_flags & (~(7 << 4))) | (2 << 4));
/* Get the number of variables */
@@ -259,7 +259,7 @@ void m3885_configure_multikey(void)
if (maxvars >= 35) {
offs = m3885_get_variable(0x23);
if ((offs > 0xc0) || (offs < 0x80)) {
- printk(BIOS_DEBUG, "M388x does not have a valid ram offset (0x%x)\n", offs);
+ printk(BIOS_DEBUG, "M388x does not have a valid RAM offset (0x%x)\n", offs);
} else {
printk(BIOS_DEBUG, "Writing Fn-Table to M388x RAM offset 0x%x\n", offs);
for (i=0; i < ARRAY_SIZE(function_ram); i++) {
diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout
index 8f12ef4..da15a8b 100644
--- a/src/mainboard/roda/rk9/cmos.layout
+++ b/src/mainboard/roda/rk9/cmos.layout
@@ -97,7 +97,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 unused
-# ram initialization internal data
+# RAM initialization internal data
1024 128 r 0 read_training_results
# -----------------------------------------------------------------
diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c
index 2bdec28..fd7117b 100644
--- a/src/mainboard/roda/rk9/mainboard.c
+++ b/src/mainboard/roda/rk9/mainboard.c
@@ -110,7 +110,7 @@ static void verb_setup(void)
static void ec_setup(void)
{
- /* Thermal limits? Values are from ectool's ram dump. */
+ /* Thermal limits? Values are from ectool's RAM dump. */
ec_write(0xd1, 0x57); /* CPUH */
ec_write(0xd2, 0xc9); /* CPUL */
ec_write(0xd4, 0x64); /* SYSH */
diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc
index a6be0c2..89a9d20 100644
--- a/src/mainboard/samsung/lumpy/Makefile.inc
+++ b/src/mainboard/samsung/lumpy/Makefile.inc
@@ -24,7 +24,7 @@ ramstage-y += chromeos.c
SPD_BIN = $(obj)/spd.bin
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN):
xxd -rg1 $(src)/mainboard/samsung/lumpy/spd.hex >| $@
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index e3e7386..5070b30 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -216,5 +216,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 7d1f834..73d92d4 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -185,5 +185,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 425f677..7ae6f11 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -108,7 +108,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ print_debug("Disabling cache as RAM ");
disable_cache_as_ram();
print_debug("done\n");
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index da92d97..d1817be 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ print_debug("Disabling cache as RAM ");
disable_cache_as_ram();
print_debug("done\n");
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 55cb95e..68dc4cc 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -188,5 +188,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index dc3bde2..577876c 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -107,7 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ print_debug("Disabling cache as RAM ");
disable_cache_as_ram();
print_debug("done\n");
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index f319450..bfaf68e 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -861,7 +861,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
}
/* Leave a 64M hole between TOP_MEM and TOP_MEM2
- * so I can see my rom chip and other I/O devices.
+ * so I can see my ROM chip and other I/O devices.
*/
if (tom_k >= 0x003f0000) {
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
@@ -2482,7 +2482,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
//FIXME add enable node interleaving here -- yhlu
/*needed?
- 1. check how many nodes we have , if not all has ram installed get out
+ 1. check how many nodes we have , if not all has RAM installed get out
2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out
3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out
4. if all ready enable node_interleaving in f1 0x40..... of every node
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index b8417a6..4996d89 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1059,7 +1059,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
}
/* Leave a 64M hole between TOP_MEM and TOP_MEM2
- * so I can see my rom chip and other I/O devices.
+ * so I can see my ROM chip and other I/O devices.
*/
if (tom_k >= 0x003f0000) {
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index c8f7f94..b697e2e 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -98,7 +98,7 @@ static void pci_domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
- printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
+ printk(BIOS_DEBUG, "I would set RAM size to %d Mbytes\n", (tomk >> 10));
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 136dcf2..53a15e2 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -542,7 +542,7 @@ static void rom_shadow_settings(void)
*
* DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE
- * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
+ * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index df69b51..6a0e4ae 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -50,7 +50,7 @@
#define WRITE_COMBINE (1<<4)
#define WRITE_SERIALIZE (1<<5)
-/* ram has none of this stuff */
+/* RAM has none of this stuff */
#define RAM_PROPERTIES (0)
#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 82b3f48..8d3897b 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -595,7 +595,7 @@ static void rom_shadow_settings(void)
*
* DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE
- * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
+ * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c
index fcebed8..e7cd8ab 100644
--- a/src/northbridge/dmp/vortex86ex/northbridge.c
+++ b/src/northbridge/dmp/vortex86ex/northbridge.c
@@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev)
ss = pci_read_config16(mc_dev, 0x6c);
ss = ((ss >> 8) & 0xf);
tomk = (2 * 1024) << ss;
- printk(BIOS_DEBUG, "I would set ram size to %ld Mbytes\n", (tomk >> 10));
+ printk(BIOS_DEBUG, "I would set RAM size to %ld Mbytes\n", (tomk >> 10));
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk)
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index b0b150d..eff1617 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -57,7 +57,7 @@ static void pci_domain_set_resources(device_t dev)
/* Find the limit of the remap window */
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
}
- /* Write the ram configuration registers,
+ /* Write the RAM configuration registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 8f1632d..0afed18 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -58,7 +58,7 @@ static void pci_domain_set_resources(device_t dev)
/* Find the limit of the remap window */
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
}
- /* Write the ram configuration registers,
+ /* Write the RAM configuration registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, TOLM);
diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c
index c632b2d..a31b56f 100644
--- a/src/northbridge/intel/e7520/northbridge.c
+++ b/src/northbridge/intel/e7520/northbridge.c
@@ -72,7 +72,7 @@ static void pci_domain_set_resources(device_t dev)
/* Find the offset of the remap window from tolm */
remapoffsetk = remapbasek - tolmk;
}
- /* Write the ram configruation registers,
+ /* Write the RAM configruation registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 55be449..2f14513 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -93,7 +93,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
sz.side1 = 0;
sz.side2 = 0;
- /* test for ddr2 */
+ /* test for DDR2 */
ddr2=0;
value = spd_read_byte(device, 2); /* type */
if (value < 0) goto hw_err;
@@ -605,7 +605,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
if (dram_type >= 2) {
if (reg == 8) { /*speed is good, is this ddr2?*/
dram_type = 2;
- } else { /* not ddr2 so use ddr333 */
+ } else { /* not DDR2 so use DDR333 */
dram_type = 1;
}
}
@@ -666,7 +666,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
long dimm_mask;
- /* Test if we can read the spd and if ram is ddr or ddr2 */
+ /* Test if we can read the spd and if RAM is DDR or DDR2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
print_err("No memory for this cpu\n");
@@ -1272,7 +1272,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* enable on dimm termination */
set_on_dimm_termination_enable(ctrl);
}
- else { /* ddr */
+ else { /* DDR */
pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 );
}
diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c
index 7625596..8120645 100644
--- a/src/northbridge/intel/e7525/northbridge.c
+++ b/src/northbridge/intel/e7525/northbridge.c
@@ -71,7 +71,7 @@ static void pci_domain_set_resources(device_t dev)
/* Find the offset of the remap window from tolm */
remapoffsetk = remapbasek - tolmk;
}
- /* Write the ram configruation registers,
+ /* Write the RAM configruation registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 11f26ee..42065e6 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -96,7 +96,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
sz.side1 = 0;
sz.side2 = 0;
- /* test for ddr2 */
+ /* test for DDR2 */
ddr2=0;
value = spd_read_byte(device, 2); /* type */
if (value < 0) goto hw_err;
@@ -611,7 +611,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
if (dram_type >= 2) {
if (reg == 8) { /*speed is good, is this ddr2?*/
dram_type = 2;
- } else { /* not ddr2 so use ddr333 */
+ } else { /* not DDR2 so use DDR333 */
dram_type = 1;
}
}
@@ -672,7 +672,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
long dimm_mask;
- /* Test if we can read the spd and if ram is ddr or ddr2 */
+ /* Test if we can read the spd and if RAM is DDR or DDR2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
print_err("No memory for this cpu\n");
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index e06db75..5978fc1 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -39,7 +39,7 @@ config CACHE_MRC_SIZE_KB
int
default 512
-# FIXME: build from rom size
+# FIXME: build from ROM size
config MRC_CACHE_BASE
hex
default 0xff800000
@@ -77,7 +77,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
default 0x2000
help
The amount of anticipated stack usage from the data cache
- during pre-ram rom stage execution.
+ during pre-ram ROM stage execution.
config HAVE_MRC
bool "Add a System Agent binary"
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index dcce48d..6ffc594 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -96,7 +96,7 @@ static void pci_domain_set_resources(device_t dev)
/* Find the offset of the remap window from tolm */
remapoffsetk = remapbasek - tolmk;
}
- /* Write the ram configruation registers,
+ /* Write the RAM configruation registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 443972e..9fc9c89 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -607,7 +607,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
long dimm_mask;
- /* Test if we can read the spd and if ram is ddr or ddr2 */
+ /* Test if we can read the spd and if RAM is DDR or DDR2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
print_err("No memory for this cpu\n");
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index 5c0379c..ce4767e 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -91,7 +91,7 @@ static void pci_domain_set_resources(device_t dev)
*/
tolmk = tomk;
}
- /* Write the ram configuration registers,
+ /* Write the RAM configuration registers,
* preserving the reserved bits.
*/
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 0ab4d38..e6becc4 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -881,7 +881,7 @@ static void spd_update(u8 reg, u32 new_value)
#endif
}
-/* if ram still doesn't work do this function */
+/* if RAM still doesn't work do this function */
static void spd_set_undocumented_registers(void)
{
spd_update(0x74, 0x00000001);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 42233e8..2cbe81a 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -87,7 +87,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command)
static void ram_read32(u32 offset)
{
- PRINTK_DEBUG(" ram read: %08x\n", offset);
+ PRINTK_DEBUG(" RAM read: %08x\n", offset);
read32(offset);
}
@@ -1469,7 +1469,7 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno
val_err:
die("Bad SPD value\n");
hw_err:
- /* If a hardware error occurs the spd rom probably does not exist.
+ /* If a hardware error occurs the spd ROM probably does not exist.
* In this case report that there is no memory
*/
sz.side1 = 0;
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
index 23a6209..fcb1315 100644
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -20,7 +20,7 @@
*/
/*
- Automatically detect and set up ddr dram on the CN400 chipset.
+ Automatically detect and set up DDR dram on the CN400 chipset.
Assumes DDR400 memory as no attempt is made to clock
the chipset down if slower memory is installed.
So far tested on:
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index c09fbb4..ac44a3c 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -224,7 +224,7 @@ static void cx700_set_lpc_registers(struct device *dev)
// Power management setup
setup_pm(dev);
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
/* Enable HPET timer */
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index bed434d..4c29e60 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -74,7 +74,7 @@ static void pci_domain_set_resources(device_t dev)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
- printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+ printk(BIOS_DEBUG, "I would set RAM size to 0x%x Kbytes\n", (rambits)*8*1024);
tomk = rambits*8*1024;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 6e0f4ea..88140d9 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -133,7 +133,7 @@ static void pci_domain_set_resources(device_t dev)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
- printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
+ printk(BIOS_DEBUG, "I would set RAM size to 0x%x Kbytes\n", (rambits)*16*1024);
tomk = rambits*16*1024 - 32768;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index b5c78a1..be1e7ee 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -19,7 +19,7 @@
*/
/*
- Automatically detect and set up ddr dram on the CLE266 chipset.
+ Automatically detect and set up DDR dram on the CLE266 chipset.
Assumes DDR memory, though chipset also supports SDRAM
Assumes at least 266Mhz memory as no attempt is made to clock
the chipset down if slower memory is installed.
diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index 3f9c70f..863a3a4 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -940,7 +940,7 @@ void main(void)
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
d0f2pcitable[i]);
}
- //0x90 look d0f2 appendixA1 , if set this to 09 or 0b, then some ddr2 will crash.
+ //0x90 look d0f2 appendixA1 , if set this to 09 or 0b, then some DDR2 will crash.
for (i = 65; i < 113; i++) {
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
d0f2pcitable[i]);
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 2ab3e64..569d951 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -394,7 +394,7 @@ g) Rx73h = 32h
/*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */
DRAMDetect(&DramAttr);
- /*begin to get ram size, 43,42 41 40 contains the end address of last rank in ddr2-slot */
+ /*begin to get RAM size, 43,42 41 40 contains the end address of last rank in ddr2-slot */
device = PCI_DEV(0, 0, 3);
for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
rambits = pci_read_config8(device, ramregs[i]);
diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c
index 1908a8a..2593b63 100644
--- a/src/northbridge/via/vx800/lpc.c
+++ b/src/northbridge/via/vx800/lpc.c
@@ -291,7 +291,7 @@ static void vx800_sb_init(struct device *dev)
// Power management setup
setup_pm(dev);
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c
index a87e65e..f652a35 100644
--- a/src/northbridge/via/vx800/northbridge.c
+++ b/src/northbridge/via/vx800/northbridge.c
@@ -74,7 +74,7 @@ static const struct pci_driver memctrl_driver __pci_driver = {
static void pci_domain_set_resources(device_t dev)
{
/*
- * the order is important to find the correct ram size.
+ * the order is important to find the correct RAM size.
*/
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
device_t mc_dev;
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 53cada3..7a1d8ca 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -262,7 +262,7 @@ static void vx900_set_resources(device_t dev)
tolmk = MIN(full_tolmk, tomk);
tolmk -= fbufk;
ram_resource(dev, idx++, 0, 640);
- printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10);
+ printk(BIOS_SPEW, "System RAM left: %dMB\n", tolmk >> 10);
/* FIXME: how can we avoid leaving this hole?
* Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */
/* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem
diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h
index e936072..cebe2b6 100644
--- a/src/soc/intel/baytrail/baytrail/iosf.h
+++ b/src/soc/intel/baytrail/baytrail/iosf.h
@@ -189,7 +189,7 @@ void iosf_ssus_write(int reg, uint32_t val);
#define BNOCACHE 0x23
/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
#define BUNIT_BMBOUND 0x25
-/* BMBOUND_HI describes the available ram above 4GiB. It has a
+/* BMBOUND_HI describes the available RAM above 4GiB. It has a
* 256MiB granularity. Physical address bits 35:28 are compared with 31:24
* bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
* granularity care needs to be taken with the e820 map to account for a hole
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 3a1d65d..a6a8ca8 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -359,7 +359,7 @@ static void *setup_stack_and_mttrs(void)
num_mtrrs++;
top_of_ram = (uint32_t)cbmem_top();
- /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
+ /* Cache 8MiB below the top of RAM. The top of RAM under 4GiB is the
* start of the TSEG region. It is required to be 8MiB aligned. Set
* this area as cacheable so it can be used later for ramstage before
* setting up the entire RAM as cacheable. */
@@ -369,7 +369,7 @@ static void *setup_stack_and_mttrs(void)
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
num_mtrrs++;
- /* Cache 8MiB at the top of ram. Top of ram is where the TSEG
+ /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG
* region resides. However, it is not restricted to SMM mode until
* SMM has been relocated. By setting the region to cacheable it
* provides faster access when relocating the SMM handler as well
diff --git a/src/soc/intel/fsp_baytrail/baytrail/iosf.h b/src/soc/intel/fsp_baytrail/baytrail/iosf.h
index 8fd1e24..afe846f 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/iosf.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/iosf.h
@@ -90,7 +90,7 @@ void iosf_lpss_write(int reg, uint32_t val);
#define BNOCACHE 0x23
/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
#define BUNIT_BMBOUND 0x25
-/* BMBOUND_HI describes the available ram above 4GiB. It has a
+/* BMBOUND_HI describes the available RAM above 4GiB. It has a
* 256MiB granularity. Physical address bits 35:28 are compared with 31:24
* bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
* granularity care needs to be taken with the e820 map to account for a hole
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index c8051ec..5b2a97e 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -64,7 +64,7 @@ static void lpc_init(device_t dev)
interrupt and visit LPC. */
pci_write_config8(dev, 0x78, byte);
- /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */
+ /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
byte = pci_read_config8(dev, 0xBB);
byte |= 1 << 0 | 1 << 3;
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 1027659..060e6ed 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -49,7 +49,7 @@ static void sb700_enable_rom(void)
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
pci_io_write_config32(dev, 0x48, dword);
- /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+ /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
/* Set the 4MB enable bits */
word = pci_io_read_config16(dev, 0x6c);
word = 0xFFC0;
@@ -58,6 +58,6 @@ static void sb700_enable_rom(void)
static void bootblock_southbridge_init(void)
{
- /* Setup the rom access for 2M */
+ /* Setup the ROM access for 2M */
sb700_enable_rom();
}
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index ac25e89..17fe012 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -218,7 +218,7 @@ config SB800_IMC_FAN_CONTROL
depends on SB800_IMC_FWM
help
Set up the SB800 to use the IMC based Fan controller. This requires
- the IMC rom from AMD. Configure the registers in devicetree.cb.
+ the IMC ROM from AMD. Configure the registers in devicetree.cb.
endchoice
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 4fd2739..9e7bfbc 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -48,7 +48,7 @@ static void enable_rom(void)
dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
pci_io_write_config32(dev, 0x48, dword);
- /* Enable rom access */
+ /* Enable ROM access */
word = pci_io_read_config16(dev, 0x6c);
word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
pci_io_write_config16(dev, 0x6c, word);
@@ -111,7 +111,7 @@ static void enable_clocks(void)
static void bootblock_southbridge_init(void)
{
- /* Setup the rom access for 2M */
+ /* Setup the ROM access for 2M */
enable_rom();
enable_prefetch();
enable_spi_fast_mode();
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index 9108a8b..a835658 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -48,7 +48,7 @@ static void sb900_enable_rom(void)
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
pci_io_write_config32(dev, 0x48, dword);
- /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+ /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
/* Set the 4MB enable bits */
word = pci_io_read_config16(dev, 0x6c);
word = 0xFFC0;
@@ -57,6 +57,6 @@ static void sb900_enable_rom(void)
static void bootblock_southbridge_init(void)
{
- /* Setup the rom access for 2M */
+ /* Setup the ROM access for 2M */
sb900_enable_rom();
}
diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c
index fd4c4ba..37c3580 100644
--- a/src/southbridge/amd/cs5535/chipsetinit.c
+++ b/src/southbridge/amd/cs5535/chipsetinit.c
@@ -310,7 +310,7 @@ chipsetinit(void)
outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
/* Allow IO read and writes during a ATA DMA operation. */
- /* This could be done in the HD rom but do it here for easier debugging. */
+ /* This could be done in the HD ROM but do it here for easier debugging. */
msrnum = ATA_SB_GLD_MSR_ERR;
msr = rdmsr(msrnum);
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index e305594..fedd6e8 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -562,7 +562,7 @@ void chipsetinit(void)
outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
/* Allow IO read and writes during a ATA DMA operation. */
- /* This could be done in the HD rom but do it here for easier debugging. */
+ /* This could be done in the HD ROM but do it here for easier debugging. */
msrnum = ATA_SB_GLD_MSR_ERR;
msr = rdmsr(msrnum);
msr.lo &= ~0x100;
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 12fd96f..090a280 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -61,7 +61,7 @@ static void lpc_init(device_t dev)
interrupt and visit LPC. */
pci_write_config8(dev, 0x78, byte);
- /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */
+ /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
byte = pci_read_config8(dev, 0xBB);
byte |= 1 << 0 | 1 << 3;
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
index 67bcadc..58c9fc3 100644
--- a/src/southbridge/intel/esb6300/lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
@@ -247,7 +247,7 @@ static void lpc_init(struct device *dev)
/* disable reset timer */
pci_write_config8(dev, 0xd4, 0x02);
- /* cmos ram 2nd 128 */
+ /* cmos RAM 2nd 128 */
pci_write_config8(dev, 0xd8, 0x04);
/* comm 2 */
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index 09874f7..d138b6c 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -86,7 +86,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->flush_stride = 0;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
- fadt->day_alrm = 0x0d; /* rtc cmos ram offset */
+ fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */
fadt->mon_alrm = 0x0; /* not supported */
fadt->century = 0x0; /* not supported */
/*
diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c
index 40854db..8b307ed 100644
--- a/src/southbridge/via/vt8231/lpc.c
+++ b/src/southbridge/via/vt8231/lpc.c
@@ -116,7 +116,7 @@ static void vt8231_init(struct device *dev)
pci_write_config8(dev, 0x47, 0x03);
pci_write_config8(dev, 0x6e, 0x98);
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
//ethernet_fixup();
diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c
index b355ad0..47881f4 100644
--- a/src/southbridge/via/vt8235/lpc.c
+++ b/src/southbridge/via/vt8235/lpc.c
@@ -205,7 +205,7 @@ static void vt8235_init(struct device *dev)
// Power management setup
setup_pm(dev);
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
index 1dbe440..6093f8f 100644
--- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
@@ -225,7 +225,7 @@ CopyHeapToMainRamAtPost (
AgesaStatus = AgesaAllocateBuffer (0, &agesaAllocateBuffer);
if (AgesaStatus == AGESA_SUCCESS) {
- // copy heap from temp ram to real ram
+ // copy heap from temp RAM to real ram
HeapMainRamPtr = (UINT8 *) agesaAllocateBuffer.BufferPointer;
HeapTempRamPtr = (UINT8 *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE));
for (i = 0; i < CurrentNodePtr->BufferSize; i++) {
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
index 2421bb9..5a25f6f 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
@@ -195,7 +195,7 @@ ExecuteFinalHltInstruction (
// Make sure not to touch any Shared MSR from this point on
- // Restore settings that were temporarily overridden for the cache as ram phase
+ // Restore settings that were temporarily overridden for the cache as RAM phase
data = __readmsr (0xC0011022); // MSR_DC_CFG
data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD
data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
index 1bad891..a208a4e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
@@ -192,7 +192,7 @@ ExecuteFinalHltInstruction (
// Make sure not to touch any Shared MSR from this point on
- // Restore settings that were temporarily overridden for the cache as ram phase
+ // Restore settings that were temporarily overridden for the cache as RAM phase
data = __readmsr (0xC0011022); // MSR_DC_CFG
data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD
data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
index 84a02d1..9840c55 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
@@ -368,7 +368,7 @@ GnbSmuFirmwareLoadV4 (
if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 1) {
IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init autehtication vector\n");
- // Step 16, Wait for rom firmware init autehtication vector
+ // Step 16, Wait for ROM firmware init autehtication vector
do {
GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, 0x80010000 , AccessWidth32, &ex1005.Value, StdHeader);
} while (ex1005.Value != 0x400);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
index 2f40389..a523380 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c
@@ -281,8 +281,8 @@ GnbSmuFirmwareLoadV7 (
if (BfxSmuProtectedMode == 1) {
IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init authentication vector\n");
- // Step 16, Wait for rom firmware init authentication vector
- IDS_HDT_CONSOLE (GNB_TRACE, "Step 16, Wait for rom firmware init authentication vector\n");
+ // Step 16, Wait for ROM firmware init authentication vector
+ IDS_HDT_CONSOLE (GNB_TRACE, "Step 16, Wait for ROM firmware init authentication vector\n");
do {
GnbUraGet (&DevObject, TRxSmuAuthVector, &RxSmuAuthVector);
} while (RxSmuAuthVector != 0x400);
diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c
index 048850d..a5faaa4 100644
--- a/src/vendorcode/amd/cimx/sb800/SBPOR.c
+++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c
@@ -242,9 +242,9 @@ sbPowerOnInit (
//The following bits must be set before enabling SPI prefetch.
// Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0).
// if Ec is enable
- // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed.
+ // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the ROM can run at the speed.
// else
- // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at
+ // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the ROM can run at
// the speed.
getChipSysMode (&dbSysConfig);
if (pConfig->BuildParameters.SpiSpeed < 0x02) {
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index fabede3..8f666f2 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -373,14 +373,14 @@ static const struct timestamp_id_to_name {
u32 id;
const char *name;
} timestamp_ids[] = {
- { TS_START_ROMSTAGE, "start of rom stage" },
- { TS_BEFORE_INITRAM, "before ram initialization" },
- { TS_AFTER_INITRAM, "after ram initialization" },
+ { TS_START_ROMSTAGE, "start of ROM stage" },
+ { TS_BEFORE_INITRAM, "before RAM initialization" },
+ { TS_AFTER_INITRAM, "after RAM initialization" },
{ TS_END_ROMSTAGE, "end of romstage" },
{ TS_START_VBOOT, "start of verified boot" },
{ TS_END_VBOOT, "end of verified boot" },
- { TS_START_COPYRAM, "start of copying ram stage" },
- { TS_END_COPYRAM, "end of copying ram stage" },
+ { TS_START_COPYRAM, "start of copying RAM stage" },
+ { TS_END_COPYRAM, "end of copying RAM stage" },
{ TS_START_RAMSTAGE, "start of ramstage" },
{ TS_DEVICE_ENUMERATE, "device enumeration" },
{ TS_DEVICE_CONFIGURE, "device configuration" },
diff --git a/util/mkelfImage/linux-i386/uniform_boot.h b/util/mkelfImage/linux-i386/uniform_boot.h
index ac81496..8009dfd 100644
--- a/util/mkelfImage/linux-i386/uniform_boot.h
+++ b/util/mkelfImage/linux-i386/uniform_boot.h
@@ -4,7 +4,7 @@
/* The uniform boot environment information is restricted to
* hardware information. In particular for a simple enough machine
* all of the environment information should be able to reside in
- * a rom and not need to be moved. This information is the
+ * a ROM and not need to be moved. This information is the
* information a trivial boot room can pass to linux to let it
* run the hardware.
*
diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c
index 569d75b..83cfd4a 100644
--- a/util/romcc/tests/raminit_test.c
+++ b/util/romcc/tests/raminit_test.c
@@ -449,7 +449,7 @@ static void set_pam(void)
static void set_drb(void)
{
/* DRB - DRAM Row Boundary Registers */
- /* Conservative setting 8MB of ram on first DIMM... */
+ /* Conservative setting 8MB of RAM on first DIMM... */
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60, 0x01);
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x61, 0x01);
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x62, 0x01);
@@ -705,7 +705,7 @@ static void spd_set_drb(void)
side1_bits += log2((byte2 << 8) | byte);
#endif
- /* now I have the ram size in bits as a power of two (less 1) */
+ /* now I have the RAM size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
@@ -754,19 +754,19 @@ static void spd_set_dramc(void)
{
/*
* Effects: Uses serial presence detect to set the
- * DRAMC register, which records if ram is registerd or not,
+ * DRAMC register, which records if RAM is registerd or not,
* and controls the refresh rate.
* The refresh rate is not set here, as memory refresh
* cannot be enbaled until after memory is initialized.
* see spd_enable_refresh.
*/
- /* auto detect if ram is registered or not. */
+ /* auto detect if RAM is registered or not. */
/* The DRAMC register also contorls the refresh rate but we can't
* set that here because we must leave refresh disabled.
* see: spd_enable_refresh
*/
/* Find the first dimm and assume the rest are the same */
- /* FIXME Check for illegal/unsupported ram configurations and abort */
+ /* FIXME Check for illegal/unsupported RAM configurations and abort */
unsigned device;
int byte;
unsigned dramc;
@@ -805,7 +805,7 @@ static void spd_enable_refresh(void)
* Effects: Uses serial presence detect to set the
* refresh rate in the DRAMC register.
* see spd_set_dramc for the other values.
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
#if HAVE_STATIC_ARRAY_SUPPORT
static const unsigned char refresh_rates[] = {
@@ -836,7 +836,7 @@ static void spd_enable_refresh(void)
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
- /* see if the ram refresh is a supported one */
+ /* see if the RAM refresh is a supported one */
if (byte < 6) {
#if HAVE_STATIC_ARRAY_SUPPORT
refresh_rate = refresh_rates[byte];
@@ -858,7 +858,7 @@ static void spd_set_rps(void)
/*
* Effects: Uses serial presence detect to set the row size
* on a given DIMM
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
/* The RPS register holds the size of a ``page'' of DRAM on each DIMM */
unsigned page_sizes;
@@ -924,7 +924,7 @@ static void spd_set_pgpol(void)
/*
* Effects: Uses serial presence detect to set the number of banks
* on a given DIMM
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
/* The PGPOL register stores the number of logical banks per DIMM,
* and number of clocks the DRAM controller waits in the idle
@@ -965,7 +965,7 @@ static void spd_set_nbxcfg(void)
/*
* Effects: Uses serial presence detect to set the
* ECC support flags in the NBXCFG register
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
unsigned reg;
unsigned index;
@@ -1174,7 +1174,7 @@ unsigned long sdram_get_ecc_size_bytes(void)
{
unsigned char byte;
unsigned long size;
- /* FIXME handle the no ram case. */
+ /* FIXME handle the no RAM case. */
/* Read the RAM SIZE */
byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67);
/* Convert it to bytes */
diff --git a/util/romcc/tests/raminit_test1.c b/util/romcc/tests/raminit_test1.c
index 569d75b..83cfd4a 100644
--- a/util/romcc/tests/raminit_test1.c
+++ b/util/romcc/tests/raminit_test1.c
@@ -449,7 +449,7 @@ static void set_pam(void)
static void set_drb(void)
{
/* DRB - DRAM Row Boundary Registers */
- /* Conservative setting 8MB of ram on first DIMM... */
+ /* Conservative setting 8MB of RAM on first DIMM... */
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60, 0x01);
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x61, 0x01);
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x62, 0x01);
@@ -705,7 +705,7 @@ static void spd_set_drb(void)
side1_bits += log2((byte2 << 8) | byte);
#endif
- /* now I have the ram size in bits as a power of two (less 1) */
+ /* now I have the RAM size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
@@ -754,19 +754,19 @@ static void spd_set_dramc(void)
{
/*
* Effects: Uses serial presence detect to set the
- * DRAMC register, which records if ram is registerd or not,
+ * DRAMC register, which records if RAM is registerd or not,
* and controls the refresh rate.
* The refresh rate is not set here, as memory refresh
* cannot be enbaled until after memory is initialized.
* see spd_enable_refresh.
*/
- /* auto detect if ram is registered or not. */
+ /* auto detect if RAM is registered or not. */
/* The DRAMC register also contorls the refresh rate but we can't
* set that here because we must leave refresh disabled.
* see: spd_enable_refresh
*/
/* Find the first dimm and assume the rest are the same */
- /* FIXME Check for illegal/unsupported ram configurations and abort */
+ /* FIXME Check for illegal/unsupported RAM configurations and abort */
unsigned device;
int byte;
unsigned dramc;
@@ -805,7 +805,7 @@ static void spd_enable_refresh(void)
* Effects: Uses serial presence detect to set the
* refresh rate in the DRAMC register.
* see spd_set_dramc for the other values.
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
#if HAVE_STATIC_ARRAY_SUPPORT
static const unsigned char refresh_rates[] = {
@@ -836,7 +836,7 @@ static void spd_enable_refresh(void)
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
- /* see if the ram refresh is a supported one */
+ /* see if the RAM refresh is a supported one */
if (byte < 6) {
#if HAVE_STATIC_ARRAY_SUPPORT
refresh_rate = refresh_rates[byte];
@@ -858,7 +858,7 @@ static void spd_set_rps(void)
/*
* Effects: Uses serial presence detect to set the row size
* on a given DIMM
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
/* The RPS register holds the size of a ``page'' of DRAM on each DIMM */
unsigned page_sizes;
@@ -924,7 +924,7 @@ static void spd_set_pgpol(void)
/*
* Effects: Uses serial presence detect to set the number of banks
* on a given DIMM
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
/* The PGPOL register stores the number of logical banks per DIMM,
* and number of clocks the DRAM controller waits in the idle
@@ -965,7 +965,7 @@ static void spd_set_nbxcfg(void)
/*
* Effects: Uses serial presence detect to set the
* ECC support flags in the NBXCFG register
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
unsigned reg;
unsigned index;
@@ -1174,7 +1174,7 @@ unsigned long sdram_get_ecc_size_bytes(void)
{
unsigned char byte;
unsigned long size;
- /* FIXME handle the no ram case. */
+ /* FIXME handle the no RAM case. */
/* Read the RAM SIZE */
byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67);
/* Convert it to bytes */
diff --git a/util/romcc/tests/raminit_test2.c b/util/romcc/tests/raminit_test2.c
index d20ae6d..bbdb3b2 100644
--- a/util/romcc/tests/raminit_test2.c
+++ b/util/romcc/tests/raminit_test2.c
@@ -449,7 +449,7 @@ static void set_pam(void)
static void set_drb(void)
{
/* DRB - DRAM Row Boundary Registers */
- /* Conservative setting 8MB of ram on first DIMM... */
+ /* Conservative setting 8MB of RAM on first DIMM... */
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60, 0x01);
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x61, 0x01);
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x62, 0x01);
@@ -705,7 +705,7 @@ static void spd_set_drb(void)
side1_bits += log2((byte2 << 8) | byte);
#endif
- /* now I have the ram size in bits as a power of two (less 1) */
+ /* now I have the RAM size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
@@ -754,19 +754,19 @@ static void spd_set_dramc(void)
{
/*
* Effects: Uses serial presence detect to set the
- * DRAMC register, which records if ram is registerd or not,
+ * DRAMC register, which records if RAM is registerd or not,
* and controls the refresh rate.
* The refresh rate is not set here, as memory refresh
* cannot be enbaled until after memory is initialized.
* see spd_enable_refresh.
*/
- /* auto detect if ram is registered or not. */
+ /* auto detect if RAM is registered or not. */
/* The DRAMC register also contorls the refresh rate but we can't
* set that here because we must leave refresh disabled.
* see: spd_enable_refresh
*/
/* Find the first dimm and assume the rest are the same */
- /* FIXME Check for illegal/unsupported ram configurations and abort */
+ /* FIXME Check for illegal/unsupported RAM configurations and abort */
unsigned device;
int byte;
unsigned dramc;
@@ -805,7 +805,7 @@ static void spd_enable_refresh(void)
* Effects: Uses serial presence detect to set the
* refresh rate in the DRAMC register.
* see spd_set_dramc for the other values.
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
#if HAVE_STATIC_ARRAY_SUPPORT
static const unsigned char refresh_rates[] = {
@@ -836,7 +836,7 @@ static void spd_enable_refresh(void)
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
- /* see if the ram refresh is a supported one */
+ /* see if the RAM refresh is a supported one */
if (byte < 6) {
#if HAVE_STATIC_ARRAY_SUPPORT
refresh_rate = refresh_rates[byte];
@@ -858,7 +858,7 @@ static void spd_set_rps(void)
/*
* Effects: Uses serial presence detect to set the row size
* on a given DIMM
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
/* The RPS register holds the size of a ``page'' of DRAM on each DIMM */
unsigned page_sizes;
@@ -924,7 +924,7 @@ static void spd_set_pgpol(void)
/*
* Effects: Uses serial presence detect to set the number of banks
* on a given DIMM
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
/* The PGPOL register stores the number of logical banks per DIMM,
* and number of clocks the DRAM controller waits in the idle
@@ -965,7 +965,7 @@ static void spd_set_nbxcfg(void)
/*
* Effects: Uses serial presence detect to set the
* ECC support flags in the NBXCFG register
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
unsigned reg;
unsigned index;
@@ -1174,7 +1174,7 @@ unsigned long sdram_get_ecc_size_bytes(void)
{
unsigned char byte;
unsigned long size;
- /* FIXME handle the no ram case. */
+ /* FIXME handle the no RAM case. */
/* Read the RAM SIZE */
byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67);
/* Convert it to bytes */
diff --git a/util/romcc/tests/simple_test3.c b/util/romcc/tests/simple_test3.c
index 864760c..0171d93 100644
--- a/util/romcc/tests/simple_test3.c
+++ b/util/romcc/tests/simple_test3.c
@@ -19,7 +19,7 @@ static void spd_set_drb(void)
/* rows */
byte = -1;
if (1) {
- /* now I have the ram size in bits as a power of two (less 1) */
+ /* now I have the RAM size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
}
diff --git a/util/romcc/tests/simple_test4.c b/util/romcc/tests/simple_test4.c
index 2ac6a4d..ea2f7d2 100644
--- a/util/romcc/tests/simple_test4.c
+++ b/util/romcc/tests/simple_test4.c
@@ -465,7 +465,7 @@ static void spd_set_drb(void)
side1_bits += log2((((byte2 << 8) | byte));
#endif
- /* now I have the ram size in bits as a power of two (less 1) */
+ /* now I have the RAM size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
diff --git a/util/romcc/tests/simple_test5.c b/util/romcc/tests/simple_test5.c
index 725d745..c013f3a 100644
--- a/util/romcc/tests/simple_test5.c
+++ b/util/romcc/tests/simple_test5.c
@@ -260,7 +260,7 @@ static void spd_enable_refresh(void)
* Effects: Uses serial presence detect to set the
* refresh rate in the DRAMC register.
* see spd_set_dramc for the other values.
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
#if HAVE_STATIC_ARRAY_SUPPORT
static const unsigned char refresh_rates[] = {
@@ -291,7 +291,7 @@ static void spd_enable_refresh(void)
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
- /* see if the ram refresh is a supported one */
+ /* see if the RAM refresh is a supported one */
if (byte < 6) {
#if HAVE_STATIC_ARRAY_SUPPORT
refresh_rate = refresh_rates[byte];
diff --git a/util/romcc/tests/simple_test56.c b/util/romcc/tests/simple_test56.c
index 570b4ee..2a19505 100644
--- a/util/romcc/tests/simple_test56.c
+++ b/util/romcc/tests/simple_test56.c
@@ -5,7 +5,7 @@ static void spd_enable_refresh(void)
* Effects: Uses serial presence detect to set the
* refresh rate in the DRAMC register.
* see spd_set_dramc for the other values.
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
static const unsigned char refresh_rates[] = {
0x01, /* Normal 15.625 us -> 15.6 us */
@@ -32,7 +32,7 @@ static void spd_enable_refresh(void)
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
- /* see if the ram refresh is a supported one */
+ /* see if the RAM refresh is a supported one */
if (byte < 6) {
refresh_rate = refresh_rates[byte];
}
diff --git a/util/romcc/tests/simple_test61.c b/util/romcc/tests/simple_test61.c
index 2b235cc..84dc680 100644
--- a/util/romcc/tests/simple_test61.c
+++ b/util/romcc/tests/simple_test61.c
@@ -3,7 +3,7 @@ static void spd_set_nbxcfg(void)
/*
* Effects: Uses serial presence detect to set the
* ECC support flags in the NBXCFG register
- * FIXME: Check for illegal/unsupported ram configurations and abort
+ * FIXME: Check for illegal/unsupported RAM configurations and abort
*/
unsigned device;
diff --git a/util/vgabios/testbios.c b/util/vgabios/testbios.c
index c12e721..247baff 100644
--- a/util/vgabios/testbios.c
+++ b/util/vgabios/testbios.c
@@ -192,7 +192,7 @@ int main(int argc, char **argv)
have_size = 1;
break;
case 'p':
- printf("Parsing rom images not implemented.\n");
+ printf("Parsing ROM images not implemented.\n");
parse_rom = 1;
break;
case 'f':
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