[coreboot-gerrit] New patch to review for coreboot: 07f6c5e armv7: add wrapper for DCCSW (data cache clean by set/way)
Isaac Christensen (isaac.christensen@se-eng.com)
gerrit at coreboot.org
Wed Jul 30 20:51:55 CEST 2014
Isaac Christensen (isaac.christensen at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6418
-gerrit
commit 07f6c5e2380ce3f6cb8e05ecf079cefd35efa47b
Author: David Hendricks <dhendrix at chromium.org>
Date: Fri Aug 16 12:17:50 2013 -0700
armv7: add wrapper for DCCSW (data cache clean by set/way)
This adds a wrapper for data cache clean (without invalidate)
by set/way.
Signed-off-by: David Hendricks <dhendrix at chromium.org>
Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2
Reviewed-on: https://gerrit.chromium.org/gerrit/66118
Commit-Queue: David Hendricks <dhendrix at chromium.org>
Tested-by: David Hendricks <dhendrix at chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich at chromium.org>
(cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001)
armv7: clean but do not invalidate caches between stages
This cleans the caches without invalidating them between stages. The
dcache content should still be valid when the next stage begins, so
we should see a small performance gain.
(thanks to gabeblack for pointing this out)
Signed-off-by: David Hendricks <dhendrix at chromium.org>
Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa
Reviewed-on: https://gerrit.chromium.org/gerrit/66119
Commit-Queue: David Hendricks <dhendrix at chromium.org>
Tested-by: David Hendricks <dhendrix at chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich at chromium.org>
(cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d)
armv7: Make coreboot and libpayload cache files the same
This merges the difference between the ARM version of cache.c and
cache.h for libpayload and coreboot.
Signed-off-by: David Hendricks <dhendrix at chromium.org>
Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93
Reviewed-on: https://gerrit.chromium.org/gerrit/66120
Commit-Queue: David Hendricks <dhendrix at chromium.org>
Tested-by: David Hendricks <dhendrix at chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich at chromium.org>
(cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6)
Squashed three related commits.
Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee
Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
---
payloads/libpayload/arch/armv7/cache.c | 6 ++++++
payloads/libpayload/include/armv7/arch/cache.h | 16 ++++++++++++++++
src/arch/armv7/cache.c | 15 +++++++++++++++
src/arch/armv7/include/arch/cache.h | 11 +++++++++++
src/arch/armv7/stages.c | 2 +-
5 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/arch/armv7/cache.c b/payloads/libpayload/arch/armv7/cache.c
index efdf75e..644a870 100644
--- a/payloads/libpayload/arch/armv7/cache.c
+++ b/payloads/libpayload/arch/armv7/cache.c
@@ -76,6 +76,7 @@ void icache_invalidate_all(void)
}
enum dcache_op {
+ OP_DCCSW,
OP_DCCISW,
OP_DCISW,
OP_DCCIMVAC,
@@ -175,6 +176,11 @@ static void dcache_foreach(enum dcache_op op)
}
}
+void dcache_clean_all(void)
+{
+ dcache_foreach(OP_DCCSW);
+}
+
void dcache_clean_invalidate_all(void)
{
dcache_foreach(OP_DCCISW);
diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h
index 0414da3..0756f11 100644
--- a/payloads/libpayload/include/armv7/arch/cache.h
+++ b/payloads/libpayload/include/armv7/arch/cache.h
@@ -110,6 +110,12 @@ static inline void tlbiall(void)
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
}
+/* invalidate unified TLB by MVA, all ASID */
+static inline void tlbimvaa(unsigned long mva)
+{
+ asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory");
+}
+
/* write data access control register (DACR) */
static inline void write_dacr(uint32_t val)
{
@@ -164,6 +170,12 @@ static inline void dccmvac(unsigned long mva)
asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
}
+/* data cache clean by set/way */
+static inline void dccsw(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory");
+}
+
/* data cache invalidate by MVA to PoC */
static inline void dcimvac(unsigned long mva)
{
@@ -286,6 +298,8 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
/* dcache invalidate by modified virtual address to PoC */
void dcache_invalidate_by_mva(unsigned long addr, unsigned long len);
+void dcache_clean_all(void);
+
/* dcache invalidate all (on current level given by CCSELR) */
void dcache_invalidate_all(void);
@@ -317,6 +331,8 @@ enum dcache_policy {
DCACHE_WRITETHROUGH,
};
+/* disable the mmu for a range. Primarily useful to lock out address 0. */
+void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
/* mmu range configuration (set dcache policy) */
void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
enum dcache_policy policy);
diff --git a/src/arch/armv7/cache.c b/src/arch/armv7/cache.c
index 4046451..644a870 100644
--- a/src/arch/armv7/cache.c
+++ b/src/arch/armv7/cache.c
@@ -76,10 +76,12 @@ void icache_invalidate_all(void)
}
enum dcache_op {
+ OP_DCCSW,
OP_DCCISW,
OP_DCISW,
OP_DCCIMVAC,
OP_DCCMVAC,
+ OP_DCIMVAC,
};
/*
@@ -174,6 +176,11 @@ static void dcache_foreach(enum dcache_op op)
}
}
+void dcache_clean_all(void)
+{
+ dcache_foreach(OP_DCCSW);
+}
+
void dcache_clean_invalidate_all(void)
{
dcache_foreach(OP_DCCISW);
@@ -220,6 +227,9 @@ static void dcache_op_mva(unsigned long addr,
case OP_DCCMVAC:
dccmvac(line);
break;
+ case OP_DCIMVAC:
+ dcimvac(line);
+ break;
default:
break;
}
@@ -238,6 +248,11 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
dcache_op_mva(addr, len, OP_DCCIMVAC);
}
+void dcache_invalidate_by_mva(unsigned long addr, unsigned long len)
+{
+ dcache_op_mva(addr, len, OP_DCIMVAC);
+}
+
void dcache_mmu_disable(void)
{
uint32_t sctlr;
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index 8a14ff9..0756f11 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -170,6 +170,12 @@ static inline void dccmvac(unsigned long mva)
asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
}
+/* data cache clean by set/way */
+static inline void dccsw(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory");
+}
+
/* data cache invalidate by MVA to PoC */
static inline void dcimvac(unsigned long mva)
{
@@ -289,6 +295,11 @@ void dcache_clean_by_mva(unsigned long addr, unsigned long len);
/* dcache clean and invalidate by modified virtual address to PoC */
void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
+/* dcache invalidate by modified virtual address to PoC */
+void dcache_invalidate_by_mva(unsigned long addr, unsigned long len);
+
+void dcache_clean_all(void);
+
/* dcache invalidate all (on current level given by CCSELR) */
void dcache_invalidate_all(void);
diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c
index 0d2072d..38d1b19 100644
--- a/src/arch/armv7/stages.c
+++ b/src/arch/armv7/stages.c
@@ -52,7 +52,7 @@ void stage_exit(void *addr)
/* make sure any code we installed is written to memory. Not all ARM have
* unified caches.
*/
- dcache_clean_invalidate_all();
+ dcache_clean_all();
/* Because most stages copy code to memory, it's a safe and hygienic thing
* to flush the icache here.
*/
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