[coreboot-gerrit] Patch set updated for coreboot: 98fdd6e northbridge/intel: Various fsp_rangeley northbridge cleanups
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Thu Jul 31 10:19:23 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6420
-gerrit
commit 98fdd6e6c2ec6115200c048d273bd811b6be3715
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Thu Jul 31 09:07:38 2014 +1000
northbridge/intel: Various fsp_rangeley northbridge cleanups
Alphabetize headers and some minor style clean ups, nothing
significant to see here.
Introduced in:
2963ae7 northbridge/intel: Add fsp_rangeley northbridge support
Change-Id: I13f2c46aa2bcedb9d1c66c485bf48ed7bc95d9c7
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/northbridge/intel/fsp_rangeley/acpi.c | 13 +++++++------
src/northbridge/intel/fsp_rangeley/chip.h | 2 +-
.../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 16 +++++++---------
.../intel/fsp_rangeley/fsp/chipset_fsp_util.h | 10 +++++-----
src/northbridge/intel/fsp_rangeley/northbridge.c | 17 +++++++++--------
src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +-
src/northbridge/intel/fsp_rangeley/port_access.c | 5 +++--
src/northbridge/intel/fsp_rangeley/raminit.c | 7 ++++---
src/northbridge/intel/fsp_rangeley/udelay.c | 4 ++--
9 files changed, 39 insertions(+), 37 deletions(-)
diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c
index 895f5b4..7be183e 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi.c
+++ b/src/northbridge/intel/fsp_rangeley/acpi.c
@@ -21,15 +21,16 @@
* MA 02110-1301 USA
*/
-#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <arch/io.h>
#include <arch/acpi.h>
+#include <arch/io.h>
+#include <build.h>
+#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <build.h>
+#include <string.h>
+#include <types.h>
+
#include "northbridge.h"
unsigned long acpi_fill_mcfg(unsigned long current)
@@ -56,7 +57,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
return current;
/* 256MB ECAM range */
- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28));
max_buses = 256;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h
index 24609a1..0d19aa7 100644
--- a/src/northbridge/intel/fsp_rangeley/chip.h
+++ b/src/northbridge/intel/fsp_rangeley/chip.h
@@ -60,4 +60,4 @@ struct northbridge_intel_fsp_rangeley_config {
uint8_t Bifurcation;
};
-#endif
+#endif /* _FSP_RANGELEY_CHIP_H_ */
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index bd196a5..ac45abf 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -17,25 +17,23 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <types.h>
-#include <string.h>
-#include <cpu/x86/stack.h>
-#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/stack.h>
#include <device/device.h>
-#include <southbridge/intel/fsp_rangeley/pci_devs.h>
#include <drivers/intel/fsp/fsp_util.h>
-#include <fspvpd.h>
#include <fspbootmode.h>
+#include <fspvpd.h>
+#include <string.h>
+#include <southbridge/intel/fsp_rangeley/pci_devs.h>
+#include <types.h>
#include <reset.h>
+
#include "../chip.h"
#ifdef __PRE_RAM__
#include <southbridge/intel/fsp_rangeley/romstage.h>
-#endif
-
-#ifdef __PRE_RAM__
/* Copy the default UPD region and settings to a buffer for modification */
static void GetUpdDefaultFromFsp
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h
index 3057865..09c4c38 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h
@@ -20,13 +20,13 @@
#ifndef CHIPSET_FSP_UTIL_H
#define CHIPSET_FSP_UTIL_H
-#include <fsptypes.h>
-#include <fspfv.h>
-#include <fspffs.h>
#include <fspapi.h>
+#include <fspffs.h>
+#include <fspfv.h>
+#include <fsphob.h>
#include <fspplatform.h>
+#include <fsptypes.h>
#include <fspinfoheader.h>
-#include <fsphob.h>
#include <fspvpd.h>
#define FSP_RESERVE_MEMORY_SIZE 0x200000
@@ -42,7 +42,7 @@
}
/*
- *The FSP Image ID is different for each platform's FSP and
+ * The FSP Image ID is different for each platform's FSP and
* can be used to verify that the right FSP binary is loaded.
* For the Rangeley FSP, the Image Id is "AVN-FSP0".
*/
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index 98c0b9c..397c53f 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -19,24 +19,25 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
-#include <stdint.h>
-#include <delay.h>
-#include <cpu/intel/fsp_model_406dx/model_406dx.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/fsp_model_406dx/model_406dx.h>
+#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <drivers/intel/fsp/fsp_util.h>
+#include <stdint.h>
#include <stdlib.h>
#include <string.h>
-#include <cpu/cpu.h>
-#include <cbmem.h>
+
#include "chip.h"
#include "northbridge.h"
-#include <drivers/intel/fsp/fsp_util.h>
-#include <cpu/x86/lapic.h>
static int bridge_revision_id = -1;
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h
index 855a056..6d40380 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.h
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.h
@@ -20,7 +20,7 @@
*/
#ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
-#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1
+#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS
diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c
index 508630e..83667f0 100644
--- a/src/northbridge/intel/fsp_rangeley/port_access.c
+++ b/src/northbridge/intel/fsp_rangeley/port_access.c
@@ -22,11 +22,12 @@
#define __PRE_RAM__ // Use simple device model for this file even in ramstage
#endif
-#include <stdint.h>
#include <arch/io.h>
+#include <cpu/x86/lapic.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
+#include <stdint.h>
+
#include "northbridge.h"
/*
diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c
index 3513c0f..3dbdfb9 100644
--- a/src/northbridge/intel/fsp_rangeley/raminit.c
+++ b/src/northbridge/intel/fsp_rangeley/raminit.c
@@ -18,13 +18,14 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
-#include <string.h>
#include <arch/io.h>
#include <cbmem.h>
+#include <console/console.h>
#include <device/pci_def.h>
-#include "northbridge.h"
#include <drivers/intel/fsp/fsp_util.h>
+#include <string.h>
+
+#include "northbridge.h"
unsigned long get_top_of_ram(void)
{
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c
index bdd9f78..a921609 100644
--- a/src/northbridge/intel/fsp_rangeley/udelay.c
+++ b/src/northbridge/intel/fsp_rangeley/udelay.c
@@ -17,10 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <delay.h>
-#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#include <delay.h>
+#include <stdint.h>
/**
* Intel Rangeley CPUs always run the TSC at BCLK=100MHz
More information about the coreboot-gerrit
mailing list