[coreboot-gerrit] New patch to review for coreboot: e16f315 Intel 945 boards: Use define for `BSM`

Paul Menzel (paulepanter@users.sourceforge.net) gerrit at coreboot.org
Thu Jun 5 08:52:55 CEST 2014


Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5929

-gerrit

commit e16f315d0615d0003eec5649f06b0716f75eb94c
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Thu Jun 5 08:50:17 2014 +0200

    Intel 945 boards: Use define for `BSM`
    
    Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/mainboard/getac/p470/romstage.c       | 2 +-
 src/mainboard/ibase/mb899/romstage.c      | 2 +-
 src/mainboard/intel/d945gclf/romstage.c   | 2 +-
 src/mainboard/kontron/986lcd-m/romstage.c | 2 +-
 src/mainboard/lenovo/t60/romstage.c       | 2 +-
 src/mainboard/lenovo/x60/i915.c           | 2 +-
 src/mainboard/lenovo/x60/romstage.c       | 2 +-
 src/mainboard/roda/rk886ex/romstage.c     | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index a081a8a..33b6726 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -347,7 +347,7 @@ void main(unsigned long bist)
 
 	{
 		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
 
 		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 418b6e4..9dfd364 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -298,7 +298,7 @@ void main(unsigned long bist)
 
 	{
 		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
 
 		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 69d4232..a0621ce 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -258,7 +258,7 @@ void main(unsigned long bist)
 
 	{
 		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
 
 		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 4acd734..0ad7a2a 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -410,7 +410,7 @@ void main(unsigned long bist)
 
 	{
 		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
 
 		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index dae917c..c5bb2f3 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -309,7 +309,7 @@ void main(unsigned long bist)
 
 	{
 		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
 
 		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index b41a0ba..8fbd2a1 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -138,7 +138,7 @@ int gtt_setup(unsigned int mmiobase)
 	PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
 	PGETBL_save |= PGETBL_ENABLED;
 
-	PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000;
+	PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
 	PGETBL_save |= 2; /* set GTT to 256kb */
 
 	write32(mmiobase + GFX_FLSH_CNTL, 0);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 1198fb2..1fed5f5 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -311,7 +311,7 @@ void main(unsigned long bist)
 
 	{
 		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c);
+		u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
 
 		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index ad323f5..2af294c 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -334,7 +334,7 @@ void main(unsigned long bist)
 
 	{
 		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
 
 		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);



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