[coreboot-gerrit] New patch to review for coreboot: ca3f202 lenovo/x60/i915.c: Mask BSM register correctly
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Thu Jun 5 22:52:27 CEST 2014
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5939
-gerrit
commit ca3f202edbea1b55b18473c2c3bab22228295c9d
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Thu Jun 5 22:27:24 2014 +0200
lenovo/x60/i915.c: Mask BSM register correctly
Base of Stolen Memory are (BSM) are bits 31:20.
This does make any difference as the bits 19:0 are read only and 0 by
default.
Change-Id: I82d087184a8550e95dca2ac2991ed48b06031536
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
src/mainboard/lenovo/x60/i915.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index 12bcf5c..9300b2b 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -137,7 +137,7 @@ int gtt_setup(unsigned int mmiobase)
pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
pgetbl_ctl |= PGETBL_ENABLED;
- pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
+ pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000;
pgetbl_ctl |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0);
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