[coreboot-gerrit] Patch set updated for coreboot: c7db8fc ibase/mb899: use defined GPIO's and add a define LPC_DEV PCI_DEV(0, 0x1f, 0)
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Jun 9 21:33:00 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5964
-gerrit
commit c7db8fc7538d352fb2f3285c6d5bbf2b4ee406a2
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Jun 9 21:21:22 2014 +0200
ibase/mb899: use defined GPIO's and add a define LPC_DEV PCI_DEV(0,0x1f,0)
Change-Id: I918a0a564519c7e74fad954612f41117404389d8
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/ibase/mb899/romstage.c | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 418b6e4..104a4c6 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -38,35 +38,36 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
#define DUMMY_DEV PNP_DEV(0x4e, 0)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
void setup_ich7_gpios(void)
{
printk(BIOS_DEBUG, " GPIOS...");
/* General Registers */
- outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
- outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
- outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ outl(0x1f1ff7c0, DEFAULT_GPIOBASE + GPIO_USE_SEL);
+ outl(0xe0e8efc3, DEFAULT_GPIOBASE + GP_IO_SEL);
+ outl(0xebffeeff, DEFAULT_GPIOBASE + GP_LVL);
/* Output Control Registers */
- outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
+ outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK);
/* Input Control Registers */
- outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
- outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
- outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
- outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
+ outl(0x00002180, DEFAULT_GPIOBASE + GPI_INV);
+ outl(0x000100ff, DEFAULT_GPIOBASE + GPIO_USE_SEL2);
+ outl(0x00000030, DEFAULT_GPIOBASE + GP_IO_SEL2);
+ outl(0x00010035, DEFAULT_GPIOBASE + GP_LVL);
}
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
// Set COM1/COM2 decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
// Enable COM1/COM2/KBD/SuperIO1+2
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
+ pci_write_config16(LPC_DEV, LPC_EN, 0x340b);
// Enable HWM at 0x290
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
+ pci_write_config32(LPC_DEV, 0x84, 0x00fc0291);
// io 0x300 decode
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
+ pci_write_config32(LPC_DEV, 0x90, 0x00000301);
}
/* This box has one superio
@@ -177,14 +178,14 @@ static void early_ich7_init(void)
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 = pci_read_config8(LPC_DEV, 0xa4);
reg8 &= ~(1 << 2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 = pci_read_config8(LPC_DEV, 0xad);
reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+ pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
reg32 |= (1 << 29) | (1 << 17);
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