[coreboot-gerrit] Patch set updated for coreboot: 8c140ff google/panther: Disable LPSS I2C controllers
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Mon Jun 16 17:42:43 CEST 2014
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5992
-gerrit
commit 8c140ff0f2b7e97efec08282728847d466a44b04
Author: Mohammed Habibulla <moch at chromium.org>
Date: Tue Oct 29 11:13:14 2013 -0700
google/panther: Disable LPSS I2C controllers
There is nothing attached to these devices so we can disable
them as well as the function 0 DMA controller.
Also remove the EC SMI/SCI mappings since there is no EC.
(panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174944
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Commit-Queue: Mohammed Habibulla <moch at chromium.org>
Tested-by: Mohammed Habibulla <moch at chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 95f1084..39d4f06 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -46,11 +46,9 @@ chip northbridge/intel/haswell
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
+ register "alt_gp_smi_en" = "0x0000"
register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_2" = "0x00000000"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
@@ -73,9 +71,9 @@ chip northbridge/intel/haswell
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
+ device pci 15.0 off end # Serial I/O DMA
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
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