[coreboot-gerrit] Patch set updated for coreboot: 14dd5a1 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147

-gerrit

commit 14dd5a174f175ec5384b982e90bcac4eacba9317
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat Jun 28 15:36:57 2014 +1000

    southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
    
    First brought to attention by Clang:
    
    Correct mask to select bits 4-6 inclusively as per comment and use
    bitwise operations while working with bits. Be sure to write back out
    the data on the retrain.
    
    Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/southbridge/amd/rs690/cmn.c | 9 ++++-----
 src/southbridge/amd/rs780/cmn.c | 9 ++++-----
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c
index 36870b3..bd3ee63 100644
--- a/src/southbridge/amd/rs690/cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
@@ -286,13 +286,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
 				/* set bit8=1, bit0-2=bit4-6 */
 				u32 tmp;
-				reg =
-				    nbpcie_p_read_index(dev,
-							PCIE_LC_LINK_WIDTH);
-				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
+				tmp = (reg >> 4) & 0x07;	/* get bit4-6 */
 				reg &= 0xfff8;	/* clear bit0-2 */
-				reg += tmp;	/* merge */
+				reg |= tmp;	/* merge */
 				reg |= 1 << 8;
+				nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
 				count++;	/* CIM said "keep in loop"?  */
 			} else {
 				res = 1;
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index cf09b9a..eb3b025 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -327,13 +327,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
 				/* set bit8=1, bit0-2=bit4-6 */
 				u32 tmp;
-				reg =
-				    nbpcie_p_read_index(dev,
-							PCIE_LC_LINK_WIDTH);
-				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
+				tmp = (reg >> 4) & 0x07;	/* get bit4-6 */
 				reg &= 0xfff8;	/* clear bit0-2 */
-				reg += tmp;	/* merge */
+				reg |= tmp;	/* merge */
 				reg |= 1 << 8;
+				nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
 				count++;	/* CIM said "keep in loop"?  */
 			} else {
 				res = 1;