[coreboot-gerrit] Patch set updated for coreboot: d0fcc23 drivers/hwm: Add a generic hwm driver.

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Tue Mar 18 11:08:44 CET 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5385

-gerrit

commit d0fcc23897cbc4b4823500638a7e5fa80167a32e
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Fri Mar 14 01:06:22 2014 +1100

    drivers/hwm: Add a generic hwm driver.
    
    Make generic, testing with Fintek Super I/O....
    currently wired in to fintek superio, need to move arary of
    values to mainboard.c??
    
    Change-Id: Ic7bdea55907e379aad9e74b87b514e8038ef9fd0
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/drivers/Kconfig                       |   1 +
 src/drivers/Makefile.inc                  |   1 +
 src/drivers/hwm/Kconfig                   |   6 ++
 src/drivers/hwm/Makefile.inc              |  20 +++++
 src/drivers/hwm/superio_hwm.c             | 142 ++++++++++++++++++++++++++++++
 src/include/hwm/superio_hwm.h             |  32 +++++++
 src/mainboard/jetway/nf81-t56n-lf/Kconfig |   4 +
 src/superio/fintek/f71869ad/chip.h        |   1 +
 src/superio/fintek/f71869ad/superio.c     |   5 +-
 9 files changed, 211 insertions(+), 1 deletion(-)

diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 5267ff8..c09e57f 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -22,6 +22,7 @@ source src/drivers/dec/Kconfig
 source src/drivers/elog/Kconfig
 source src/drivers/emulation/Kconfig
 source src/drivers/generic/Kconfig
+source src/drivers/hwm/Kconfig
 source src/drivers/i2c/Kconfig
 source src/drivers/ics/Kconfig
 source src/drivers/intel/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index 197a900..4b944cb 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -39,3 +39,4 @@ subdirs-y += ipmi
 subdirs-y += elog
 subdirs-y += xpowers
 subdirs-$(CONFIG_ARCH_X86) += pc80
+subdirs-$(CONFIG_ARCH_X86) += hwm
diff --git a/src/drivers/hwm/Kconfig b/src/drivers/hwm/Kconfig
new file mode 100644
index 0000000..dc60fd7
--- /dev/null
+++ b/src/drivers/hwm/Kconfig
@@ -0,0 +1,6 @@
+config DRIVERS_SUPERIO_HWM
+	bool "Super I/O HWM"
+	default n
+	help
+	  Just enough of a driver to make coreboot control system fans.
+	  No configuration is necessary for the OS to pick up the device.
diff --git a/src/drivers/hwm/Makefile.inc b/src/drivers/hwm/Makefile.inc
new file mode 100644
index 0000000..ccb6de0
--- /dev/null
+++ b/src/drivers/hwm/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_DRIVERS_SUPERIO_HWM) += superio_hwm.c
diff --git a/src/drivers/hwm/superio_hwm.c b/src/drivers/hwm/superio_hwm.c
new file mode 100644
index 0000000..49bc90f
--- /dev/null
+++ b/src/drivers/hwm/superio_hwm.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This code should work for all Fintek Super I/O HWM's. */
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+#include <hwm/superio_hwm.h>
+
+/* Helper functions */
+static void write_index(u16 port, u8 reg, u8 value)
+{
+	outb(reg, port);
+	outb(value, port + 1);
+}
+
+static u8 read_index(u16 port, u8 reg)
+{
+	outb(reg, port);
+	return inb(port + 1);
+}
+/* .. */
+
+/* Initialize F71869AD hardware monitor registers, which are at 0x225. */
+/* XXX: make configurable.. */
+static void init_registers(u16 base)
+{
+	u8 reg, value;
+	int i;
+
+	/* XXX: work out correct values??? */
+	u8 hwm_reg_values[] = {
+	/*  reg   mask  data */
+		0x0a, 0x00, 0x02, /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */
+		0x08, 0x00, 0x98, /* SMBus Address p.53 */
+		0xe9, 0x00, 0xff, /* SMB Data Buff 9 ??? */
+		0xed, 0x00, 0x01, /* SMB/TSI Command Byte p.83 */
+		0xee, 0x00, 0xc0, /* SMB_Status p.83 */
+		0xef, 0x00, 0x02, /* SMB_Protocal p.83 */
+		/* Tfan1 = Tnow + (Ta - Tb)*Ct where, */
+		0xaf, 0x00, 0x8c, /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */
+		0x9f, 0x00, 0x8a, /* set FAN_PROG_SEL = 1 */
+		0x94, 0x00, 0x00, /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */
+		0x96, 0x00, 0x07, /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */
+		0x95, 0x00, 0x22, /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/2 up & down) in 0x95 when FAN_PROG_SEL = 1, p.65-66 */
+		0x9f, 0x00, 0x0a, /* set FAN_PROG_SEL = 0 */
+        /* .. */
+		0x02, 0x00, 0x30, /* OVT_MODE p.52 */
+		0x63, 0x00, 0x20, /* Temperature BEEP Enable Register p.58 */
+		0x66, 0x00, 0x02, /* OVT and Alert Output Enable Register 1 p.59 */
+		0x82, 0x00, 0x76, /* Temperature sensors 1 OVT limit p.61 */
+		0x91, 0x00, 0x07, /* FAN Interrupt Status Register p.63 */
+		0xa3, 0x00, 0x0e, /* FAN1 RPM mode p.70 */
+		0xa9, 0x00, 0x14, /* VT1 Boundary 2 Temperature p.71 */
+		0xaa, 0x00, 0xff, /* FAN1 Segment 1 Speed Count */
+		0xab, 0x00, 0x0e, /* FAN1 Segment 2 Speed Count */
+		0xae, 0x00, 0x07, /* FAN1 Segment 3 Speed Count */
+	};
+
+	for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
+		reg = hwm_reg_values[i];
+		value = read_index(base, reg);
+		value &= 0xff & hwm_reg_values[i + 1];
+		value |= 0xff & hwm_reg_values[i + 2];
+		printk(BIOS_DEBUG, "Super I/O HWM: base = 0x%04x, reg = 0x%02x, "
+		       "value = 0x%02x\n", base, reg, value);
+		write_index(base, reg, value);
+		value = read_index(base, reg);
+		printk(BIOS_DEBUG, "Super I/O HWM (read back): base = 0x%04x, reg = 0x%02x, "
+		       "value = 0x%02x\n", base, reg, value);
+	}
+}
+/* .. */
+
+/* Main driver */
+void hwm_init(device_t dev)
+{
+	if (!CONFIG_DRIVERS_SUPERIO_HWM)
+		return;
+
+	/* return if hwm is disabled in devicetree.cb */
+	struct drivers_superio_hwm_config *config = dev->chip_info;
+	if (!dev->enabled || !config)
+		return;
+
+	u32 hwm_base = config->base;
+
+	printk(BIOS_DEBUG, "Super I/O HWM: Initializing Hardware Monitor at pnp %04x\n"
+		, hwm_base);
+
+	struct resource *res = find_resource(dev, PNP_IDX_IO0);
+	if (!res) {
+		printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "Super I/O HWM: Base Address at 0x%x\n", (u32)res->base);
+	printk(BIOS_WARNING, "Super I/O HWM: Configuring registers...\n");
+	init_registers(res->base);
+}
+
+/*
+static void hwm_noop(device_t dummy)
+{
+}
+
+static struct device_operations hwm_ops = {
+	.read_resources = hwm_noop,
+	.set_resources = hwm_noop,
+	.enable_resources = hwm_noop,
+	.init = hwm_init,
+};
+
+static void enable_dev(device_t dev)
+{
+	dev->ops = &hwm_ops;
+}
+
+struct chip_operations hwm_fintek_ops = {
+	CHIP_NAME("Super I/O Hardware Monitor.")
+	.enable_dev = enable_dev
+};
+*/
diff --git a/src/include/hwm/superio_hwm.h b/src/include/hwm/superio_hwm.h
new file mode 100644
index 0000000..49e431c
--- /dev/null
+++ b/src/include/hwm/superio_hwm.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014  Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef DRIVERS_SUPERIO_HWM_H
+#define DRIVERS_SUPERIO_HWM_H
+
+#include <device/device.h>
+
+/* Initialization parameters?? */
+typedef struct drivers_superio_hwm_config {
+	u32 base;
+} hwm_config_t;
+
+void hwm_init(device_t dev);
+
+#endif /* DRIVERS_SUPERIO_HWM_H */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index 2d0272f..dd0b528 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -114,4 +114,8 @@ config DRIVERS_PS2_KEYBOARD
 	bool
 	default y
 
+config DRIVERS_SUPERIO_HWM
+	bool
+	default y
+
 endif # BOARD_JETWAY_NF81_T56N_LF
diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h
index 5b18c33..fe5be17 100644
--- a/src/superio/fintek/f71869ad/chip.h
+++ b/src/superio/fintek/f71869ad/chip.h
@@ -21,6 +21,7 @@
 #ifndef SUPERIO_FINTEK_F71869AD_CHIP_H
 #define SUPERIO_FINTEK_F71869AD_CHIP_H
 
+#include <hwm/superio_hwm.h>
 #include <pc80/keyboard.h>
 #include <device/device.h>
 
diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c
index dbcb812..3c2a303 100644
--- a/src/superio/fintek/f71869ad/superio.c
+++ b/src/superio/fintek/f71869ad/superio.c
@@ -37,6 +37,9 @@ static void f71869ad_init(device_t dev)
 
 	switch(dev->path.pnp.device) {
 	/* TODO: Might potentially need code for HWM or FDC etc. */
+	case F71869AD_HWM:
+		hwm_init(dev);
+		break;
 	case F71869AD_KBC:
 		pc_keyboard_init(&conf->keyboard);
 		break;
@@ -109,7 +112,7 @@ static struct pnp_info pnp_dev_info[] = {
 	{ &ops, F71869AD_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, F71869AD_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, F71869AD_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
-	{ &ops, F71869AD_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, F71869AD_HWM,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, F71869AD_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
 	{ &ops, F71869AD_GPIO, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, F71869AD_BSEL,  PNP_IO0, {0x07f8, 0}, },



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