[coreboot-gerrit] Patch set updated for coreboot: 5ff0af2 jetway/nf81-t56n-lf: Remove random GPIO driving for PCI-e resets
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed May 7 12:32:48 CEST 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5684
-gerrit
commit 5ff0af29fcf44875e8202478379028ad4f290fe5
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue May 6 16:30:25 2014 +0300
jetway/nf81-t56n-lf: Remove random GPIO driving for PCI-e resets
These reset signals were copied as-is from AMD persimmon.
Power-on defaults are safer than randomly picked GPIOs configured
as outputs, but even the GPIO input/output configurations for
this board have not been verified.
Change-Id: Ia95a8e6cef44cfc2eaa0ebdfdf75a7709dd6e9f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 48 +-----------------------
1 file changed, 1 insertion(+), 47 deletions(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index f4b8586..9dc0513 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -35,7 +35,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
{AGESA_READ_SPD, BiosReadSpd },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
- {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset },
+ {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported },
{AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit },
{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
@@ -73,49 +73,3 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
return AGESA_SUCCESS;
}
-
-/* PCIE slot reset control */
-AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
-{
- AGESA_STATUS Status;
- uint32_t FcnData;
- PCIe_SLOT_RESET_INFO *ResetInfo;
-
- uint32_t GpioMmioAddr;
- uint32_t AcpiMmioAddr;
- uint8_t Data8;
- uint16_t Data16;
-
- FcnData = Data;
- ResetInfo = ConfigPtr;
- /* Get SB800 MMIO Base (AcpiMmioAddr) */
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16=Data8<<8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16|=Data8;
- AcpiMmioAddr = (uint32_t)Data16 << 16;
- Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- switch (ResetInfo->ResetId)
- {
- case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */
- switch (ResetInfo->ResetControl) {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
- Data8 &= ~(uint8_t)BIT6 ;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
- Data8 |= BIT6 ;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- }
- return Status;
-}
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