[coreboot-gerrit] Patch merged into coreboot/master: dd2e8c3 superio/fintek/f71869ad: Configure multi-func reg in devicetree
gerrit at coreboot.org
gerrit at coreboot.org
Thu May 8 12:10:41 CEST 2014
the following patch was just integrated into master:
commit dd2e8c35fb368316b51d969d046696a017f09d25
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Thu Apr 24 02:58:11 2014 +1000
superio/fintek/f71869ad: Configure multi-func reg in devicetree
Facilitate for the configuration of so called "Multi-function Select
Registers" with devicetree.cb in ramstage.
Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to
correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI
mode. This allows the Fintek to correctly talk to the Southbridge over
the SMBus for CPU temperature data as to control fans and so on.
Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5576
Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/5576 for details.
-gerrit
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