[coreboot-gerrit] Patch merged into coreboot/master: 2dd3f87 cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
gerrit at coreboot.org
gerrit at coreboot.org
Fri May 9 21:36:15 CEST 2014
the following patch was just integrated into master:
commit 2dd3f877cc7926f5ac1cfd5a7e5d546c8be2121c
Author: Martin Roth <gaumless at gmail.com>
Date: Fri Apr 25 15:09:27 2014 -0600
cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
CPU - fsp_model_206ax:
- Remove Kconfig options and mark this as using the FSP.
- Use shared FSP cache_as_ram.inc file
Mainboard - intel/cougar_canyon2:
- Update to use the shared FSP header file.
- Modify to call copy_and_run() directly instead of returning to
cache_as_ram.inc.
Northbridge - fsp_sandybridge:
- remove mrccache, fsp_util.[ch]
- add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
- Update to use the shared FSP header file.
These changes were validated with FSP:
CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
MD5: 24965382fbb832f7b184d3f24157abda
Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
Signed-off-by: Martin Roth <gaumless at gmail.com>
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
Reviewed-on: http://review.coreboot.org/5636
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones at se-eng.com>
See http://review.coreboot.org/5636 for details.
-gerrit
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