[coreboot-gerrit] Patch merged into coreboot/master: 19edc3a baytrail: clear the pmc wake status registers
gerrit at coreboot.org
gerrit at coreboot.org
Tue May 13 16:11:27 CEST 2014
the following patch was just integrated into master:
commit 19edc3a2e53eb54994a99ca8a868480badcbf227
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Jan 9 11:17:37 2014 -0600
baytrail: clear the pmc wake status registers
The PMC in baytrail maintains an additional set
wake status in memory-mapped registers. If these
bits aren't cleared the device won't be able to
go to S5 or S3 without being immediately woken up.
Therefore clear these registers.
BUG=chrome-os-partner:24913
BRANCH=rambi,squawks
TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work
correctly.
Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181984
Reviewed-on: http://review.coreboot.org/5034
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
See http://review.coreboot.org/5034 for details.
-gerrit
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