[coreboot-gerrit] New patch to review for coreboot: 0771ebd earlymtrr: Determine CPU_ADDR_BITS dynamically
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sun Nov 16 21:07:56 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7482
-gerrit
commit 0771ebd5f388fd512714a224955da35a61731e9f
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sun Nov 16 20:09:50 2014 +0100
earlymtrr: Determine CPU_ADDR_BITS dynamically
Change-Id: Ic5cbd509e45df8d3bbecd8b0e75219c8bb926c02
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/arch/x86/lib/Makefile.inc | 1 +
src/arch/x86/lib/cpu.c | 20 --------------------
src/arch/x86/lib/cpu_addr_size.c | 26 ++++++++++++++++++++++++++
src/cpu/x86/mtrr/earlymtrr.c | 4 +++-
4 files changed, 30 insertions(+), 21 deletions(-)
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 22306f1..5c2302d 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -13,6 +13,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
ramstage-y += c_start.S
ramstage-y += cpu.c
+ramstage-y += cpu_addr_size.c
ramstage-y += pci_ops_conf1.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
ramstage-y += exception.c
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 86b5cb0..f7a8d73 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -130,26 +130,6 @@ static const char *cpu_vendor_name(int vendor)
return name;
}
-static int cpu_cpuid_extended_level(void)
-{
- return cpuid_eax(0x80000000);
-}
-
-#define CPUID_FEATURE_PAE (1 << 6)
-#define CPUID_FEATURE_PSE36 (1 << 17)
-
-int cpu_phys_address_size(void)
-{
- if (!(cpu_have_cpuid()))
- return 32;
-
- if (cpu_cpuid_extended_level() >= 0x80000008)
- return cpuid_eax(0x80000008) & 0xff;
-
- if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
- return 36;
- return 32;
-}
static void identify_cpu(struct device *cpu)
{
char vendor_name[16];
diff --git a/src/arch/x86/lib/cpu_addr_size.c b/src/arch/x86/lib/cpu_addr_size.c
new file mode 100644
index 0000000..ca65fdd
--- /dev/null
+++ b/src/arch/x86/lib/cpu_addr_size.c
@@ -0,0 +1,26 @@
+#include <cpu/cpu.h>
+#include <arch/cpu.h>
+
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+static int cpu_cpuid_extended_level(void)
+{
+ return cpuid_eax(0x80000000);
+}
+
+#ifdef __ROMCC__
+static
+#endif
+int cpu_phys_address_size(void)
+{
+ if (!(cpu_have_cpuid()))
+ return 32;
+
+ if (cpu_cpuid_extended_level() >= 0x80000008)
+ return cpuid_eax(0x80000008) & 0xff;
+
+ if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+ return 36;
+ return 32;
+}
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 0471a9e..7bd33ed 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -2,6 +2,8 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
+#include <arch/x86/lib/cpu_addr_size.c>
+
#ifdef __ROMCC__
static
#endif
@@ -15,7 +17,7 @@ void set_var_mtrr(
basem.hi = 0;
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.lo = ~(size - 1) | MTRRphysMaskValid;
- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+ maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
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