[coreboot-gerrit] Patch set updated for coreboot: 44e2ee6 fsp_baytrail: remove register option for TSEG size
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Mon Nov 17 05:53:27 CET 2014
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7490
-gerrit
commit 44e2ee618ca203514b989972629b5d1e896fc5eb
Author: Martin Roth <martin.roth at se-eng.com>
Date: Sun Nov 16 20:28:57 2014 -0700
fsp_baytrail: remove register option for TSEG size
Set the UPD entry based on the Kconfig value instead of having two
separate places that the value needs to be set.
Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/mainboard/intel/bayleybay_fsp/devicetree.cb | 1 -
src/mainboard/intel/minnowmax/devicetree.cb | 1 -
src/soc/intel/fsp_baytrail/chip.h | 14 --------------
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 4 ++--
4 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index a19a676..521fd12 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -27,7 +27,6 @@ chip soc/intel/fsp_baytrail
register "PcdSataMode" = "SATA_MODE_AHCI"
register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
- register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB"
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb
index dd999a0..fd2431c 100644
--- a/src/mainboard/intel/minnowmax/devicetree.cb
+++ b/src/mainboard/intel/minnowmax/devicetree.cb
@@ -27,7 +27,6 @@ chip soc/intel/fsp_baytrail
register "PcdSataMode" = "SATA_MODE_AHCI"
register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
- register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB"
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
index b2723c3..2bffe18 100644
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -51,20 +51,6 @@ struct soc_intel_fsp_baytrail_config {
#define SATA_MODE_AHCI INCREMENT_FOR_DEFAULT(0)
/*
- * MrcInitTsegSize
- * 0x01, "1 MB"
- * 0x02, "2 MB"
- * 0x04, "4 MB"
- * 0x08, "8 MB"
- */
- uint16_t PcdMrcInitTsegSize;
- #define TSEG_SIZE_DEFAULT UPD_DEFAULT
- #define TSEG_SIZE_1_MB INCREMENT_FOR_DEFAULT(1)
- #define TSEG_SIZE_2_MB INCREMENT_FOR_DEFAULT(2)
- #define TSEG_SIZE_4_MB INCREMENT_FOR_DEFAULT(4)
- #define TSEG_SIZE_8_MB INCREMENT_FOR_DEFAULT(8)
-
- /*
* MrcInitMmioSize
* 0x400, "1.0 GB"s
* 0x600, "1.5 GB"
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index ed42201..f3a9461 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -32,6 +32,7 @@
#include <baytrail/pmc.h>
#include <baytrail/acpi.h>
#include <baytrail/iomap.h>
+#include <baytrail/smm.h>
#ifdef __PRE_RAM__
#include <baytrail/romstage.h>
@@ -96,8 +97,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
(config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE))
UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode;
- if (config->PcdMrcInitTsegSize != TSEG_SIZE_DEFAULT)
- UpdData->PcdMrcInitTsegSize = config->PcdMrcInitTsegSize;
+ UpdData->PcdMrcInitTsegSize = smm_region_size() >> 20;
printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize);
printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize);
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