[coreboot-gerrit] New patch to review for coreboot: 74d7d00 Added fix for SMM/SMI

[kayalvizhi dhandapani (kayalvizhid@ami.com)]

kayalvizhi dhandapani (kayalvizhid at ami.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7022

-gerrit

commit 74d7d0042f056717088ea1348f1e04a29bca3de6
Author: kayalvizhid <kayalvizhid at ami.com>
Date:   Mon Oct 6 11:59:02 2014 -0400

    Added fix for SMM/SMI
    
    When enabled SMM, the boot stopped while patching up global NVS in DSDT.
    Noticed both CPUs were assigned the same SMBASE address.
    Updated cpu_smm_do_relocation() function so that every cpu get different SMBASE address
    Added other minor fix to fix the errors 1.unknown type error for "device_t" &
    2.implicit declaration of funtion "southcluster_smm_save_gpio_route".
    [TESTED]Tested on intel bayleybay CRB. The SMI works with the above fixes.
    
    Change-Id: Ia414678cffd27bef3caac6761a576bbba46a0e51
    Signed-off-by: kayalvizhi dhandapani <kayalvizhid at ami.com>
---
 src/mainboard/intel/bayleybay_fsp/devicetree.cb |  2 +-
 src/soc/intel/fsp_baytrail/cpu.c                | 10 ++++++++--
 src/soc/intel/fsp_baytrail/gpio.c               |  1 +
 src/soc/intel/fsp_baytrail/tsc_freq.c           | 10 +++++-----
 4 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index befd3dc..356c8df 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail
 	register "SataMode"             = "SATA_MODE_AHCI"
 	register "MrcInitSPDAddr1"      = "SPD_ADDR_DEFAULT"
 	register "MrcInitSPDAddr2"      = "SPD_ADDR_DEFAULT"
-	register "MrcInitTsegSize"      = "TSEG_SIZE_DEFAULT"
+	register "MrcInitTsegSize"      = "TSEG_SIZE_8_MB"
 	register "MrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"
 	register "eMMCBootMode"         = "EMMC_FOLLOWS_DEVICETREE"
 	register "IgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index f260880..6f1e9c4 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -148,14 +148,20 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params)
 		runtime->apic_id_to_cpu[i] = mp_get_apic_id(i);
 }
 
-static void asmlinkage
-cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime)
+static void asmlinkage cpu_smm_do_relocation(void *arg)
 {
 #ifndef CONFIG_MAX_CPUS
 #error CONFIG_MAX_CPUS must be set.
 #endif
 	msr_t smrr;
 	em64t100_smm_state_save_area_t *smm_state;
+        const struct smm_module_params *p;
+        const struct smm_runtime *runtime;
+        int cpu;
+
+        p = arg;
+        runtime = p->runtime;
+        cpu = p->cpu;
 
 	if (cpu >= CONFIG_MAX_CPUS) {
 		printk(BIOS_CRIT,
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index 69e9ac6..c12c937 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -21,6 +21,7 @@
 #include <console/console.h>
 #include <baytrail/gpio.h>
 #include <baytrail/pmc.h>
+#include <baytrail/smm.h>
 
 /* GPIO-to-Pad LUTs */
 static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c
index b74e41e..da7e965 100644
--- a/src/soc/intel/fsp_baytrail/tsc_freq.c
+++ b/src/soc/intel/fsp_baytrail/tsc_freq.c
@@ -21,11 +21,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
 #include <baytrail/msr.h>
-#if !defined(__PRE_RAM__)
-#include <baytrail/ramstage.h>
-#else
-#include <baytrail/romstage.h>
-#endif
 
 unsigned bus_freq_khz(void)
 {
@@ -57,6 +52,11 @@ unsigned long tsc_freq_mhz(void)
 }
 
 #if !defined(__SMM__)
+#if !defined(__PRE_RAM__)
+#include <baytrail/ramstage.h>
+#else
+#include <baytrail/romstage.h>
+#endif
 
 void set_max_freq(void)
 {