[coreboot-gerrit] New patch to review for coreboot: 3062a56 baytrail: Add padding to the end of device_nvs to match ACPI

[Scott Radcliffe (sradcliffe@microind.com)]

Scott Radcliffe (sradcliffe at microind.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7039

-gerrit

commit 3062a5611721d53e4a2f0f7490d4158b2bfdd210
Author: Scott Radcliffe <sradcliffe at microind.com>
Date:   Fri Oct 10 16:15:01 2014 -0400

    baytrail: Add padding to the end of device_nvs to match ACPI
    
    ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000.
    To reserve the full 0x2000 bytes for gnvs usage, padding must be
    added to the device_nvs struct.
    
    Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac
    Signed-off-by: Scott Radcliffe <sradcliffe at microind.com>
---
 src/soc/intel/baytrail/baytrail/device_nvs.h     | 3 ++-
 src/soc/intel/fsp_baytrail/baytrail/device_nvs.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h
index f8f831b..4e175a0 100644
--- a/src/soc/intel/baytrail/baytrail/device_nvs.h
+++ b/src/soc/intel/baytrail/baytrail/device_nvs.h
@@ -55,13 +55,14 @@ typedef struct {
 	u32	scc_bar0[3];
 	u32	lpe_bar0;
 
-	/* BAR 0 */
+	/* BAR 1 */
 	u32	lpss_bar1[14];
 	u32	scc_bar1[3];
 	u32	lpe_bar1;
 
 	/* Extra */
 	u32	lpe_fw; /* LPE Firmware */
+	u8  rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
 } __attribute__((packed)) device_nvs_t;
 
 #endif
diff --git a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h
index a06ca70..4e175a0 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h
@@ -62,6 +62,7 @@ typedef struct {
 
 	/* Extra */
 	u32	lpe_fw; /* LPE Firmware */
+	u8  rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
 } __attribute__((packed)) device_nvs_t;
 
 #endif