[coreboot-gerrit] Patch set updated for coreboot: 869df7d bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Wed Oct 15 20:18:37 CEST 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6921
-gerrit
commit 869df7de69095a8a276c1598eba00ed02ba0a54a
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Fri Sep 5 16:29:41 2014 +0200
bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.
Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/google/butterfly/romstage.c | 21 +------------------
src/mainboard/google/link/romstage.c | 22 ++------------------
src/mainboard/google/parrot/romstage.c | 21 +------------------
src/mainboard/google/stout/romstage.c | 21 +------------------
src/mainboard/intel/emeraldlake2/romstage.c | 21 +------------------
src/mainboard/kontron/ktqm77/romstage.c | 21 +------------------
src/mainboard/lenovo/t520/romstage.c | 21 +------------------
src/mainboard/lenovo/t530/romstage.c | 21 +------------------
src/mainboard/lenovo/x220/romstage.c | 21 +------------------
src/mainboard/lenovo/x230/romstage.c | 21 +------------------
src/mainboard/samsung/lumpy/romstage.c | 21 +------------------
src/mainboard/samsung/stumpy/romstage.c | 21 +------------------
src/southbridge/intel/bd82x6x/early_pch.c | 31 +++++++++++++++++++++++++++++
src/southbridge/intel/bd82x6x/pch.h | 1 +
14 files changed, 45 insertions(+), 240 deletions(-)
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 03d499d..908b6d8 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -117,8 +117,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
struct pei_data pei_data = {
pei_version: PEI_VERSION,
@@ -202,24 +200,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index ca58262..8236e20 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -155,8 +155,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
@@ -239,24 +237,8 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- } else {
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
+ if (boot_mode == 0) {
/* This is the fastest way to let users know
* the Intel CPU is now alive.
*/
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 667d639..ce42b41 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -118,8 +118,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
@@ -202,24 +200,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 7ac5297..bfa4af7 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -159,8 +159,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
struct pei_data pei_data = {
pei_version: PEI_VERSION,
@@ -249,24 +247,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
/* Do ec reset as early as possible, but skip it on S3 resume */
if (boot_mode < 2)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index c9c2b1d..220b1d7 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -167,8 +167,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
@@ -250,24 +248,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 5053530..401314c 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -164,8 +164,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
@@ -262,24 +260,7 @@ void main(unsigned long bist)
pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) |
DEVEN_PEG10);
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 8fc0f5f..a0cbad5 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -114,8 +114,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
if (MCHBAR16(SSKPD) == 0xCAFE) {
outb(0x6, 0xcf9);
@@ -196,24 +194,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index d95f10a..c2f0a4b 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -152,8 +152,6 @@ static void init_usb(void)
void main(unsigned long bist)
{
int s3resume = 0;
- u32 pm1_cnt;
- u16 pm1_sts;
spd_raw_data spd[4];
if (MCHBAR16(SSKPD) == 0xCAFE) {
@@ -200,24 +198,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 59563f9..b989ecb 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -151,8 +151,6 @@ init_usb (void)
void main(unsigned long bist)
{
int s3resume = 0;
- u32 pm1_cnt;
- u16 pm1_sts;
spd_raw_data spd[4];
if (MCHBAR16(SSKPD) == 0xCAFE) {
@@ -198,24 +196,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 1a96ab2..16a17c2 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -152,8 +152,6 @@ init_usb (void)
void main(unsigned long bist)
{
int s3resume = 0;
- u32 pm1_cnt;
- u16 pm1_sts;
spd_raw_data spd[4];
if (MCHBAR16(SSKPD) == 0xCAFE) {
@@ -189,24 +187,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 20fcaee..dc4161d 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -137,8 +137,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
struct pei_data pei_data = {
pei_version: PEI_VERSION,
@@ -225,24 +223,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 2166d6e..625903d 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -177,8 +177,6 @@ void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
- u32 pm1_cnt;
- u16 pm1_sts;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
@@ -265,24 +263,7 @@ void main(unsigned long bist)
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
- /* Check PM1_STS[15] to see if we are waking from Sx */
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
- /* Read PM1_CNT[12:10] to determine which Sx state */
- pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
- if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 9f80d41..3438a0a 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -20,6 +20,9 @@
#include <arch/io.h>
#include <timestamp.h>
+#include "pch.h"
+#include <arch/acpi.h>
+#include <console/console.h>
#if CONFIG_COLLECT_TIMESTAMPS
tsc_t get_initial_timestamp(void)
@@ -31,3 +34,31 @@ tsc_t get_initial_timestamp(void)
return base_time;
}
#endif
+
+
+int southbridge_detect_s3_resume(void)
+{
+ u32 pm1_cnt;
+ u16 pm1_sts;
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+ if (acpi_s3_resume_allowed()) {
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+ return 1;
+ } else {
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+ }
+ }
+
+ return 0;
+}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 83128e2..aabf617 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -76,6 +76,7 @@ int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
void early_thermal_init(void);
void early_pch_init_native(void);
+int southbridge_detect_s3_resume(void);
#endif
#endif
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