[coreboot-gerrit] Patch set updated for coreboot: 4063fa9 mc146818: Change read_option to use cmos_layout.bin
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Thu Oct 16 16:52:11 CEST 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7075
-gerrit
commit 4063fa959bbde35b85781612e4242d5146f39a38
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sun Jan 26 23:47:03 2014 +0100
mc146818: Change read_option to use cmos_layout.bin
To simplify updating existing image.
Change-Id: Ifc01c57454dd8fee8c1eff510dbc06fe818af555
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/drivers/pc80/mc146818rtc_early.c | 40 +++++++++++++++++++++++++++++++----
src/include/boot/coreboot_tables.h | 19 +++++++++++++++++
src/include/pc80/mc146818rtc.h | 8 +++----
src/northbridge/intel/e7520/raminit.c | 5 -----
src/northbridge/intel/e7525/raminit.c | 5 -----
5 files changed, 59 insertions(+), 18 deletions(-)
diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c
index 145fe21..6ca54b9 100644
--- a/src/drivers/pc80/mc146818rtc_early.c
+++ b/src/drivers/pc80/mc146818rtc_early.c
@@ -1,6 +1,13 @@
#include <stdint.h>
#include <pc80/mc146818rtc.h>
#include <fallback.h>
+#ifdef __ROMCC__
+#include <arch/cbfs.h>
+#else
+#include <cbfs.h>
+#endif
+#include <boot/coreboot_tables.h>
+
#if CONFIG_USE_OPTION_TABLE
#include "option_table.h"
#endif
@@ -92,12 +99,37 @@ static inline __attribute__((unused)) int do_normal_boot(void)
return (byte & (1<<1));
}
-unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
+unsigned read_option_real(const char *name, unsigned def)
{
#if CONFIG_USE_OPTION_TABLE
- unsigned byte;
- byte = cmos_read(start/8);
- return (byte >> (start & 7U)) & ((1U << size) - 1U);
+ struct cmos_option_table *ct;
+ struct cmos_entries *ce;
+
+#ifdef __ROMCC__
+ ct = (struct cmos_option_table *)walkcbfs("cmos_layout.bin");
+#else
+ ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin",
+ CBFS_COMPONENT_CMOS_LAYOUT, NULL);
+#endif
+
+ if (!ct)
+ return def;
+
+ ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
+ for(;ce->tag==LB_TAG_OPTION;
+ ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+ unsigned byte;
+ unsigned i;
+ for (i = 0; name[i] && i < CMOS_MAX_NAME_LENGTH; i++)
+ if (name[i] != ce->name[i])
+ goto next_option;
+ byte = cmos_read(ce->bit/8);
+ byte >>= (ce->bit & 7U);
+
+ return (byte) & ((1U << ce->length) - 1U);
+ next_option:;
+ }
+ return def;
#else
return def;
#endif
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index db3c508..3b611e0 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -43,6 +43,7 @@
* See also: util/lbtdump/lbtdump.c
*/
+#ifndef __ROMCC__
struct lb_uint64 {
uint32_t lo;
uint32_t hi;
@@ -64,6 +65,8 @@ static inline struct lb_uint64 pack_lb64(uint64_t value)
return result;
}
+#endif
+
struct lb_header
{
uint8_t signature[4]; /* LBIO */
@@ -89,6 +92,8 @@ struct lb_record {
#define LB_TAG_MEMORY 0x0001
+#ifndef __ROMCC__
+
struct lb_memory_range {
struct lb_uint64 start;
struct lb_uint64 size;
@@ -115,6 +120,8 @@ struct lb_hwrpb {
uint64_t hwrpb;
};
+#endif
+
#define LB_TAG_MAINBOARD 0x0003
struct lb_mainboard {
uint32_t tag;
@@ -168,6 +175,8 @@ struct lb_console {
#define LB_TAG_CONSOLE_EHCI 5
#define LB_TAG_CONSOLE_SERIAL8250MEM 6
+#ifndef __ROMCC__
+
#define LB_TAG_FORWARD 0x0011
struct lb_forward {
uint32_t tag;
@@ -195,6 +204,8 @@ struct lb_framebuffer {
uint8_t reserved_mask_size;
};
+#endif
+
#define LB_TAG_GPIO 0x0013
struct lb_gpio {
@@ -215,6 +226,8 @@ struct lb_gpios {
struct lb_gpio gpios[0];
};
+#ifndef __ROMCC__
+
#define LB_TAG_VDAT 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
@@ -238,6 +251,8 @@ struct lb_cbmem_ref {
uint64_t cbmem_addr;
};
+#endif
+
#define LB_TAG_X86_ROM_MTRR 0x0021
struct lb_x86_rom_mtrr {
uint32_t tag;
@@ -321,6 +336,8 @@ struct cmos_checksum {
/* function prototypes for building the coreboot table */
+#ifndef __ROMCC__
+
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
@@ -338,4 +355,6 @@ void lb_board(struct lb_header *header);
struct lb_record *lb_new_record(struct lb_header *header);
+#endif
+
#endif /* COREBOOT_TABLES_H */
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index a401821..8bbfb95 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -177,7 +177,8 @@ void rtc_check_update_cmos_date(u8 has_century);
#if CONFIG_USE_OPTION_TABLE
enum cb_err set_option(const char *name, void *val);
enum cb_err get_option(void *dest, const char *name);
-unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
+unsigned read_option_real(const char *name, unsigned def);
+#define read_option(name, def) read_option(#name, def)
#else
static inline enum cb_err set_option(const char *name __attribute__((unused)),
void *val __attribute__((unused)))
@@ -185,12 +186,11 @@ static inline enum cb_err set_option(const char *name __attribute__((unused)),
static inline enum cb_err get_option(void *dest __attribute__((unused)),
const char *name __attribute__((unused)))
{ return CB_CMOS_OTABLE_DISABLED; }
-#define read_option_lowlevel(start, size, def) def
+#define read_option(name, def) def
#endif
#else /* defined(__ROMCC__) */
#include <drivers/pc80/mc146818rtc_early.c>
-#endif /* !defined(__ROMCC__) */
-#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
+#endif
#if CONFIG_CMOS_POST
#if CONFIG_USE_OPTION_TABLE
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 1e335f5..23ed54c 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -23,9 +23,6 @@
#include "raminit.h"
#include "e7520.h"
#include <pc80/mc146818rtc.h>
-#if CONFIG_HAVE_OPTION_TABLE
-#include "option_table.h"
-#endif
#define BAR 0x40000000
@@ -617,12 +614,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
}
ecc = 2;
-#if CONFIG_HAVE_OPTION_TABLE
if (read_option(ECC_memory, 1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
print_debug("ECC off\n");
} else
-#endif
{
print_debug("ECC on\n");
}
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 0e6e204..3c0a450 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -24,9 +24,6 @@
#include "raminit.h"
#include "e7525.h"
#include <pc80/mc146818rtc.h>
-#if CONFIG_HAVE_OPTION_TABLE
-#include "option_table.h"
-#endif
#define BAR 0x40000000
@@ -623,12 +620,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
}
ecc = 2;
-#if CONFIG_HAVE_OPTION_TABLE
if (read_option(ECC_memory, 1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
print_debug("ECC off\n");
} else
-#endif
{
print_debug("ECC on\n");
}
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