[coreboot-gerrit] Patch set updated for coreboot: f8a134c i945: consolidate sb & nb early inits
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sun Oct 19 02:53:57 CEST 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7062
-gerrit
commit f8a134c4554596d0924d0ee2256ab830fd67e1d5
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Wed Oct 15 20:17:51 2014 +0200
i945: consolidate sb & nb early inits
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/apple/macbook21/romstage.c | 69 ++----------------------------
src/mainboard/getac/p470/romstage.c | 48 ++-------------------
src/mainboard/ibase/mb899/romstage.c | 51 ++--------------------
src/mainboard/intel/d945gclf/romstage.c | 48 ++-------------------
src/mainboard/kontron/986lcd-m/romstage.c | 50 ++--------------------
src/mainboard/lenovo/t60/romstage.c | 50 +++-------------------
src/mainboard/lenovo/x60/romstage.c | 50 ++--------------------
src/mainboard/roda/rk886ex/romstage.c | 48 ++-------------------
src/northbridge/intel/i945/early_init.c | 52 +++++++++++++++++++++-
src/northbridge/intel/i945/i945.h | 2 +-
src/southbridge/intel/i82801gx/early_lpc.c | 26 +++++++++++
src/southbridge/intel/i82801gx/i82801gx.h | 1 +
12 files changed, 112 insertions(+), 383 deletions(-)
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index e7ff902..7bec26b 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -286,12 +286,9 @@ static void early_ich7_init(void)
void main(unsigned long bist)
{
- u32 reg32;
- int boot_mode = 0;
- int cbmem_was_initted;
+ int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
-
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
@@ -324,22 +321,7 @@ void main(unsigned long bist)
*/
i945_early_initialization();
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-
-#else
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
- }
+ s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
@@ -349,7 +331,7 @@ void main(unsigned long bist)
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(boot_mode, spd_addrmap);
+ sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
@@ -364,50 +346,7 @@ void main(unsigned long bist)
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization();
-
-#if !CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, tom);
- }
-#endif
-#endif
-#endif
-
- MCHBAR16(SSKPD) = 0xCAFE;
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if ((boot_mode == 2) && cbmem_was_initted) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
- HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
- SKPAD_ACPI_S3_MAGIC);
- }
-#endif
+ i945_late_initialization(s3resume);
timestamp_add_now(TS_END_ROMSTAGE);
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 3dab527..ccfb076 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -268,9 +268,7 @@ static void early_ich7_init(void)
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
- u32 reg32;
- int boot_mode = 0;
- int cbmem_was_initted;
+ int s3resume = 0;
if (bist == 0)
enable_lapic();
@@ -302,21 +300,7 @@ void main(unsigned long bist)
*/
i945_early_initialization();
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
@@ -325,7 +309,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode, NULL);
+ sdram_initialize(s3resume ? 2 : 0, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
@@ -339,29 +323,5 @@ void main(unsigned long bist)
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization();
-
- MCHBAR16(SSKPD) = 0xCAFE;
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if ((boot_mode == 2) && cbmem_was_initted) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
- }
-#endif
+ i945_late_initialization(s3resume);
}
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 322907b..2a81921 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -226,9 +226,7 @@ static void early_ich7_init(void)
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
- u32 reg32;
- int boot_mode = 0;
- int cbmem_was_initted;
+ int s3resume = 0;
if (bist == 0)
enable_lapic();
@@ -253,21 +251,7 @@ void main(unsigned long bist)
*/
i945_early_initialization();
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
@@ -276,7 +260,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode, NULL);
+ sdram_initialize(s3resume ? 2 : 0, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
@@ -290,32 +274,5 @@ void main(unsigned long bist)
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization();
-
-
- quick_ram_check();
-
- MCHBAR16(SSKPD) = 0xCAFE;
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if ((boot_mode == 2) && cbmem_was_initted) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
- }
-#endif
+ i945_late_initialization(s3resume);
}
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 0c48247..4508968 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -159,9 +159,7 @@ static void early_ich7_init(void)
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
- u32 reg32;
- int boot_mode = 0;
- int cbmem_was_initted;
+ int s3resume = 0, boot_mode = 0;
if (bist == 0)
enable_lapic();
@@ -187,21 +185,7 @@ void main(unsigned long bist)
*/
i945_early_initialization();
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
@@ -210,7 +194,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode, NULL);
+ sdram_initialize(s3resume ? 2 : boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
@@ -224,29 +208,5 @@ void main(unsigned long bist)
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization();
-
- MCHBAR16(SSKPD) = 0xCAFE;
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if ((boot_mode == 2) && cbmem_was_initted) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
- }
-#endif
+ i945_late_initialization(s3resume);
}
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 2c12c5d..2c89e6c 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -332,9 +332,7 @@ static void early_ich7_init(void)
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
- u32 reg32;
- int boot_mode = 0;
- int cbmem_was_initted;
+ int s3resume = 0;
if (bist == 0)
enable_lapic();
@@ -364,21 +362,7 @@ void main(unsigned long bist)
*/
i945_early_initialization();
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
@@ -387,7 +371,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode, NULL);
+ sdram_initialize(s3resume ? 2 : 0, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
@@ -401,31 +385,5 @@ void main(unsigned long bist)
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization();
-
- quick_ram_check();
-
- MCHBAR16(SSKPD) = 0xCAFE;
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if ((boot_mode == 2) && cbmem_was_initted) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
- }
-#endif
+ i945_late_initialization(s3resume);
}
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index f11b33e..f0ebcbc 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -209,9 +209,8 @@ static void early_ich7_init(void)
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
- u32 reg32;
- int boot_mode = 0, dock_err;
- int cbmem_was_initted;
+ int s3resume = 0;
+ int dock_err;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
@@ -262,21 +261,7 @@ void main(unsigned long bist)
*/
i945_early_initialization();
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
@@ -286,7 +271,7 @@ void main(unsigned long bist)
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(boot_mode, spd_addrmap);
+ sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
@@ -301,32 +286,7 @@ void main(unsigned long bist)
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization();
-
- MCHBAR16(SSKPD) = 0xCAFE;
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if ((boot_mode == 2) && cbmem_was_initted) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
- }
-#endif
+ i945_late_initialization(s3resume);
timestamp_add_now(TS_END_ROMSTAGE);
-
}
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 943143a..1310b33 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -216,9 +216,7 @@ static void early_ich7_init(void)
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
- u32 reg32;
- int boot_mode = 0;
- int cbmem_was_initted;
+ int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
@@ -264,21 +262,7 @@ void main(unsigned long bist)
*/
i945_early_initialization();
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
@@ -288,7 +272,7 @@ void main(unsigned long bist)
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(boot_mode, spd_addrmap);
+ sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
@@ -303,33 +287,7 @@ void main(unsigned long bist)
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization();
-
- MCHBAR16(SSKPD) = 0xCAFE;
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if ((boot_mode == 2) && cbmem_was_initted) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
- HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
- SKPAD_ACPI_S3_MAGIC);
- }
-#endif
+ i945_late_initialization(s3resume);
timestamp_add_now(TS_END_ROMSTAGE);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 7cc1a1d..071fa2a 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -254,9 +254,7 @@ static void init_artec_dongle(void)
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
- u32 reg32;
- int boot_mode = 0;
- int cbmem_was_initted;
+ int s3resume = 0;
if (bist == 0)
enable_lapic();
@@ -289,21 +287,7 @@ void main(unsigned long bist)
/* This has to happen after i945_early_initialization() */
init_artec_dongle();
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
@@ -312,7 +296,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode, NULL);
+ sdram_initialize(s3resume ? 2 : 0, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
@@ -326,29 +310,5 @@ void main(unsigned long bist)
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization();
-
- MCHBAR16(SSKPD) = 0xCAFE;
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if ((boot_mode == 2) && cbmem_was_initted) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
- }
-#endif
+ i945_late_initialization(s3resume);
}
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 24054bd..1715c47 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -22,6 +22,8 @@
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_def.h>
+#include <cbmem.h>
+#include <string.h>
#include "i945.h"
int i945_silicon_revision(void)
@@ -887,7 +889,34 @@ void i945_early_initialization(void)
RCBA32(0x2010) |= (1 << 10);
}
-void i945_late_initialization(void)
+static void i945_prepare_resume(int s3resume)
+{
+ int cbmem_was_initted;
+
+ cbmem_was_initted = !cbmem_recovery(s3resume);
+
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+ if (s3resume && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+ /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+ * through stage 2. We could keep stuff like stack and heap in high tables
+ * memory completely, but that's a wonderful clean up task for another
+ * day.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
+ HIGH_MEMORY_SAVE);
+
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
+ SKPAD_ACPI_S3_MAGIC);
+ }
+}
+
+void i945_late_initialization(int s3resume)
{
i945_setup_egress_port();
@@ -902,4 +931,25 @@ void i945_late_initialization(void)
i945_setup_pci_express_x16();
i945_setup_root_complex_topology();
+
+#if !CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+#if CONFIG_DEBUG_RAM_SETUP
+ sdram_dump_mchbar_registers();
+
+ {
+ /* This will not work if TSEG is in place! */
+ u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c);
+
+ printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
+ ram_check(0x00000000, 0x000a0000);
+ ram_check(0x00100000, tom);
+ }
+#endif
+#endif
+#endif
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+
+ i945_prepare_resume(s3resume);
}
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 9be9379..8573b0c 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -350,7 +350,7 @@ static inline void barrier(void) { asm("" ::: "memory"); }
int i945_silicon_revision(void);
void i945_early_initialization(void);
-void i945_late_initialization(void);
+void i945_late_initialization(int s3resume);
/* provided by mainboard code */
void setup_ich7_gpios(void);
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c
index 9f80d41..69bbfb2 100644
--- a/src/southbridge/intel/i82801gx/early_lpc.c
+++ b/src/southbridge/intel/i82801gx/early_lpc.c
@@ -20,6 +20,9 @@
#include <arch/io.h>
#include <timestamp.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include "i82801gx.h"
#if CONFIG_COLLECT_TIMESTAMPS
tsc_t get_initial_timestamp(void)
@@ -31,3 +34,26 @@ tsc_t get_initial_timestamp(void)
return base_time;
}
#endif
+
+int southbridge_detect_s3_resume(void)
+{
+ u32 reg32;
+
+ /* Read PM1_CNT */
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+ if (((reg32 >> 10) & 7) == 5) {
+ if (acpi_s3_resume_allowed()) {
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ return 1;
+ } else {
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+ }
+ }
+
+ return 0;
+}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 1064dde..ee13b7d 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -44,6 +44,7 @@ extern void i82801gx_enable(device_t dev);
#else
void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
+int southbridge_detect_s3_resume(void);
#endif
#endif
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