[coreboot-gerrit] New patch to review for coreboot: cf09f62 northbridge/amd: Don't hide pointers behind typedefs
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Wed Oct 22 16:06:54 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7168
-gerrit
commit cf09f625585c7dfdfac8521ace7719e69446f809
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Thu Oct 23 01:06:05 2014 +1100
northbridge/amd: Don't hide pointers behind typedefs
Change-Id: I2b523e7ebc4e219b1a5193542dc66977ce7e6aeb
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/northbridge/amd/agesa/family10/reset_test.h | 4 ++--
src/northbridge/amd/agesa/family12/amdfam12_conf.c | 12 ++++++------
src/northbridge/amd/agesa/family12/northbridge.h | 2 +-
src/northbridge/amd/agesa/family14/amdfam14_conf.c | 12 ++++++------
src/northbridge/amd/agesa/family14/northbridge.h | 2 +-
src/northbridge/amd/agesa/family15/northbridge.h | 2 +-
src/northbridge/amd/agesa/family15tn/iommu.c | 4 ++--
src/northbridge/amd/cimx/rd890/late.c | 2 +-
8 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h
index 8c8d9a0..651a813 100644
--- a/src/northbridge/amd/agesa/family10/reset_test.h
+++ b/src/northbridge/amd/agesa/family10/reset_test.h
@@ -33,7 +33,7 @@
static inline u32 warm_reset_detect(u8 nodeid)
{
u32 htic;
- device_t device;
+ struct device * device;
device = NODE_PCI(nodeid, 0);
htic = pci_io_read_config32(device, HT_INIT_CONTROL);
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
@@ -42,7 +42,7 @@ static inline u32 warm_reset_detect(u8 nodeid)
static inline void distinguish_cpu_resets(u8 nodeid)
{
u32 htic;
- device_t device;
+ struct device * device;
device = NODE_PCI(nodeid, 0);
htic = pci_io_read_config32(device, HT_INIT_CONTROL);
htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
index 00ff641..116a466 100644
--- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c
+++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
@@ -28,7 +28,7 @@ struct dram_base_mask_t {
static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
- device_t dev;
+ struct device * dev;
struct dram_base_mask_t d;
#if defined(__PRE_RAM__)
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
@@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
u32 busn_min, u32 busn_max,
u32 type)
{
- device_t dev;
+ struct device * dev;
u32 i;
u32 tempreg;
u32 index_min, index_max;
@@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
{
u32 i;
u32 tempreg;
- device_t dev;
+ struct device * dev;
#if CONFIG_EXT_CONF_SUPPORT
if(ht_c_index<4) {
@@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 io_min, u32 io_max, u32 nodes)
{
u32 i;
- device_t dev;
+ struct device * dev;
#if CONFIG_EXT_CONF_SUPPORT
if(ht_c_index<4) {
#endif
@@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
return 0;
}
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
{
@@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
return;
}
- device_t dev;
+ struct device * dev;
u32 j;
// if ht_c_index > 3, We should use extend space
// for nodeid at first
diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h
index 4edb525..c3fc171 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.h
+++ b/src/northbridge/amd/agesa/family12/northbridge.h
@@ -23,6 +23,6 @@
static struct device_operations pci_domain_ops;
static struct device_operations cpu_bus_ops;
-device_t get_node_pci(u32 nodeid, u32 fn);
+struct device * get_node_pci(u32 nodeid, u32 fn);
#endif /* NORTHBRIDGE_AMD_AGESA_FAM12H_H */
diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c
index c255213..b72b21b 100644
--- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c
+++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c
@@ -28,7 +28,7 @@ struct dram_base_mask_t {
static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
- device_t dev;
+ struct device * dev;
struct dram_base_mask_t d;
#if defined(__PRE_RAM__)
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
@@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
u32 busn_min, u32 busn_max,
u32 type)
{
- device_t dev;
+ struct device * dev;
u32 i;
u32 tempreg;
u32 index_min, index_max;
@@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
{
u32 i;
u32 tempreg;
- device_t dev;
+ struct device * dev;
#if CONFIG_EXT_CONF_SUPPORT
if(ht_c_index<4) {
@@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 io_min, u32 io_max, u32 nodes)
{
u32 i;
- device_t dev;
+ struct device * dev;
#if CONFIG_EXT_CONF_SUPPORT
if(ht_c_index<4) {
#endif
@@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
return 0;
}
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
{
@@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
return;
}
- device_t dev;
+ struct device * dev;
u32 j;
// if ht_c_index > 3, We should use extend space
// for nodeid at first
diff --git a/src/northbridge/amd/agesa/family14/northbridge.h b/src/northbridge/amd/agesa/family14/northbridge.h
index 474e74c..6046137 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.h
+++ b/src/northbridge/amd/agesa/family14/northbridge.h
@@ -23,6 +23,6 @@
static struct device_operations pci_domain_ops;
static struct device_operations cpu_bus_ops;
-device_t get_node_pci(u32 nodeid, u32 fn);
+struct device * get_node_pci(u32 nodeid, u32 fn);
#endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */
diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h
index 99fdcae..3a90964 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.h
+++ b/src/northbridge/amd/agesa/family15/northbridge.h
@@ -22,6 +22,6 @@
static struct device_operations pci_domain_ops;
static struct device_operations cpu_bus_ops;
-static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max);
+static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max);
#endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */
diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c
index 3765f20..5b3529b 100644
--- a/src/northbridge/amd/agesa/family15tn/iommu.c
+++ b/src/northbridge/amd/agesa/family15tn/iommu.c
@@ -23,7 +23,7 @@
#include <device/pci_ops.h>
#include <lib.h>
-static void iommu_read_resources(device_t dev)
+static void iommu_read_resources(struct device * dev)
{
struct resource *res;
@@ -39,7 +39,7 @@ static void iommu_read_resources(device_t dev)
res->flags = IORESOURCE_MEM;
}
-static void iommu_set_resources(device_t dev)
+static void iommu_set_resources(struct device * dev)
{
struct resource *res;
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c
index fa23344..09cdce5 100644
--- a/src/northbridge/amd/cimx/rd890/late.c
+++ b/src/northbridge/amd/cimx/rd890/late.c
@@ -66,7 +66,7 @@ void nb_Late_Post_Init(void)
LibSystemApiCall(AmdLatePostInit, &gConfig);
}
-static void rd890_enable(device_t dev)
+static void rd890_enable(struct device * dev)
{
u32 address = 0;
u32 devfn;
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