[coreboot-gerrit] Patch set updated for coreboot: 98133e4 AGESA boards: Move agesawrapper_amdinitmmio()
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Oct 22 16:36:38 CEST 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7163
-gerrit
commit 98133e4aee5705430efa38a6a373da9eff0a74cd
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Oct 17 17:52:17 2014 +0300
AGESA boards: Move agesawrapper_amdinitmmio()
Enabling MMCONF PCI-e configuration access and possible LPC decoder
configuration should be done before console_init().
Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/amd/dinar/romstage.c | 5 ++---
src/mainboard/amd/inagua/romstage.c | 5 ++---
src/mainboard/amd/persimmon/romstage.c | 5 ++---
src/mainboard/amd/south_station/romstage.c | 5 ++---
src/mainboard/amd/union_station/romstage.c | 5 ++---
src/mainboard/asrock/e350m1/romstage.c | 5 ++---
src/mainboard/gizmosphere/gizmo/romstage.c | 5 ++---
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 5 ++---
src/mainboard/lippert/frontrunner-af/romstage.c | 5 ++---
src/mainboard/lippert/toucan-af/romstage.c | 5 ++---
10 files changed, 20 insertions(+), 30 deletions(-)
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ed3cf83..7fc8b60 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -44,6 +44,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
@@ -63,9 +65,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
- post_code(0x32);
- AGESAWRAPPER(amdinitmmio);
-
/* Halt if there was a built in self test failure */
post_code(0x33);
report_bist_failure(bist);
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index bd92558..7e15036 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -55,6 +55,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
__writemsr (0xc0010062, 0);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -74,9 +76,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 9b61c18..360ff8a 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -61,6 +61,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -79,9 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index de4989f..27c48eb 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -56,6 +56,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -74,9 +76,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 0b906a9..8618142 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -51,6 +51,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
__writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
__writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -68,9 +70,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index ecfe7e1..4f6fd7f 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -56,6 +56,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr(0xc0010062, 0);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -74,9 +76,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index aab0087..ece6abc 100755
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -69,6 +69,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr.hi = 0;
wrmsr (MSR_PSTATE_CONTROL, msr);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -87,9 +89,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 30215ce..2af5c7c 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -77,6 +77,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -95,9 +97,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index e792e62..cc1edc0 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -60,6 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -78,9 +80,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 57d3dcd..f332660 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -61,6 +61,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
@@ -79,9 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
More information about the coreboot-gerrit
mailing list