[coreboot-gerrit] New patch to review for coreboot: d478566 bd82x6x/sata: Fix AHCI mode setting for max 6 ports on first controller

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7175

-gerrit

commit d47856663fb909c147a54f07cfe6484630302199
Author: Damien Zammit <damien at zamaudio.com>
Date:   Thu Oct 23 13:21:45 2014 +1100

    bd82x6x/sata: Fix AHCI mode setting for max 6 ports on first controller
    
    According to the Intel datasheet, 2 flags must be set when in AHCI mode.
    This is now fixed.  There is an alternative setting to enable max 2 ports
    on first controller and 4 on the second controller, but this patch hardcodes
    max 6 sata ports on the first controller.
    Tested and working on new Intel desktop mainboard port.
    
    Change-Id: I7872f0d4d4ffacbf4f80bb0157389ed8593d42e9
    Co-Author: Damien Zammit <damien at zamaudio.com>
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/southbridge/intel/bd82x6x/chip.h | 1 +
 src/southbridge/intel/bd82x6x/sata.c | 8 +++++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 0f2f0e9..e8d1da9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -65,6 +65,7 @@ struct southbridge_intel_bd82x6x_config {
 
 	/* IDE configuration */
 	uint8_t sata_port_map;
+	uint8_t sata_port_split;
 	uint32_t sata_port0_gen3_tx;
 	uint32_t sata_port1_gen3_tx;
 
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..702dabc 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -224,15 +224,21 @@ static void sata_enable(device_t dev)
 	if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
 		sata_mode = 0;
 
+	/* Take care as 0x90 has reserved bits */
+	map = pci_read_config16(dev, 0x90);
+
 	/*
 	 * Set SATA controller mode early so the resource allocator can
 	 * properly assign IO/Memory resources for the controller.
 	 */
 	if (sata_mode == 0)
-		map = 0x0060;
+		map |= 0x0060;
 
 	map |= (config->sata_port_map ^ 0x3f) << 8;
 
+	/* Toggle between 6/0 or 2/4 on split first/second respectively controllers */
+	map |= (config->sata_port_split << 5) & 0x20;
+
 	pci_write_config16(dev, 0x90, map);
 }