[coreboot-gerrit] Patch set updated for coreboot: 856cdeb Rename directories to match vendor names
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sat Oct 25 02:52:07 CEST 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7181
-gerrit
commit 856cdebe01b809c3f291596344bcf3f88ae3c6c7
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Tue Oct 21 09:03:16 2014 +0200
Rename directories to match vendor names
Change-Id: Ie6641d4d4b003e1d712f8990c24a4e596bfff8d2
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/Kconfig | 34 +--
src/mainboard/a-trend/Kconfig | 38 ---
src/mainboard/a-trend/atc-6220/Kconfig | 43 ---
src/mainboard/a-trend/atc-6220/board_info.txt | 6 -
src/mainboard/a-trend/atc-6220/devicetree.cb | 59 ----
src/mainboard/a-trend/atc-6220/irq_tables.c | 50 ----
src/mainboard/a-trend/atc-6220/romstage.c | 57 ----
src/mainboard/a-trend/atc-6240/Kconfig | 43 ---
src/mainboard/a-trend/atc-6240/board_info.txt | 4 -
src/mainboard/a-trend/atc-6240/devicetree.cb | 69 -----
src/mainboard/a-trend/atc-6240/irq_tables.c | 50 ----
src/mainboard/a-trend/atc-6240/romstage.c | 56 ----
src/mainboard/a_trend/Kconfig | 38 +++
src/mainboard/a_trend/atc-6220/Kconfig | 43 +++
src/mainboard/a_trend/atc-6220/board_info.txt | 6 +
src/mainboard/a_trend/atc-6220/devicetree.cb | 59 ++++
src/mainboard/a_trend/atc-6220/irq_tables.c | 50 ++++
src/mainboard/a_trend/atc-6220/romstage.c | 57 ++++
src/mainboard/a_trend/atc-6240/Kconfig | 43 +++
src/mainboard/a_trend/atc-6240/board_info.txt | 4 +
src/mainboard/a_trend/atc-6240/devicetree.cb | 69 +++++
src/mainboard/a_trend/atc-6240/irq_tables.c | 50 ++++
src/mainboard/a_trend/atc-6240/romstage.c | 56 ++++
src/mainboard/artec_group/Kconfig | 19 ++
src/mainboard/artec_group/dbe61/Kconfig | 28 ++
src/mainboard/artec_group/dbe61/board_info.txt | 3 +
src/mainboard/artec_group/dbe61/cmos.layout | 72 +++++
src/mainboard/artec_group/dbe61/devicetree.cb | 42 +++
src/mainboard/artec_group/dbe61/irq_tables.c | 68 +++++
src/mainboard/artec_group/dbe61/mainboard.c | 56 ++++
src/mainboard/artec_group/dbe61/romstage.c | 126 ++++++++
src/mainboard/artec_group/dbe61/spd_table.h | 53 ++++
src/mainboard/artecgroup/Kconfig | 19 --
src/mainboard/artecgroup/dbe61/Kconfig | 28 --
src/mainboard/artecgroup/dbe61/board_info.txt | 3 -
src/mainboard/artecgroup/dbe61/cmos.layout | 72 -----
src/mainboard/artecgroup/dbe61/devicetree.cb | 42 ---
src/mainboard/artecgroup/dbe61/irq_tables.c | 68 -----
src/mainboard/artecgroup/dbe61/mainboard.c | 56 ----
src/mainboard/artecgroup/dbe61/romstage.c | 126 --------
src/mainboard/artecgroup/dbe61/spd_table.h | 53 ----
src/mainboard/bachmann/Kconfig | 17 --
src/mainboard/bachmann/ot200/Kconfig | 35 ---
src/mainboard/bachmann/ot200/board_info.txt | 1 -
src/mainboard/bachmann/ot200/cmos.default | 4 -
src/mainboard/bachmann/ot200/cmos.layout | 64 ----
src/mainboard/bachmann/ot200/devicetree.cb | 40 ---
src/mainboard/bachmann/ot200/irq_tables.c | 68 -----
src/mainboard/bachmann/ot200/mainboard.c | 92 ------
src/mainboard/bachmann/ot200/romstage.c | 82 -----
src/mainboard/bachmann_electronic/Kconfig | 17 ++
src/mainboard/bachmann_electronic/ot200/Kconfig | 35 +++
.../bachmann_electronic/ot200/board_info.txt | 1 +
.../bachmann_electronic/ot200/cmos.default | 4 +
.../bachmann_electronic/ot200/cmos.layout | 64 ++++
.../bachmann_electronic/ot200/devicetree.cb | 40 +++
.../bachmann_electronic/ot200/irq_tables.c | 68 +++++
.../bachmann_electronic/ot200/mainboard.c | 92 ++++++
src/mainboard/bachmann_electronic/ot200/romstage.c | 82 +++++
src/mainboard/digital_logic/Kconfig | 23 ++
src/mainboard/digital_logic/adl855pc/Kconfig | 33 +++
.../digital_logic/adl855pc/board_info.txt | 1 +
src/mainboard/digital_logic/adl855pc/cmos.layout | 72 +++++
src/mainboard/digital_logic/adl855pc/devicetree.cb | 56 ++++
src/mainboard/digital_logic/adl855pc/irq_tables.c | 36 +++
src/mainboard/digital_logic/adl855pc/romstage.c | 64 ++++
src/mainboard/digital_logic/msm586seg/Kconfig | 23 ++
.../digital_logic/msm586seg/board_info.txt | 2 +
src/mainboard/digital_logic/msm586seg/cmos.layout | 72 +++++
.../digital_logic/msm586seg/devicetree.cb | 7 +
src/mainboard/digital_logic/msm586seg/irq_tables.c | 31 ++
src/mainboard/digital_logic/msm586seg/mainboard.c | 133 +++++++++
src/mainboard/digital_logic/msm586seg/romstage.c | 240 +++++++++++++++
src/mainboard/digital_logic/msm800sev/Kconfig | 27 ++
.../digital_logic/msm800sev/board_info.txt | 2 +
src/mainboard/digital_logic/msm800sev/cmos.layout | 72 +++++
.../digital_logic/msm800sev/devicetree.cb | 86 ++++++
src/mainboard/digital_logic/msm800sev/irq_tables.c | 75 +++++
src/mainboard/digital_logic/msm800sev/mainboard.c | 36 +++
src/mainboard/digital_logic/msm800sev/romstage.c | 82 +++++
src/mainboard/digitallogic/Kconfig | 23 --
src/mainboard/digitallogic/adl855pc/Kconfig | 33 ---
src/mainboard/digitallogic/adl855pc/board_info.txt | 1 -
src/mainboard/digitallogic/adl855pc/cmos.layout | 72 -----
src/mainboard/digitallogic/adl855pc/devicetree.cb | 56 ----
src/mainboard/digitallogic/adl855pc/irq_tables.c | 36 ---
src/mainboard/digitallogic/adl855pc/romstage.c | 64 ----
src/mainboard/digitallogic/msm586seg/Kconfig | 23 --
.../digitallogic/msm586seg/board_info.txt | 2 -
src/mainboard/digitallogic/msm586seg/cmos.layout | 72 -----
src/mainboard/digitallogic/msm586seg/devicetree.cb | 7 -
src/mainboard/digitallogic/msm586seg/irq_tables.c | 31 --
src/mainboard/digitallogic/msm586seg/mainboard.c | 133 ---------
src/mainboard/digitallogic/msm586seg/romstage.c | 240 ---------------
src/mainboard/digitallogic/msm800sev/Kconfig | 27 --
.../digitallogic/msm800sev/board_info.txt | 2 -
src/mainboard/digitallogic/msm800sev/cmos.layout | 72 -----
src/mainboard/digitallogic/msm800sev/devicetree.cb | 86 ------
src/mainboard/digitallogic/msm800sev/irq_tables.c | 75 -----
src/mainboard/digitallogic/msm800sev/mainboard.c | 36 ---
src/mainboard/digitallogic/msm800sev/romstage.c | 82 -----
src/mainboard/lanner/em8510/romstage.c | 2 +-
src/mainboard/linutop/linutop1/board_info.txt | 2 +-
src/mainboard/packard_bell/Kconfig | 19 ++
src/mainboard/packard_bell/ms2290/Kconfig | 61 ++++
src/mainboard/packard_bell/ms2290/Makefile.inc | 20 ++
src/mainboard/packard_bell/ms2290/acpi/ac.asl | 49 +++
src/mainboard/packard_bell/ms2290/acpi/battery.asl | 155 ++++++++++
src/mainboard/packard_bell/ms2290/acpi/ec.asl | 136 +++++++++
src/mainboard/packard_bell/ms2290/acpi/gpe.asl | 24 ++
.../packard_bell/ms2290/acpi/nehalem_pci_irqs.asl | 86 ++++++
.../packard_bell/ms2290/acpi/platform.asl | 146 +++++++++
src/mainboard/packard_bell/ms2290/acpi/superio.asl | 1 +
src/mainboard/packard_bell/ms2290/acpi/thermal.asl | 48 +++
src/mainboard/packard_bell/ms2290/acpi_tables.c | 97 ++++++
src/mainboard/packard_bell/ms2290/board_info.txt | 6 +
src/mainboard/packard_bell/ms2290/cmos.default | 7 +
src/mainboard/packard_bell/ms2290/cmos.layout | 138 +++++++++
src/mainboard/packard_bell/ms2290/devicetree.cb | 104 +++++++
src/mainboard/packard_bell/ms2290/dsdt.asl | 88 ++++++
src/mainboard/packard_bell/ms2290/fadt.c | 160 ++++++++++
src/mainboard/packard_bell/ms2290/hda_verb.c | 66 +++++
src/mainboard/packard_bell/ms2290/mainboard.c | 136 +++++++++
src/mainboard/packard_bell/ms2290/romstage.c | 330 +++++++++++++++++++++
src/mainboard/packard_bell/ms2290/smihandler.c | 112 +++++++
src/mainboard/packardbell/Kconfig | 19 --
src/mainboard/packardbell/ms2290/Kconfig | 61 ----
src/mainboard/packardbell/ms2290/Makefile.inc | 20 --
src/mainboard/packardbell/ms2290/acpi/ac.asl | 49 ---
src/mainboard/packardbell/ms2290/acpi/battery.asl | 155 ----------
src/mainboard/packardbell/ms2290/acpi/ec.asl | 136 ---------
src/mainboard/packardbell/ms2290/acpi/gpe.asl | 24 --
.../packardbell/ms2290/acpi/nehalem_pci_irqs.asl | 86 ------
src/mainboard/packardbell/ms2290/acpi/platform.asl | 146 ---------
src/mainboard/packardbell/ms2290/acpi/superio.asl | 1 -
src/mainboard/packardbell/ms2290/acpi/thermal.asl | 48 ---
src/mainboard/packardbell/ms2290/acpi_tables.c | 97 ------
src/mainboard/packardbell/ms2290/board_info.txt | 6 -
src/mainboard/packardbell/ms2290/cmos.default | 7 -
src/mainboard/packardbell/ms2290/cmos.layout | 138 ---------
src/mainboard/packardbell/ms2290/devicetree.cb | 104 -------
src/mainboard/packardbell/ms2290/dsdt.asl | 88 ------
src/mainboard/packardbell/ms2290/fadt.c | 160 ----------
src/mainboard/packardbell/ms2290/hda_verb.c | 66 -----
src/mainboard/packardbell/ms2290/mainboard.c | 136 ---------
src/mainboard/packardbell/ms2290/romstage.c | 330 ---------------------
src/mainboard/packardbell/ms2290/smihandler.c | 112 -------
src/mainboard/pc_engines/Kconfig | 26 ++
src/mainboard/pc_engines/alix1c/Kconfig | 29 ++
src/mainboard/pc_engines/alix1c/board_info.txt | 5 +
src/mainboard/pc_engines/alix1c/cmos.default | 11 +
src/mainboard/pc_engines/alix1c/cmos.layout | 72 +++++
src/mainboard/pc_engines/alix1c/devicetree.cb | 86 ++++++
src/mainboard/pc_engines/alix1c/irq_tables.c | 110 +++++++
src/mainboard/pc_engines/alix1c/mainboard.c | 36 +++
src/mainboard/pc_engines/alix1c/romstage.c | 169 +++++++++++
src/mainboard/pc_engines/alix2c/Kconfig | 9 +
src/mainboard/pc_engines/alix2c/board_info.txt | 4 +
src/mainboard/pc_engines/alix2d/Kconfig | 30 ++
src/mainboard/pc_engines/alix2d/board_info.txt | 3 +
src/mainboard/pc_engines/alix2d/cmos.layout | 72 +++++
src/mainboard/pc_engines/alix2d/devicetree.cb | 46 +++
src/mainboard/pc_engines/alix2d/irq_tables.c | 117 ++++++++
src/mainboard/pc_engines/alix2d/mainboard.c | 36 +++
src/mainboard/pc_engines/alix2d/romstage.c | 192 ++++++++++++
src/mainboard/pc_engines/alix6/Kconfig | 9 +
src/mainboard/pc_engines/alix6/board_info.txt | 5 +
src/mainboard/pcengines/Kconfig | 26 --
src/mainboard/pcengines/alix1c/Kconfig | 29 --
src/mainboard/pcengines/alix1c/board_info.txt | 5 -
src/mainboard/pcengines/alix1c/cmos.default | 11 -
src/mainboard/pcengines/alix1c/cmos.layout | 72 -----
src/mainboard/pcengines/alix1c/devicetree.cb | 86 ------
src/mainboard/pcengines/alix1c/irq_tables.c | 110 -------
src/mainboard/pcengines/alix1c/mainboard.c | 36 ---
src/mainboard/pcengines/alix1c/romstage.c | 169 -----------
src/mainboard/pcengines/alix2c/Kconfig | 9 -
src/mainboard/pcengines/alix2c/board_info.txt | 4 -
src/mainboard/pcengines/alix2d/Kconfig | 30 --
src/mainboard/pcengines/alix2d/board_info.txt | 3 -
src/mainboard/pcengines/alix2d/cmos.layout | 72 -----
src/mainboard/pcengines/alix2d/devicetree.cb | 46 ---
src/mainboard/pcengines/alix2d/irq_tables.c | 117 --------
src/mainboard/pcengines/alix2d/mainboard.c | 36 ---
src/mainboard/pcengines/alix2d/romstage.c | 192 ------------
src/mainboard/pcengines/alix6/Kconfig | 9 -
src/mainboard/pcengines/alix6/board_info.txt | 5 -
src/mainboard/sun/Kconfig | 17 ++
src/mainboard/sun/ultra40/Kconfig | 66 +++++
src/mainboard/sun/ultra40/board_info.txt | 2 +
src/mainboard/sun/ultra40/cmos.layout | 96 ++++++
src/mainboard/sun/ultra40/devicetree.cb | 151 ++++++++++
src/mainboard/sun/ultra40/get_bus_conf.c | 279 +++++++++++++++++
src/mainboard/sun/ultra40/irq_tables.c | 181 +++++++++++
src/mainboard/sun/ultra40/mptable.c | 197 ++++++++++++
src/mainboard/sun/ultra40/resourcemap.c | 265 +++++++++++++++++
src/mainboard/sun/ultra40/romstage.c | 152 ++++++++++
src/mainboard/sunw/Kconfig | 17 --
src/mainboard/sunw/ultra40/Kconfig | 66 -----
src/mainboard/sunw/ultra40/board_info.txt | 2 -
src/mainboard/sunw/ultra40/cmos.layout | 96 ------
src/mainboard/sunw/ultra40/devicetree.cb | 151 ----------
src/mainboard/sunw/ultra40/get_bus_conf.c | 279 -----------------
src/mainboard/sunw/ultra40/irq_tables.c | 181 -----------
src/mainboard/sunw/ultra40/mptable.c | 197 ------------
src/mainboard/sunw/ultra40/resourcemap.c | 265 -----------------
src/mainboard/sunw/ultra40/romstage.c | 152 ----------
src/mainboard/traverse/Kconfig | 17 --
src/mainboard/traverse/geos/Kconfig | 32 --
src/mainboard/traverse/geos/board_info.txt | 4 -
src/mainboard/traverse/geos/cmos.layout | 73 -----
src/mainboard/traverse/geos/devicetree.cb | 40 ---
src/mainboard/traverse/geos/irq_tables.c | 71 -----
src/mainboard/traverse/geos/mainboard.c | 36 ---
src/mainboard/traverse/geos/romstage.c | 82 -----
src/mainboard/traverse_technologies/Kconfig | 17 ++
src/mainboard/traverse_technologies/geos/Kconfig | 32 ++
.../traverse_technologies/geos/board_info.txt | 4 +
.../traverse_technologies/geos/cmos.layout | 73 +++++
.../traverse_technologies/geos/devicetree.cb | 40 +++
.../traverse_technologies/geos/irq_tables.c | 71 +++++
.../traverse_technologies/geos/mainboard.c | 36 +++
.../traverse_technologies/geos/romstage.c | 82 +++++
src/mainboard/win_enterprise/Kconfig | 39 +++
src/mainboard/win_enterprise/mb6047/Kconfig | 68 +++++
src/mainboard/win_enterprise/mb6047/acpi_tables.c | 64 ++++
src/mainboard/win_enterprise/mb6047/board_info.txt | 1 +
src/mainboard/win_enterprise/mb6047/cmos.layout | 96 ++++++
src/mainboard/win_enterprise/mb6047/devicetree.cb | 120 ++++++++
src/mainboard/win_enterprise/mb6047/dsdt.asl | 210 +++++++++++++
src/mainboard/win_enterprise/mb6047/get_bus_conf.c | 99 +++++++
src/mainboard/win_enterprise/mb6047/irq_tables.c | 136 +++++++++
src/mainboard/win_enterprise/mb6047/mainboard.c | 20 ++
src/mainboard/win_enterprise/mb6047/mptable.c | 104 +++++++
src/mainboard/win_enterprise/mb6047/romstage.c | 150 ++++++++++
src/mainboard/win_enterprise/pl6064/Kconfig | 27 ++
src/mainboard/win_enterprise/pl6064/board_info.txt | 3 +
src/mainboard/win_enterprise/pl6064/cmos.layout | 72 +++++
src/mainboard/win_enterprise/pl6064/devicetree.cb | 81 +++++
src/mainboard/win_enterprise/pl6064/irq_tables.c | 73 +++++
src/mainboard/win_enterprise/pl6064/mainboard.c | 36 +++
src/mainboard/win_enterprise/pl6064/romstage.c | 84 ++++++
src/mainboard/winent/Kconfig | 39 ---
src/mainboard/winent/mb6047/Kconfig | 68 -----
src/mainboard/winent/mb6047/acpi_tables.c | 64 ----
src/mainboard/winent/mb6047/board_info.txt | 1 -
src/mainboard/winent/mb6047/cmos.layout | 96 ------
src/mainboard/winent/mb6047/devicetree.cb | 120 --------
src/mainboard/winent/mb6047/dsdt.asl | 210 -------------
src/mainboard/winent/mb6047/get_bus_conf.c | 99 -------
src/mainboard/winent/mb6047/irq_tables.c | 136 ---------
src/mainboard/winent/mb6047/mainboard.c | 20 --
src/mainboard/winent/mb6047/mptable.c | 104 -------
src/mainboard/winent/mb6047/romstage.c | 150 ----------
src/mainboard/winent/pl6064/Kconfig | 27 --
src/mainboard/winent/pl6064/board_info.txt | 3 -
src/mainboard/winent/pl6064/cmos.layout | 72 -----
src/mainboard/winent/pl6064/devicetree.cb | 81 -----
src/mainboard/winent/pl6064/irq_tables.c | 73 -----
src/mainboard/winent/pl6064/mainboard.c | 36 ---
src/mainboard/winent/pl6064/romstage.c | 84 ------
261 files changed, 8837 insertions(+), 8837 deletions(-)
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 29b439c..90e3941 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -22,7 +22,7 @@ config VENDOR_APPLE
bool "Apple"
config VENDOR_ARIMA
bool "Arima"
-config VENDOR_ARTECGROUP
+config VENDOR_ARTEC_GROUP
bool "Artec Group"
config VENDOR_ASI
bool "ASI"
@@ -38,7 +38,7 @@ config VENDOR_AXUS
bool "AXUS"
config VENDOR_AZZA
bool "AZZA"
-config VENDOR_BACHMANN
+config VENDOR_BACHMANN_ELECTRONIC
bool "Bachmann electronic"
config VENDOR_BCOM
bool "BCOM"
@@ -52,7 +52,7 @@ config VENDOR_COMPAQ
bool "Compaq"
config VENDOR_CUBIETECH
bool "Cubietech"
-config VENDOR_DIGITALLOGIC
+config VENDOR_DIGITAL_LOGIC
bool "DIGITAL-LOGIC"
config VENDOR_DMP
bool "DMP"
@@ -108,9 +108,9 @@ config VENDOR_NOKIA
bool "Nokia"
config VENDOR_NVIDIA
bool "NVIDIA"
-config VENDOR_PACKARDBELL
+config VENDOR_PACKARD_BELL
bool "Packard Bell"
-config VENDOR_PCENGINES
+config VENDOR_PC_ENGINES
bool "PC Engines"
config VENDOR_RCA
bool "RCA"
@@ -122,7 +122,7 @@ config VENDOR_SIEMENS
bool "Siemens"
config VENDOR_SOYO
bool "Soyo"
-config VENDOR_SUNW
+config VENDOR_SUN
bool "Sun"
config VENDOR_SUPERMICRO
bool "Supermicro"
@@ -136,20 +136,20 @@ config VENDOR_TI
bool "TI"
config VENDOR_THOMSON
bool "Thomson"
-config VENDOR_TRAVERSE
+config VENDOR_TRAVERSE_TECHNOLOGIES
bool "Traverse Technologies"
config VENDOR_TYAN
bool "Tyan"
config VENDOR_VIA
bool "VIA"
-config VENDOR_WINENT
+config VENDOR_WIN_ENTERPRISE
bool "Win Enterprises"
config VENDOR_WYSE
bool "Wyse"
endchoice
-source "src/mainboard/a-trend/Kconfig"
+source "src/mainboard/a_trend/Kconfig"
source "src/mainboard/aaeon/Kconfig"
source "src/mainboard/abit/Kconfig"
source "src/mainboard/adlink/Kconfig"
@@ -159,21 +159,21 @@ source "src/mainboard/amd/Kconfig"
source "src/mainboard/aopen/Kconfig"
source "src/mainboard/apple/Kconfig"
source "src/mainboard/arima/Kconfig"
-source "src/mainboard/artecgroup/Kconfig"
+source "src/mainboard/artec_group/Kconfig"
source "src/mainboard/asi/Kconfig"
source "src/mainboard/asrock/Kconfig"
source "src/mainboard/asus/Kconfig"
source "src/mainboard/avalue/Kconfig"
source "src/mainboard/axus/Kconfig"
source "src/mainboard/azza/Kconfig"
-source "src/mainboard/bachmann/Kconfig"
+source "src/mainboard/bachmann_electronic/Kconfig"
source "src/mainboard/bcom/Kconfig"
source "src/mainboard/bifferos/Kconfig"
source "src/mainboard/biostar/Kconfig"
source "src/mainboard/broadcom/Kconfig"
source "src/mainboard/compaq/Kconfig"
source "src/mainboard/cubietech/Kconfig"
-source "src/mainboard/digitallogic/Kconfig"
+source "src/mainboard/digital_logic/Kconfig"
source "src/mainboard/dmp/Kconfig"
source "src/mainboard/eaglelion/Kconfig"
source "src/mainboard/ecs/Kconfig"
@@ -201,24 +201,24 @@ source "src/mainboard/nec/Kconfig"
source "src/mainboard/newisys/Kconfig"
source "src/mainboard/nokia/Kconfig"
source "src/mainboard/nvidia/Kconfig"
-source "src/mainboard/packardbell/Kconfig"
-source "src/mainboard/pcengines/Kconfig"
+source "src/mainboard/packard_bell/Kconfig"
+source "src/mainboard/pc_engines/Kconfig"
source "src/mainboard/rca/Kconfig"
source "src/mainboard/roda/Kconfig"
source "src/mainboard/samsung/Kconfig"
source "src/mainboard/siemens/Kconfig"
source "src/mainboard/soyo/Kconfig"
-source "src/mainboard/sunw/Kconfig"
+source "src/mainboard/sun/Kconfig"
source "src/mainboard/supermicro/Kconfig"
source "src/mainboard/technexion/Kconfig"
source "src/mainboard/technologic/Kconfig"
source "src/mainboard/televideo/Kconfig"
source "src/mainboard/thomson/Kconfig"
source "src/mainboard/ti/Kconfig"
-source "src/mainboard/traverse/Kconfig"
+source "src/mainboard/traverse_technologies/Kconfig"
source "src/mainboard/tyan/Kconfig"
source "src/mainboard/via/Kconfig"
-source "src/mainboard/winent/Kconfig"
+source "src/mainboard/win_enterprise/Kconfig"
source "src/mainboard/wyse/Kconfig"
config BOARD_ROMSIZE_KB_64
diff --git a/src/mainboard/a-trend/Kconfig b/src/mainboard/a-trend/Kconfig
deleted file mode 100644
index 88232e1..0000000
--- a/src/mainboard/a-trend/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-if VENDOR_A_TREND
-
-choice
- prompt "Mainboard model"
-
-config BOARD_A_TREND_ATC_6220
- bool "ATC-6220"
-config BOARD_A_TREND_ATC_6240
- bool "ATC-6240"
-
-endchoice
-
-source "src/mainboard/a-trend/atc-6220/Kconfig"
-source "src/mainboard/a-trend/atc-6240/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "A-Trend"
-
-endif # VENDOR_A_TREND
diff --git a/src/mainboard/a-trend/atc-6220/Kconfig b/src/mainboard/a-trend/atc-6220/Kconfig
deleted file mode 100644
index 036d8e6..0000000
--- a/src/mainboard/a-trend/atc-6220/Kconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-if BOARD_A_TREND_ATC_6220
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SLOT_1
- select NORTHBRIDGE_INTEL_I440BX
- select SOUTHBRIDGE_INTEL_I82371EB
- select SUPERIO_WINBOND_W83977TF
- select HAVE_PIRQ_TABLE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_256
-
-config MAINBOARD_DIR
- string
- default a-trend/atc-6220
-
-config MAINBOARD_PART_NUMBER
- string
- default "ATC-6220"
-
-config IRQ_SLOT_COUNT
- int
- default 7
-
-endif # BOARD_A_TREND_ATC_6220
diff --git a/src/mainboard/a-trend/atc-6220/board_info.txt b/src/mainboard/a-trend/atc-6220/board_info.txt
deleted file mode 100644
index a56cca3..0000000
--- a/src/mainboard/a-trend/atc-6220/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: desktop
-Board URL: http://www.motherboard.cz/mb/atrend/atc6220.htm
-ROM package: DIP32
-ROM protocol: Parallel
-ROM socketed: y
-Flashrom support: y
diff --git a/src/mainboard/a-trend/atc-6220/devicetree.cb b/src/mainboard/a-trend/atc-6220/devicetree.cb
deleted file mode 100644
index 0dea9ae..0000000
--- a/src/mainboard/a-trend/atc-6220/devicetree.cb
+++ /dev/null
@@ -1,59 +0,0 @@
-chip northbridge/intel/i440bx # Northbridge
- device cpu_cluster 0 on # APIC cluster
- chip cpu/intel/slot_1 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- device pci 1.0 on end # PCI/AGP bridge
- chip southbridge/intel/i82371eb # Southbridge
- device pci 7.0 on # ISA bridge
- chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
- device pnp 3f0.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 3f0.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 3f0.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 3f0.3 on # COM2 / IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 3f0.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard interrupt
- irq 0x72 = 12 # PS/2 mouse interrupt
- end
- device pnp 3f0.6 on # Consumer IR
- end
- device pnp 3f0.7 on # GPIO 1
- end
- device pnp 3f0.8 on # GPIO 2
- end
- device pnp 3f0.a on # ACPI
- end
- end
- end
- device pci 7.1 on end # IDE
- device pci 7.2 on end # USB
- device pci 7.3 on end # ACPI
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "ide_legacy_enable" = "1"
- # Enable UDMA/33 for higher speed if your IDE device(s) support it.
- register "ide0_drive0_udma33_enable" = "0"
- register "ide0_drive1_udma33_enable" = "0"
- register "ide1_drive0_udma33_enable" = "0"
- register "ide1_drive1_udma33_enable" = "0"
- end
- end
-end
diff --git a/src/mainboard/a-trend/atc-6220/irq_tables.c b/src/mainboard/a-trend/atc-6220/irq_tables.c
deleted file mode 100644
index c1b42e4..0000000
--- a/src/mainboard/a-trend/atc-6220/irq_tables.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- (0x07 << 3) | 0x0, /* Interrupt router device */
- 0x600, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x7000, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x4e, /* Checksum */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
- {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
- {0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
- {0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
- {0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
- {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
- {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c
deleted file mode 100644
index 70bc5d8..0000000
--- a/src/mainboard/a-trend/atc-6220/romstage.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb.h"
-#include "northbridge/intel/i440bx/raminit.h"
-#include "drivers/pc80/udelay_io.c"
-#include "lib/delay.c"
-#include "cpu/x86/bist.h"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83977tf/w83977tf.h>
-
-#include <lib.h>
-
-#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- report_bist_failure(bist);
-
- enable_smbus();
- dump_spd_registers();
- sdram_set_registers();
- sdram_set_spd_registers();
- sdram_enable();
-}
diff --git a/src/mainboard/a-trend/atc-6240/Kconfig b/src/mainboard/a-trend/atc-6240/Kconfig
deleted file mode 100644
index d19f92d..0000000
--- a/src/mainboard/a-trend/atc-6240/Kconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-if BOARD_A_TREND_ATC_6240
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SLOT_1
- select NORTHBRIDGE_INTEL_I440BX
- select SOUTHBRIDGE_INTEL_I82371EB
- select SUPERIO_WINBOND_W83627HF
- select HAVE_PIRQ_TABLE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_256
-
-config MAINBOARD_DIR
- string
- default a-trend/atc-6240
-
-config MAINBOARD_PART_NUMBER
- string
- default "ATC-6240"
-
-config IRQ_SLOT_COUNT
- int
- default 7
-
-endif # BOARD_A_TREND_ATC_6240
diff --git a/src/mainboard/a-trend/atc-6240/board_info.txt b/src/mainboard/a-trend/atc-6240/board_info.txt
deleted file mode 100644
index 1acf41b..0000000
--- a/src/mainboard/a-trend/atc-6240/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: desktop
-Board URL: http://active-hardware.com/english/reviews/mainboard/atc6240.htm
-ROM package: DIP32
-ROM protocol: Parallel
diff --git a/src/mainboard/a-trend/atc-6240/devicetree.cb b/src/mainboard/a-trend/atc-6240/devicetree.cb
deleted file mode 100644
index e0bfdac..0000000
--- a/src/mainboard/a-trend/atc-6240/devicetree.cb
+++ /dev/null
@@ -1,69 +0,0 @@
-chip northbridge/intel/i440bx # Northbridge
- device cpu_cluster 0 on # APIC cluster
- chip cpu/intel/slot_1 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- device pci 1.0 on end # PCI/AGP bridge
- chip southbridge/intel/i82371eb # Southbridge
- device pci 7.0 on # ISA bridge
- chip superio/winbond/w83627hf # Super I/O
- device pnp 3f0.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 3f0.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 3f0.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 3f0.3 on # COM2 / IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 3f0.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard interrupt
- irq 0x72 = 12 # PS/2 mouse interrupt
- end
- device pnp 3f0.6 on # Consumer IR
- io 0x60 = 0x00
- end
- device pnp 3f0.7 on # Game port / MIDI / GPIO 1
- io 0x60 = 0x201
- io 0x62 = 0x330
- irq 0x70 = 9
- end
- device pnp 3f0.8 off # GPIO 2 / WDT
- end
- device pnp 3f0.9 off # GPIO 3
- end
- device pnp 3f0.a off # ACPI
- end
- device pnp 3f0.b off # HWM (TODO)
- end
- end
- end
- device pci 7.1 on end # IDE
- device pci 7.2 on end # USB
- device pci 7.3 on end # ACPI
- device pci c.0 on end # Onboard audio (ES1371)
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "ide_legacy_enable" = "1"
- # Enable UDMA/33 for higher speed if your IDE device(s) support it.
- register "ide0_drive0_udma33_enable" = "0"
- register "ide0_drive1_udma33_enable" = "0"
- register "ide1_drive0_udma33_enable" = "0"
- register "ide1_drive1_udma33_enable" = "0"
- end
- end
-end
diff --git a/src/mainboard/a-trend/atc-6240/irq_tables.c b/src/mainboard/a-trend/atc-6240/irq_tables.c
deleted file mode 100644
index 3383056..0000000
--- a/src/mainboard/a-trend/atc-6240/irq_tables.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- (0x07 << 3) | 0x0, /* Interrupt router device */
- 0xc20, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x7000, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x44, /* Checksum */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
- {0x00,(0x0e<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x2, 0x0},
- {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0},
- {0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0},
- {0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0},
- {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
- {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c
deleted file mode 100644
index 392f40f..0000000
--- a/src/mainboard/a-trend/atc-6240/romstage.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb.h"
-#include "northbridge/intel/i440bx/raminit.h"
-#include "drivers/pc80/udelay_io.c"
-#include "lib/delay.c"
-#include "cpu/x86/bist.h"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <lib.h>
-
-#define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- report_bist_failure(bist);
-
- enable_smbus();
- dump_spd_registers();
- sdram_set_registers();
- sdram_set_spd_registers();
- sdram_enable();
-}
diff --git a/src/mainboard/a_trend/Kconfig b/src/mainboard/a_trend/Kconfig
new file mode 100644
index 0000000..e7a154d
--- /dev/null
+++ b/src/mainboard/a_trend/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+if VENDOR_A_TREND
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_A_TREND_ATC_6220
+ bool "ATC-6220"
+config BOARD_A_TREND_ATC_6240
+ bool "ATC-6240"
+
+endchoice
+
+source "src/mainboard/a_trend/atc-6220/Kconfig"
+source "src/mainboard/a_trend/atc-6240/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "A-Trend"
+
+endif # VENDOR_A_TREND
diff --git a/src/mainboard/a_trend/atc-6220/Kconfig b/src/mainboard/a_trend/atc-6220/Kconfig
new file mode 100644
index 0000000..982271d
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6220/Kconfig
@@ -0,0 +1,43 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+if BOARD_A_TREND_ATC_6220
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_SLOT_1
+ select NORTHBRIDGE_INTEL_I440BX
+ select SOUTHBRIDGE_INTEL_I82371EB
+ select SUPERIO_WINBOND_W83977TF
+ select HAVE_PIRQ_TABLE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_256
+
+config MAINBOARD_DIR
+ string
+ default a_trend/atc-6220
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ATC-6220"
+
+config IRQ_SLOT_COUNT
+ int
+ default 7
+
+endif # BOARD_A_TREND_ATC_6220
diff --git a/src/mainboard/a_trend/atc-6220/board_info.txt b/src/mainboard/a_trend/atc-6220/board_info.txt
new file mode 100644
index 0000000..a56cca3
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6220/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: http://www.motherboard.cz/mb/atrend/atc6220.htm
+ROM package: DIP32
+ROM protocol: Parallel
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/a_trend/atc-6220/devicetree.cb b/src/mainboard/a_trend/atc-6220/devicetree.cb
new file mode 100644
index 0000000..0dea9ae
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6220/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_1 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # Consumer IR
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/a_trend/atc-6220/irq_tables.c b/src/mainboard/a_trend/atc-6220/irq_tables.c
new file mode 100644
index 0000000..c1b42e4
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6220/irq_tables.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x07 << 3) | 0x0, /* Interrupt router device */
+ 0x600, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x7000, /* Device */
+ 0, /* Miniport data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x4e, /* Checksum */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
+ {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
+ {0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
+ {0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
+ {0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
+ {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+ {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/a_trend/atc-6220/romstage.c b/src/mainboard/a_trend/atc-6220/romstage.c
new file mode 100644
index 0000000..70bc5d8
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6220/romstage.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include "southbridge/intel/i82371eb/i82371eb.h"
+#include "northbridge/intel/i440bx/raminit.h"
+#include "drivers/pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/bist.h"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83977tf/w83977tf.h>
+
+#include <lib.h>
+
+#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ report_bist_failure(bist);
+
+ enable_smbus();
+ dump_spd_registers();
+ sdram_set_registers();
+ sdram_set_spd_registers();
+ sdram_enable();
+}
diff --git a/src/mainboard/a_trend/atc-6240/Kconfig b/src/mainboard/a_trend/atc-6240/Kconfig
new file mode 100644
index 0000000..776768b
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6240/Kconfig
@@ -0,0 +1,43 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+if BOARD_A_TREND_ATC_6240
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_SLOT_1
+ select NORTHBRIDGE_INTEL_I440BX
+ select SOUTHBRIDGE_INTEL_I82371EB
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_256
+
+config MAINBOARD_DIR
+ string
+ default a_trend/atc-6240
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ATC-6240"
+
+config IRQ_SLOT_COUNT
+ int
+ default 7
+
+endif # BOARD_A_TREND_ATC_6240
diff --git a/src/mainboard/a_trend/atc-6240/board_info.txt b/src/mainboard/a_trend/atc-6240/board_info.txt
new file mode 100644
index 0000000..1acf41b
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6240/board_info.txt
@@ -0,0 +1,4 @@
+Category: desktop
+Board URL: http://active-hardware.com/english/reviews/mainboard/atc6240.htm
+ROM package: DIP32
+ROM protocol: Parallel
diff --git a/src/mainboard/a_trend/atc-6240/devicetree.cb b/src/mainboard/a_trend/atc-6240/devicetree.cb
new file mode 100644
index 0000000..e0bfdac
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6240/devicetree.cb
@@ -0,0 +1,69 @@
+chip northbridge/intel/i440bx # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_1 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/winbond/w83627hf # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # Consumer IR
+ io 0x60 = 0x00
+ end
+ device pnp 3f0.7 on # Game port / MIDI / GPIO 1
+ io 0x60 = 0x201
+ io 0x62 = 0x330
+ irq 0x70 = 9
+ end
+ device pnp 3f0.8 off # GPIO 2 / WDT
+ end
+ device pnp 3f0.9 off # GPIO 3
+ end
+ device pnp 3f0.a off # ACPI
+ end
+ device pnp 3f0.b off # HWM (TODO)
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ device pci c.0 on end # Onboard audio (ES1371)
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/a_trend/atc-6240/irq_tables.c b/src/mainboard/a_trend/atc-6240/irq_tables.c
new file mode 100644
index 0000000..3383056
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6240/irq_tables.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x07 << 3) | 0x0, /* Interrupt router device */
+ 0xc20, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x7000, /* Device */
+ 0, /* Miniport data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x44, /* Checksum */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
+ {0x00,(0x0e<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x2, 0x0},
+ {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0},
+ {0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0},
+ {0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0},
+ {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+ {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/a_trend/atc-6240/romstage.c b/src/mainboard/a_trend/atc-6240/romstage.c
new file mode 100644
index 0000000..392f40f
--- /dev/null
+++ b/src/mainboard/a_trend/atc-6240/romstage.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "southbridge/intel/i82371eb/i82371eb.h"
+#include "northbridge/intel/i440bx/raminit.h"
+#include "drivers/pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/bist.h"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+#include <lib.h>
+
+#define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ report_bist_failure(bist);
+
+ enable_smbus();
+ dump_spd_registers();
+ sdram_set_registers();
+ sdram_set_spd_registers();
+ sdram_enable();
+}
diff --git a/src/mainboard/artec_group/Kconfig b/src/mainboard/artec_group/Kconfig
new file mode 100644
index 0000000..c5b98ec
--- /dev/null
+++ b/src/mainboard/artec_group/Kconfig
@@ -0,0 +1,19 @@
+if VENDOR_ARTEC_GROUP
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_ARTEC_GROUP_DBE61
+ bool "DBE61"
+
+endchoice
+
+config MAINBOARD_VENDOR
+ string
+ default "Artec Group"
+
+endif # VENDOR_ARTEC_GROUP
+
+if VENDOR_ARTEC_GROUP || VENDOR_LINUTOP
+source "src/mainboard/artec_group/dbe61/Kconfig"
+endif # VENDOR_ARTEC_GROUP || VENDOR_LINUTOP
diff --git a/src/mainboard/artec_group/dbe61/Kconfig b/src/mainboard/artec_group/dbe61/Kconfig
new file mode 100644
index 0000000..5266e15
--- /dev/null
+++ b/src/mainboard/artec_group/dbe61/Kconfig
@@ -0,0 +1,28 @@
+if BOARD_ARTEC_GROUP_DBE61 || BOARD_LINUTOP_LINUTOP1
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_GEODE_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_256
+ select POWER_BUTTON_FORCE_DISABLE
+
+config MAINBOARD_DIR
+ string
+ default artec_group/dbe61
+
+if BOARD_ARTEC_GROUP_DBE61
+config MAINBOARD_PART_NUMBER
+ string
+ default "DBE61"
+endif
+
+config IRQ_SLOT_COUNT
+ int
+ default 3
+
+endif # BOARD_ARTEC_GROUP_DBE61
diff --git a/src/mainboard/artec_group/dbe61/board_info.txt b/src/mainboard/artec_group/dbe61/board_info.txt
new file mode 100644
index 0000000..67ffbf9
--- /dev/null
+++ b/src/mainboard/artec_group/dbe61/board_info.txt
@@ -0,0 +1,3 @@
+Category: settop
+Board URL: http://www.artec_group.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34
+Flashrom support: y
diff --git a/src/mainboard/artec_group/dbe61/cmos.layout b/src/mainboard/artec_group/dbe61/cmos.layout
new file mode 100644
index 0000000..9050c3d
--- /dev/null
+++ b/src/mainboard/artec_group/dbe61/cmos.layout
@@ -0,0 +1,72 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/artec_group/dbe61/devicetree.cb b/src/mainboard/artec_group/dbe61/devicetree.cb
new file mode 100644
index 0000000..d270f3d
--- /dev/null
+++ b/src/mainboard/artec_group/dbe61/devicetree.cb
@@ -0,0 +1,42 @@
+chip northbridge/amd/lx
+ device domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ register "lpc_serirq_enable" = "0x00001002"
+ register "lpc_serirq_polarity" = "0x0000EFFD"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x2F8"
+ register "com1_irq" = "3"
+ register "com2_enable" = "1"
+ register "com2_address" = "0x3F8"
+ register "com2_irq" = "4"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci b.0 on end # Slot 3
+ device pci c.0 on end # Slot 4
+ device pci d.0 on end # Slot 1
+ device pci e.0 on end # Slot 2
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device cpu_cluster 0 on
+ chip cpu/amd/geode_lx
+ device lapic 0 on end
+ end
+ end
+
+end
+
diff --git a/src/mainboard/artec_group/dbe61/irq_tables.c b/src/mainboard/artec_group/dbe61/irq_tables.c
new file mode 100644
index 0000000..0f21913
--- /dev/null
+++ b/src/mainboard/artec_group/dbe61/irq_tables.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 10
+#define PIRQB 11
+#define PIRQC 10
+#define PIRQD 11
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Miniport data */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/artec_group/dbe61/mainboard.c b/src/mainboard/artec_group/dbe61/mainboard.c
new file mode 100644
index 0000000..cd824d0
--- /dev/null
+++ b/src/mainboard/artec_group/dbe61/mainboard.c
@@ -0,0 +1,56 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/lxdef.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+static void init_gpio(void)
+{
+ msr_t msr;
+ printk(BIOS_DEBUG, "Checking GPIO module...\n");
+
+ msr = rdmsr(MDD_LBAR_GPIO);
+ printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
+}
+
+static void init(struct device *dev)
+{
+ // BOARD-SPECIFIC INIT
+ printk(BIOS_DEBUG, "ARTEC_GROUP DBE61 ENTER %s\n", __func__);
+
+ init_gpio();
+
+ printk(BIOS_DEBUG, "ARTEC_GROUP DBE61 EXIT %s\n", __func__);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/artec_group/dbe61/romstage.c b/src/mainboard/artec_group/dbe61/romstage.c
new file mode 100644
index 0000000..343351f
--- /dev/null
+++ b/src/mainboard/artec_group/dbe61/romstage.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include "spd_table.h"
+#include <spd.h>
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include "northbridge/amd/lx/raminit.h"
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ int i;
+
+ if (device == DIMM0) {
+ for (i=0; i < (ARRAY_SIZE(spd_table)); i++) {
+ if (spd_table[i].address == address) {
+ return spd_table[i].data;
+ }
+ }
+ }
+
+ /* returns 0xFF on any failures */
+ return 0xFF;
+}
+
+#include "northbridge/amd/lx/pll_reset.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+
+ msr_t msr;
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0, DIMM1}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* NOTE: must do this AFTER the early_setup!
+ * it is counting on some early MSR setup
+ * for cs5536
+ */
+ /* cs5536_disable_internal_uart disable them. Set them up now... */
+ cs5536_setup_onchipuart(2); /* dbe61 uses UART2 as COM1 */
+ /* set address to 3F8 */
+ msr = rdmsr(MDD_LEG_IO);
+ msr.lo |= 0x7 << 20;
+ wrmsr(MDD_LEG_IO, msr);
+
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset();
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Dump memory configuration. */
+#if 0
+ msr = rdmsr(MC_CF07_DATA);
+ print_debug("MC_CF07_DATA: ");
+ print_debug_hex32(MC_CF07_DATA);
+ print_debug(" value is: ");
+ print_debug_hex32(msr.hi);
+ print_debug(":");
+ print_debug_hex32(msr.lo);
+ print_debug("\n");
+
+ msr = rdmsr(MC_CF1017_DATA);
+ print_debug("MC_CF1017_DATA: ");
+ print_debug_hex32(MC_CF1017_DATA);
+ print_debug(" value is: ");
+ print_debug_hex32(msr.hi);
+ print_debug(":");
+ print_debug_hex32(msr.lo);
+ print_debug("\n");
+
+ msr = rdmsr(MC_CF8F_DATA);
+ print_debug("MC_CF8F_DATA: ");
+ print_debug_hex32(MC_CF8F_DATA);
+ print_debug(" value is: ");
+ print_debug_hex32(msr.hi);
+ print_debug(":");
+ print_debug_hex32(msr.lo);
+ msr = rdmsr(MC_CF8F_DATA);
+ print_debug("\n");
+#endif
+}
diff --git a/src/mainboard/artec_group/dbe61/spd_table.h b/src/mainboard/artec_group/dbe61/spd_table.h
new file mode 100644
index 0000000..3d45b6f
--- /dev/null
+++ b/src/mainboard/artec_group/dbe61/spd_table.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <spd.h>
+
+struct spd_entry {
+ unsigned int address;
+ unsigned int data;
+ };
+
+/* Save space by using a short list of SPD values used by Geode LX Memory init */
+/* 128MB */
+const struct spd_entry spd_table [] =
+{
+{SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */
+{SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */
+{SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
+{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
+{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x50}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
+{SPD_REFRESH, 0x82}, /* Refresh rate/type */
+{SPD_PRIMARY_SDRAM_WIDTH, 0x08}, /* SDRAM width (primary SDRAM) */
+{SPD_NUM_BANKS_PER_SDRAM, 0x04}, /* SDRAM device attributes, number of banks on SDRAM device */
+{SPD_ACCEPTABLE_CAS_LATENCIES, 0x1C}, /* SDRAM device attributes, CAS latency */
+{SPD_MODULE_ATTRIBUTES, 0x20}, /* SDRAM module attributes */
+{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xC0}, /* SDRAM device attributes, general */
+{SPD_SDRAM_CYCLE_TIME_2ND, 0x60}, /* SDRAM cycle time (2nd highest CAS latency) */
+{SPD_SDRAM_CYCLE_TIME_3RD, 0x75}, /* SDRAM cycle time (3rd highest CAS latency) */
+{SPD_MIN_ROW_PRECHARGE_TIME, 0x3C}, /* Minimum row precharge time (Trp) */
+{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x28}, /* Minimum row active to row active (Trrd) */
+{SPD_MIN_RAS_TO_CAS_DELAY, 0x3C}, /* Minimum RAS to CAS delay (Trcd) */
+{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x28}, /* Minimum RAS pulse width (Tras) */
+{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */
+{SPD_CMD_SIGNAL_INPUT_HOLD_TIME, 0x60}, /* Command and address signal input hold time */
+{SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
+{SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
+};
diff --git a/src/mainboard/artecgroup/Kconfig b/src/mainboard/artecgroup/Kconfig
deleted file mode 100644
index f2d0d32..0000000
--- a/src/mainboard/artecgroup/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if VENDOR_ARTECGROUP
-
-choice
- prompt "Mainboard model"
-
-config BOARD_ARTECGROUP_DBE61
- bool "DBE61"
-
-endchoice
-
-config MAINBOARD_VENDOR
- string
- default "Artec Group"
-
-endif # VENDOR_ARTECGROUP
-
-if VENDOR_ARTECGROUP || VENDOR_LINUTOP
-source "src/mainboard/artecgroup/dbe61/Kconfig"
-endif # VENDOR_ARTECGROUP || VENDOR_LINUTOP
diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig
deleted file mode 100644
index c512f7b..0000000
--- a/src/mainboard/artecgroup/dbe61/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-if BOARD_ARTECGROUP_DBE61 || BOARD_LINUTOP_LINUTOP1
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_GEODE_LX
- select NORTHBRIDGE_AMD_LX
- select SOUTHBRIDGE_AMD_CS5536
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_256
- select POWER_BUTTON_FORCE_DISABLE
-
-config MAINBOARD_DIR
- string
- default artecgroup/dbe61
-
-if BOARD_ARTECGROUP_DBE61
-config MAINBOARD_PART_NUMBER
- string
- default "DBE61"
-endif
-
-config IRQ_SLOT_COUNT
- int
- default 3
-
-endif # BOARD_ARTECGROUP_DBE61
diff --git a/src/mainboard/artecgroup/dbe61/board_info.txt b/src/mainboard/artecgroup/dbe61/board_info.txt
deleted file mode 100644
index d059a75..0000000
--- a/src/mainboard/artecgroup/dbe61/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: settop
-Board URL: http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34
-Flashrom support: y
diff --git a/src/mainboard/artecgroup/dbe61/cmos.layout b/src/mainboard/artecgroup/dbe61/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/artecgroup/dbe61/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb
deleted file mode 100644
index d270f3d..0000000
--- a/src/mainboard/artecgroup/dbe61/devicetree.cb
+++ /dev/null
@@ -1,42 +0,0 @@
-chip northbridge/amd/lx
- device domain 0 on
- device pci 1.0 on end # Northbridge
- device pci 1.1 on end # Graphics
- chip southbridge/amd/cs5536
- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
- # SIRQ Mode = Active(Quiet) mode. Save power....
- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
- register "lpc_serirq_enable" = "0x00001002"
- register "lpc_serirq_polarity" = "0x0000EFFD"
- register "lpc_serirq_mode" = "1"
- register "enable_gpio_int_route" = "0x0D0C0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "0" #0: host, 1:device
- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "0"
- register "com1_address" = "0x2F8"
- register "com1_irq" = "3"
- register "com2_enable" = "1"
- register "com2_address" = "0x3F8"
- register "com2_irq" = "4"
- register "unwanted_vpci[0]" = "0" # End of list has a zero
- device pci b.0 on end # Slot 3
- device pci c.0 on end # Slot 4
- device pci d.0 on end # Slot 1
- device pci e.0 on end # Slot 2
- device pci f.0 on end # ISA Bridge
- device pci f.2 on end # IDE Controller
- device pci f.3 on end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
- # APIC cluster is late CPU init.
- device cpu_cluster 0 on
- chip cpu/amd/geode_lx
- device lapic 0 on end
- end
- end
-
-end
-
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
deleted file mode 100644
index 0f21913..0000000
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 10
-#define PIRQB 11
-#define PIRQC 10
-#define PIRQD 11
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Miniport data */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
- {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/artecgroup/dbe61/mainboard.c b/src/mainboard/artecgroup/dbe61/mainboard.c
deleted file mode 100644
index 692d2ab..0000000
--- a/src/mainboard/artecgroup/dbe61/mainboard.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright (C) 2007 Advanced Micro Devices
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-static void init_gpio(void)
-{
- msr_t msr;
- printk(BIOS_DEBUG, "Checking GPIO module...\n");
-
- msr = rdmsr(MDD_LBAR_GPIO);
- printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
-}
-
-static void init(struct device *dev)
-{
- // BOARD-SPECIFIC INIT
- printk(BIOS_DEBUG, "ARTECGROUP DBE61 ENTER %s\n", __func__);
-
- init_gpio();
-
- printk(BIOS_DEBUG, "ARTECGROUP DBE61 EXIT %s\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
deleted file mode 100644
index 343351f..0000000
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/lxdef.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-#include "spd_table.h"
-#include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
-#include "northbridge/amd/lx/raminit.h"
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- int i;
-
- if (device == DIMM0) {
- for (i=0; i < (ARRAY_SIZE(spd_table)); i++) {
- if (spd_table[i].address == address) {
- return spd_table[i].data;
- }
- }
- }
-
- /* returns 0xFF on any failures */
- return 0xFF;
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
-
- msr_t msr;
- static const struct mem_controller memctrl[] = {
- {.channel0 = {DIMM0, DIMM1}}
- };
-
- SystemPreInit();
- msr_init();
-
- cs5536_early_setup();
-
- /* NOTE: must do this AFTER the early_setup!
- * it is counting on some early MSR setup
- * for cs5536
- */
- /* cs5536_disable_internal_uart disable them. Set them up now... */
- cs5536_setup_onchipuart(2); /* dbe61 uses UART2 as COM1 */
- /* set address to 3F8 */
- msr = rdmsr(MDD_LEG_IO);
- msr.lo |= 0x7 << 20;
- wrmsr(MDD_LEG_IO, msr);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pll_reset();
-
- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
- sdram_initialize(1, memctrl);
-
- /* Dump memory configuration. */
-#if 0
- msr = rdmsr(MC_CF07_DATA);
- print_debug("MC_CF07_DATA: ");
- print_debug_hex32(MC_CF07_DATA);
- print_debug(" value is: ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- print_debug("\n");
-
- msr = rdmsr(MC_CF1017_DATA);
- print_debug("MC_CF1017_DATA: ");
- print_debug_hex32(MC_CF1017_DATA);
- print_debug(" value is: ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- print_debug("\n");
-
- msr = rdmsr(MC_CF8F_DATA);
- print_debug("MC_CF8F_DATA: ");
- print_debug_hex32(MC_CF8F_DATA);
- print_debug(" value is: ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- msr = rdmsr(MC_CF8F_DATA);
- print_debug("\n");
-#endif
-}
diff --git a/src/mainboard/artecgroup/dbe61/spd_table.h b/src/mainboard/artecgroup/dbe61/spd_table.h
deleted file mode 100644
index 3d45b6f..0000000
--- a/src/mainboard/artecgroup/dbe61/spd_table.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <spd.h>
-
-struct spd_entry {
- unsigned int address;
- unsigned int data;
- };
-
-/* Save space by using a short list of SPD values used by Geode LX Memory init */
-/* 128MB */
-const struct spd_entry spd_table [] =
-{
-{SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */
-{SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */
-{SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
-{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
-{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x50}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
-{SPD_REFRESH, 0x82}, /* Refresh rate/type */
-{SPD_PRIMARY_SDRAM_WIDTH, 0x08}, /* SDRAM width (primary SDRAM) */
-{SPD_NUM_BANKS_PER_SDRAM, 0x04}, /* SDRAM device attributes, number of banks on SDRAM device */
-{SPD_ACCEPTABLE_CAS_LATENCIES, 0x1C}, /* SDRAM device attributes, CAS latency */
-{SPD_MODULE_ATTRIBUTES, 0x20}, /* SDRAM module attributes */
-{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xC0}, /* SDRAM device attributes, general */
-{SPD_SDRAM_CYCLE_TIME_2ND, 0x60}, /* SDRAM cycle time (2nd highest CAS latency) */
-{SPD_SDRAM_CYCLE_TIME_3RD, 0x75}, /* SDRAM cycle time (3rd highest CAS latency) */
-{SPD_MIN_ROW_PRECHARGE_TIME, 0x3C}, /* Minimum row precharge time (Trp) */
-{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x28}, /* Minimum row active to row active (Trrd) */
-{SPD_MIN_RAS_TO_CAS_DELAY, 0x3C}, /* Minimum RAS to CAS delay (Trcd) */
-{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x28}, /* Minimum RAS pulse width (Tras) */
-{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */
-{SPD_CMD_SIGNAL_INPUT_HOLD_TIME, 0x60}, /* Command and address signal input hold time */
-{SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
-{SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
-};
diff --git a/src/mainboard/bachmann/Kconfig b/src/mainboard/bachmann/Kconfig
deleted file mode 100644
index ee61049..0000000
--- a/src/mainboard/bachmann/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if VENDOR_BACHMANN
-
-choice
- prompt "Mainboard model"
-
-config BOARD_BACHMANN_OT200
- bool "OT200"
-
-endchoice
-
-source "src/mainboard/bachmann/ot200/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Bachmann electronic"
-
-endif # VENDOR_BACHMANN
diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig
deleted file mode 100644
index baef807..0000000
--- a/src/mainboard/bachmann/ot200/Kconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-if BOARD_BACHMANN_OT200
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_GEODE_LX
- select NORTHBRIDGE_AMD_LX
- select SOUTHBRIDGE_AMD_CS5536
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_2048
- select POWER_BUTTON_DEFAULT_DISABLE
- select DRIVERS_I2C_IDREG
- select PLL_MANUAL_CONFIG
- select CORE_GLIU_500_266
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
-
-config MAINBOARD_DIR
- string
- default bachmann/ot200
-
-config MAINBOARD_PART_NUMBER
- string
- default "OT200"
-
-config IRQ_SLOT_COUNT
- int
- default 6
-
-config PLLMSRlo
- hex
- default 0x07de001e
-
-endif # BOARD_BACHMANN_OT200
diff --git a/src/mainboard/bachmann/ot200/board_info.txt b/src/mainboard/bachmann/ot200/board_info.txt
deleted file mode 100644
index 0ba2657..0000000
--- a/src/mainboard/bachmann/ot200/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: settop
diff --git a/src/mainboard/bachmann/ot200/cmos.default b/src/mainboard/bachmann/ot200/cmos.default
deleted file mode 100644
index 05eadbf..0000000
--- a/src/mainboard/bachmann/ot200/cmos.default
+++ /dev/null
@@ -1,4 +0,0 @@
-boot_option=Fallback
-last_boot=Fallback
-baud_rate=115200
-debug_level=Spew
diff --git a/src/mainboard/bachmann/ot200/cmos.layout b/src/mainboard/bachmann/ot200/cmos.layout
deleted file mode 100644
index f5a3170..0000000
--- a/src/mainboard/bachmann/ot200/cmos.layout
+++ /dev/null
@@ -1,64 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Bachmann electronic GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-entries
-
-#start-bit length config config-ID name
-# -----------------------------------------------------------------
-# RTC reserved
-0 384 r 0 reserved_memory
-
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-388 4 r 0 reboot_bits
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392 3 e 1 baud_rate
-395 4 e 2 debug_level
-
-# -----------------------------------------------------------------
-# coreboot config options: check sums
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 115200
-1 1 57600
-1 2 38400
-1 3 19200
-1 4 9600
-1 5 4800
-1 6 2400
-1 7 1200
-2 0 Emergency
-2 1 Alert
-2 2 Critical
-2 3 Error
-2 4 Warning
-2 5 Notice
-2 6 Info
-2 7 Debug
-2 8 Spew
-4 0 Fallback
-4 1 Normal
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/bachmann/ot200/devicetree.cb b/src/mainboard/bachmann/ot200/devicetree.cb
deleted file mode 100644
index 1e61b3d..0000000
--- a/src/mainboard/bachmann/ot200/devicetree.cb
+++ /dev/null
@@ -1,40 +0,0 @@
-chip northbridge/amd/lx
- device domain 0 on
- device pci 1.0 on end # Northbridge
- device pci 1.1 on end # Graphics
- device pci 1.2 on end # AES
- chip southbridge/amd/cs5536
- register "lpc_serirq_enable" = "0x00000000"
- register "lpc_serirq_polarity" = "0x00000000"
- register "lpc_serirq_mode" = "0"
- register "enable_gpio_int_route" = "0x0C0D0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "0" #0: host, 1:device
- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "1"
- register "com1_address" = "0x3F8"
- register "com1_irq" = "4"
- register "com2_enable" = "1"
- register "com2_address" = "0x2F8"
- register "com2_irq" = "3"
- register "unwanted_vpci[0]" = "0" # End of list has a zero
- device pci 4.0 on end # Ethernet 0
- device pci f.0 on # ISA Bridge
- chip drivers/generic/generic # eeprom
- device i2c 52 on end
- end
- end
- device pci f.2 on end # IDE Controller
- device pci f.3 on end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- device pci f.7 on end # UOC
- end
- end
- # APIC cluster is late CPU init.
- device cpu_cluster 0 on
- chip cpu/amd/geode_lx
- device lapic 0 on end
- end
- end
-end
diff --git a/src/mainboard/bachmann/ot200/irq_tables.c b/src/mainboard/bachmann/ot200/irq_tables.c
deleted file mode 100644
index 428032f..0000000
--- a/src/mainboard/bachmann/ot200/irq_tables.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Bachmann electronic GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-
-/* Platform IRQs */
-#define PIRQA 5
-#define PIRQB 9
-#define PIRQC 10
-#define PIRQD 7
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- 0x0f << 3, /* Interrupt router dev */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x100b, /* Vendor */
- 0x2b, /* Device */
- 0, /* Miniport */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x20, /* Checksum (has to be set to some value that
- * would give 0 after the sum of all bytes
- * for this structure (including checksum).
- */
- {
- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* CPU */
- {0x00, (0x0f << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
- {0x00, (0x04 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* ethernet */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c
deleted file mode 100644
index d4b0b2d..0000000
--- a/src/mainboard/bachmann/ot200/mainboard.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Bachmann electronic GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/smbus.h>
-#include <smbios.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <arch/io.h>
-
-/* overwrite a weak function to fill SMBIOS table with a custom value */
-static u8 hw_rev = 0;
-static char mb_rev_str[2] = { '0' };
-
-const char *smbios_mainboard_version(void)
-{
- /* UDMA is not working on all supported devices */
- if (hw_rev < 113) {
- mb_rev_str[0] = '1';
- } else {
- mb_rev_str[0] = '2';
- }
-
- return mb_rev_str;
-}
-
-static void init(struct device *dev)
-{
- unsigned int i;
- u32 chksum = 0;
- char block[20];
- msr_t reset;
- device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52);
-
- if (eeprom_dev == 0) {
- printk(BIOS_WARNING, "eeprom not found\n");
- return;
- }
-
- /* turn off all leds except led_ini */
- outb(0x02, 0x5a); /* bit0 - led_run */
- /* bit1 - led_ini */
- /* bit2 - led_err */
- /* bit3-bit7 - write has no effect */
- outb(0x00, 0x49); /* bit0-bit6 - led_7-led_1 */
- /* bit7 - write has no effect */
-
- /* read the whole block and check if checksum is okay */
- for (i = 0; i < 20; i++) {
- block[i] = smbus_read_byte(eeprom_dev, i);
- chksum += block[i];
- }
-
- if (chksum != 0) {
- printk(BIOS_WARNING, "wrong checksum: 0x%0x\n", chksum);
- }
-
- hw_rev = block[5];
-
- printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev);
-
- /* Reset MFGPT7 (standby power domain) - this is done via
- * an undocumented register */
- reset = rdmsr(0x5140002b);
- reset.lo |= 1 << 7;
- wrmsr(0x5140002b, reset);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c
deleted file mode 100644
index 849479c..0000000
--- a/src/mainboard/bachmann/ot200/romstage.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Bachmann electronic GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <spd.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <console/console.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/lxdef.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
-#include "northbridge/amd/lx/raminit.h"
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- static const struct mem_controller memctrl[] = {
- {.channel0 = {DIMM0}}
- };
-
- SystemPreInit();
- msr_init();
-
- cs5536_early_setup();
-
- /* Note: must do this AFTER the early_setup! It is counting on some
- * early MSR setup for CS5536.
- */
- /* cs5536_disable_internal_uart: disable them for now, set them
- * up later...
- */
- /* If debug. real setup done in chipset init via devicetree.cb. */
- cs5536_setup_onchipuart(1);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pll_reset();
-
- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
- sdram_initialize(1, memctrl);
-
- /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
- return;
-}
diff --git a/src/mainboard/bachmann_electronic/Kconfig b/src/mainboard/bachmann_electronic/Kconfig
new file mode 100644
index 0000000..ea53b77
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/Kconfig
@@ -0,0 +1,17 @@
+if VENDOR_BACHMANN_ELECTRONIC
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_BACHMANN_ELECTRONIC_OT200
+ bool "OT200"
+
+endchoice
+
+source "src/mainboard/bachmann_electronic/ot200/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Bachmann electronic"
+
+endif # VENDOR_BACHMANN_ELECTRONIC
diff --git a/src/mainboard/bachmann_electronic/ot200/Kconfig b/src/mainboard/bachmann_electronic/ot200/Kconfig
new file mode 100644
index 0000000..4143de9
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/ot200/Kconfig
@@ -0,0 +1,35 @@
+if BOARD_BACHMANN_ELECTRONIC_OT200
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_GEODE_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_2048
+ select POWER_BUTTON_DEFAULT_DISABLE
+ select DRIVERS_I2C_IDREG
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_266
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+
+config MAINBOARD_DIR
+ string
+ default bachmann_electronic/ot200
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "OT200"
+
+config IRQ_SLOT_COUNT
+ int
+ default 6
+
+config PLLMSRlo
+ hex
+ default 0x07de001e
+
+endif # BOARD_BACHMANN_ELECTRONIC_OT200
diff --git a/src/mainboard/bachmann_electronic/ot200/board_info.txt b/src/mainboard/bachmann_electronic/ot200/board_info.txt
new file mode 100644
index 0000000..0ba2657
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/ot200/board_info.txt
@@ -0,0 +1 @@
+Category: settop
diff --git a/src/mainboard/bachmann_electronic/ot200/cmos.default b/src/mainboard/bachmann_electronic/ot200/cmos.default
new file mode 100644
index 0000000..05eadbf
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/ot200/cmos.default
@@ -0,0 +1,4 @@
+boot_option=Fallback
+last_boot=Fallback
+baud_rate=115200
+debug_level=Spew
diff --git a/src/mainboard/bachmann_electronic/ot200/cmos.layout b/src/mainboard/bachmann_electronic/ot200/cmos.layout
new file mode 100644
index 0000000..f5a3170
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/ot200/cmos.layout
@@ -0,0 +1,64 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Bachmann electronic GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+entries
+
+#start-bit length config config-ID name
+# -----------------------------------------------------------------
+# RTC reserved
+0 384 r 0 reserved_memory
+
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 1 baud_rate
+395 4 e 2 debug_level
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 115200
+1 1 57600
+1 2 38400
+1 3 19200
+1 4 9600
+1 5 4800
+1 6 2400
+1 7 1200
+2 0 Emergency
+2 1 Alert
+2 2 Critical
+2 3 Error
+2 4 Warning
+2 5 Notice
+2 6 Info
+2 7 Debug
+2 8 Spew
+4 0 Fallback
+4 1 Normal
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/bachmann_electronic/ot200/devicetree.cb b/src/mainboard/bachmann_electronic/ot200/devicetree.cb
new file mode 100644
index 0000000..1e61b3d
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/ot200/devicetree.cb
@@ -0,0 +1,40 @@
+chip northbridge/amd/lx
+ device domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ device pci 1.2 on end # AES
+ chip southbridge/amd/cs5536
+ register "lpc_serirq_enable" = "0x00000000"
+ register "lpc_serirq_polarity" = "0x00000000"
+ register "lpc_serirq_mode" = "0"
+ register "enable_gpio_int_route" = "0x0C0D0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "1"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "1"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci 4.0 on end # Ethernet 0
+ device pci f.0 on # ISA Bridge
+ chip drivers/generic/generic # eeprom
+ device i2c 52 on end
+ end
+ end
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ device pci f.7 on end # UOC
+ end
+ end
+ # APIC cluster is late CPU init.
+ device cpu_cluster 0 on
+ chip cpu/amd/geode_lx
+ device lapic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/bachmann_electronic/ot200/irq_tables.c b/src/mainboard/bachmann_electronic/ot200/irq_tables.c
new file mode 100644
index 0000000..428032f
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/ot200/irq_tables.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Bachmann electronic GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+/* Platform IRQs */
+#define PIRQA 5
+#define PIRQB 9
+#define PIRQC 10
+#define PIRQD 7
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ 0x0f << 3, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x100b, /* Vendor */
+ 0x2b, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x20, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* CPU */
+ {0x00, (0x0f << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
+ {0x00, (0x04 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* ethernet */
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/bachmann_electronic/ot200/mainboard.c b/src/mainboard/bachmann_electronic/ot200/mainboard.c
new file mode 100644
index 0000000..d4b0b2d
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/ot200/mainboard.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Bachmann electronic GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/smbus.h>
+#include <smbios.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <arch/io.h>
+
+/* overwrite a weak function to fill SMBIOS table with a custom value */
+static u8 hw_rev = 0;
+static char mb_rev_str[2] = { '0' };
+
+const char *smbios_mainboard_version(void)
+{
+ /* UDMA is not working on all supported devices */
+ if (hw_rev < 113) {
+ mb_rev_str[0] = '1';
+ } else {
+ mb_rev_str[0] = '2';
+ }
+
+ return mb_rev_str;
+}
+
+static void init(struct device *dev)
+{
+ unsigned int i;
+ u32 chksum = 0;
+ char block[20];
+ msr_t reset;
+ device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52);
+
+ if (eeprom_dev == 0) {
+ printk(BIOS_WARNING, "eeprom not found\n");
+ return;
+ }
+
+ /* turn off all leds except led_ini */
+ outb(0x02, 0x5a); /* bit0 - led_run */
+ /* bit1 - led_ini */
+ /* bit2 - led_err */
+ /* bit3-bit7 - write has no effect */
+ outb(0x00, 0x49); /* bit0-bit6 - led_7-led_1 */
+ /* bit7 - write has no effect */
+
+ /* read the whole block and check if checksum is okay */
+ for (i = 0; i < 20; i++) {
+ block[i] = smbus_read_byte(eeprom_dev, i);
+ chksum += block[i];
+ }
+
+ if (chksum != 0) {
+ printk(BIOS_WARNING, "wrong checksum: 0x%0x\n", chksum);
+ }
+
+ hw_rev = block[5];
+
+ printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev);
+
+ /* Reset MFGPT7 (standby power domain) - this is done via
+ * an undocumented register */
+ reset = rdmsr(0x5140002b);
+ reset.lo |= 1 << 7;
+ wrmsr(0x5140002b, reset);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/bachmann_electronic/ot200/romstage.c b/src/mainboard/bachmann_electronic/ot200/romstage.c
new file mode 100644
index 0000000..849479c
--- /dev/null
+++ b/src/mainboard/bachmann_electronic/ot200/romstage.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Bachmann electronic GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <spd.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include "northbridge/amd/lx/raminit.h"
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/lx/pll_reset.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* Note: must do this AFTER the early_setup! It is counting on some
+ * early MSR setup for CS5536.
+ */
+ /* cs5536_disable_internal_uart: disable them for now, set them
+ * up later...
+ */
+ /* If debug. real setup done in chipset init via devicetree.cb. */
+ cs5536_setup_onchipuart(1);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset();
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
+ return;
+}
diff --git a/src/mainboard/digital_logic/Kconfig b/src/mainboard/digital_logic/Kconfig
new file mode 100644
index 0000000..11b1709
--- /dev/null
+++ b/src/mainboard/digital_logic/Kconfig
@@ -0,0 +1,23 @@
+if VENDOR_DIGITAL_LOGIC
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_DIGITAL_LOGIC_ADL855PC
+ bool "smartModule855"
+config BOARD_DIGITAL_LOGIC_MSM586SEG
+ bool "MSM586SEG"
+config BOARD_DIGITAL_LOGIC_MSM800SEV
+ bool "MSM800SEV"
+
+endchoice
+
+source "src/mainboard/digital_logic/adl855pc/Kconfig"
+source "src/mainboard/digital_logic/msm586seg/Kconfig"
+source "src/mainboard/digital_logic/msm800sev/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "DIGITAL-LOGIC"
+
+endif # VENDOR_DIGITAL_LOGIC
diff --git a/src/mainboard/digital_logic/adl855pc/Kconfig b/src/mainboard/digital_logic/adl855pc/Kconfig
new file mode 100644
index 0000000..a863c4b
--- /dev/null
+++ b/src/mainboard/digital_logic/adl855pc/Kconfig
@@ -0,0 +1,33 @@
+if BOARD_DIGITAL_LOGIC_ADL855PC
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_SOCKET_MPGA479M
+ select NORTHBRIDGE_INTEL_I855
+ select SOUTHBRIDGE_INTEL_I82801DX
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select BOARD_ROMSIZE_KB_1024
+
+config MAINBOARD_DIR
+ string
+ default digital_logic/adl855pc
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "smartModule855"
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+config IRQ_SLOT_COUNT
+ int
+ default 5
+
+endif # BOARD_DIGITAL_LOGIC_ADL855PC
diff --git a/src/mainboard/digital_logic/adl855pc/board_info.txt b/src/mainboard/digital_logic/adl855pc/board_info.txt
new file mode 100644
index 0000000..7680e6f
--- /dev/null
+++ b/src/mainboard/digital_logic/adl855pc/board_info.txt
@@ -0,0 +1 @@
+Category: half
diff --git a/src/mainboard/digital_logic/adl855pc/cmos.layout b/src/mainboard/digital_logic/adl855pc/cmos.layout
new file mode 100644
index 0000000..9050c3d
--- /dev/null
+++ b/src/mainboard/digital_logic/adl855pc/cmos.layout
@@ -0,0 +1,72 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/digital_logic/adl855pc/devicetree.cb b/src/mainboard/digital_logic/adl855pc/devicetree.cb
new file mode 100644
index 0000000..3a9603b
--- /dev/null
+++ b/src/mainboard/digital_logic/adl855pc/devicetree.cb
@@ -0,0 +1,56 @@
+chip northbridge/intel/i855
+ device domain 0 on
+ device pci 0.0 on end
+ device pci 1.0 on end
+ chip southbridge/intel/i82801dx
+# pci 11.0 on end
+# pci 11.1 on end
+# pci 11.2 on end
+# pci 11.3 on end
+# pci 11.4 on end
+# pci 11.5 on end
+# pci 11.6 on end
+# pci 12.0 on end
+ register "enable_usb" = "0"
+ register "enable_native_ide" = "0"
+ chip superio/winbond/w83627hf # link 1
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ end
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_mPGA479M
+ device lapic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/digital_logic/adl855pc/irq_tables.c b/src/mainboard/digital_logic/adl855pc/irq_tables.c
new file mode 100644
index 0000000..94adba1
--- /dev/null
+++ b/src/mainboard/digital_logic/adl855pc/irq_tables.c
@@ -0,0 +1,36 @@
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+ Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0, /* Where the interrupt router lies (bus) */
+ 0x88, /* Where the interrupt router lies (dev) */
+ 0x1c20, /* IRQs devoted exclusively to PCI usage */
+ 0x1106, /* Vendor */
+ 0x8231, /* Device */
+ 0, /* Miniport data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* 8231 ethernet */
+ {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
+ /* 8231 internal */
+ {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
+ /* PCI slot */
+ {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
+ {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
+ {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
+ }
+};
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/digital_logic/adl855pc/romstage.c b/src/mainboard/digital_logic/adl855pc/romstage.c
new file mode 100644
index 0000000..093c60b
--- /dev/null
+++ b/src/mainboard/digital_logic/adl855pc/romstage.c
@@ -0,0 +1,64 @@
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include <lib.h>
+#include "drivers/pc80/udelay_io.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include "southbridge/intel/i82801dx/i82801dx.h"
+#include "northbridge/intel/i855/raminit.h"
+#include "northbridge/intel/i855/debug.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+#include "cpu/x86/bist.h"
+#include <spd.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i855/raminit.c"
+#include "northbridge/intel/i855/reset_test.c"
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+ if (bist == 0) {
+#if 0
+ enable_lapic();
+ init_timer();
+#endif
+ }
+
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+#if 0
+ print_pci_devices();
+#endif
+
+ if (!bios_reset_detected()) {
+ enable_smbus();
+#if 0
+ dump_spd_registers();
+ dump_smbus_registers();
+#endif
+ sdram_set_registers();
+ sdram_set_spd_registers();
+ sdram_enable();
+ }
+
+#if 0
+ dump_pci_devices();
+ dump_pci_device(PCI_DEV(0, 0, 0));
+#endif
+}
diff --git a/src/mainboard/digital_logic/msm586seg/Kconfig b/src/mainboard/digital_logic/msm586seg/Kconfig
new file mode 100644
index 0000000..c2d5a1a
--- /dev/null
+++ b/src/mainboard/digital_logic/msm586seg/Kconfig
@@ -0,0 +1,23 @@
+if BOARD_DIGITAL_LOGIC_MSM586SEG
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_SC520
+ select HAVE_PIRQ_TABLE
+ select HAVE_OPTION_TABLE
+ select BOARD_ROMSIZE_KB_512
+ select ROMCC
+
+config MAINBOARD_DIR
+ string
+ default digital_logic/msm586seg
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MSM586SEG"
+
+config IRQ_SLOT_COUNT
+ int
+ default 2
+
+endif # BOARD_DIGITAL_LOGIC_MSM586SEG
diff --git a/src/mainboard/digital_logic/msm586seg/board_info.txt b/src/mainboard/digital_logic/msm586seg/board_info.txt
new file mode 100644
index 0000000..739c592
--- /dev/null
+++ b/src/mainboard/digital_logic/msm586seg/board_info.txt
@@ -0,0 +1,2 @@
+Category: half
+Board URL: http://www.digital_logic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM586SEG
diff --git a/src/mainboard/digital_logic/msm586seg/cmos.layout b/src/mainboard/digital_logic/msm586seg/cmos.layout
new file mode 100644
index 0000000..9050c3d
--- /dev/null
+++ b/src/mainboard/digital_logic/msm586seg/cmos.layout
@@ -0,0 +1,72 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/digital_logic/msm586seg/devicetree.cb b/src/mainboard/digital_logic/msm586seg/devicetree.cb
new file mode 100644
index 0000000..e43ebff
--- /dev/null
+++ b/src/mainboard/digital_logic/msm586seg/devicetree.cb
@@ -0,0 +1,7 @@
+chip cpu/amd/sc520
+ device domain 0 on
+ device pci 0.0 on end
+ device pci 12.0 on end # enet
+ device pci 14.0 on end # 69000
+ end
+end
diff --git a/src/mainboard/digital_logic/msm586seg/irq_tables.c b/src/mainboard/digital_logic/msm586seg/irq_tables.c
new file mode 100644
index 0000000..15dcddd
--- /dev/null
+++ b/src/mainboard/digital_logic/msm586seg/irq_tables.c
@@ -0,0 +1,31 @@
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x122e, /* Device */
+ 0, /* Miniport data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x12<<3)|0x0, {{0x30, 0x8000}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x00}}, 0x0, 0x0},
+ {0x00,(0x14<<3)|0x0, {{0x30, 0x8000}, {0x31, 0x0}, {0x32, 0x0}, {0x33, 0x00}}, 0x0, 0x0},
+ }
+};
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/digital_logic/msm586seg/mainboard.c b/src/mainboard/digital_logic/msm586seg/mainboard.c
new file mode 100644
index 0000000..0310176
--- /dev/null
+++ b/src/mainboard/digital_logic/msm586seg/mainboard.c
@@ -0,0 +1,133 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/amd/sc520.h>
+
+
+static void irqdump(void)
+{
+ volatile unsigned char *irq;
+ void *mmcr;
+ int i;
+ int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
+ 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
+ 0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
+ 0xd30, 0xd31, 0xd32, 0xd33,
+ 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
+ 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
+ -1};
+ mmcr = (void *) 0xfffef000;
+
+ printk(BIOS_ERR, "mmcr is %p\n", mmcr);
+ for(i = 0; irqlist[i] >= 0; i++) {
+ irq = mmcr + irqlist[i];
+ printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
+ }
+
+}
+
+/* TODO: finish up mmcr struct in sc520.h, and;
+ - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
+*/
+static void mainboard_enable(struct device *dev)
+{
+ //volatile struct mmcrpic *pic = MMCRPIC;
+ volatile struct mmcr *mmcr = MMCRDEFAULT;
+
+ /* msm586seg has this register set to a weird value.
+ * follow the board, not the manual!
+ */
+
+ /* currently, nothing in the device to use, so ignore it. */
+ printk(BIOS_ERR, "digital logic msm586 seg ENTER %s\n", __func__);
+
+
+ /* from fuctory bios */
+ /* NOTE: the following interrupt settings made interrupts work
+ * for hard drive, and serial, but not for ethernet
+ */
+ /* just do what they say and nobody gets hurt. */
+ mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE;
+ /* all ints to level */
+ mmcr->pic.mpicmode = 0;
+ mmcr->pic.sl1picmode = 0;
+ mmcr->pic.sl2picmode = 0x80;
+
+ mmcr->pic.intpinpol = 0;
+
+ mmcr->pic.pit0map = 1;
+ mmcr->pic.uart1map = 0xc;
+ mmcr->pic.uart2map = 0xb;
+ mmcr->pic.rtcmap = 3;
+ mmcr->pic.ferrmap = 8;
+ mmcr->pic.gp0imap = 6;
+ mmcr->pic.gp1imap = 2;
+ mmcr->pic.gp2imap = 7;
+ mmcr->pic.gp6imap = 0x15;
+ mmcr->pic.gp7imap = 0x16;
+ mmcr->pic.gp10imap = 0x9;
+ mmcr->pic.gp9imap = 0x4;
+
+ irqdump();
+ printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
+
+ printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
+ printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22);
+
+ /* The following block has NOT proven sufficient to get
+ * the VGA hardware to talk to us
+ */
+ /* let's set some mmcr stuff per the BIOS settings */
+ mmcr->dbctl.dbctl = 0x10;
+ mmcr->sysarb.ctl = 6;
+ mmcr->sysarb.menb = 0xf;
+ mmcr->sysarb.prictl = 0xc0000f0f;
+ /* this is bios setting, depends on sysarb above */
+ mmcr->hostbridge.ctl = 0x108;
+ printk(BIOS_ERR, "digital logic msm586 seg EXIT %s\n", __func__);
+
+ /* pio */
+ mmcr->pio.data31_16 = 0xffbf;
+
+ /* pci stuff */
+ mmcr->pic.pciintamap = 0xa;
+
+ /* END block where vga hardware still will not talk to us */
+ /* all we get from VGA I/O addresses are ffff etc.
+ */
+ mmcr->sysmap.adddecctl = 0x10;
+
+ /* VGA now talks to us, so this adddecctl was the trick.
+ * still no interrupts from enet.
+ * Let's try fixing the piodata stuff, as there may be
+ * some wire there not documented.
+ */
+ mmcr->pio.data31_16 = 0xffbf;
+ /* also, our sl?picmode needs to match fuctory bios */
+ mmcr->pic.sl1picmode = 0x80;
+ mmcr->pic.sl2picmode = 0x0;
+ /* and, finally, they do set gp5imap and we don't.
+ */
+ mmcr->pic.gp5imap = 0xd;
+ /* remaining problem: almost certainly, the irq table is bogus
+ * NO SHOCK as it came from fuctory bios.
+ * but let's try these 4 changes for now and see what shakes.
+ */
+ /* still not interrupts. */
+ /* their IRQ table is wrong. Just hardwire it */
+ {
+ unsigned char pciints[4] = {15, 15, 15, 15};
+ pci_assign_irqs(0, 12, pciints);
+ }
+ /* the assigned failed but we just noticed -- there is no
+ * dma mapping, and selftest on e100 requires that dma work
+ */
+ /* follow fuctory here */
+ mmcr->dmacontrol.extchanmapa = 0x3210;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/digital_logic/msm586seg/romstage.c b/src/mainboard/digital_logic/msm586seg/romstage.c
new file mode 100644
index 0000000..ab944a4
--- /dev/null
+++ b/src/mainboard/digital_logic/msm586seg/romstage.c
@@ -0,0 +1,240 @@
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include "cpu/x86/bist.h"
+
+void setup_pars(void)
+{
+ volatile unsigned long *par;
+ /* as per the book: */
+ /* PAR register setup */
+ /* set up the PAR registers as they are on the MSM586SEG */
+ par = (unsigned long *) 0xfffef088;
+
+ /* NOTE: move this to mainboard.c ASAP */
+ *par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
+ *par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
+ *par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
+ *par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
+ *par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
+ *par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
+ *par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
+ *par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
+ *par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
+ *par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
+ *par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
+ *par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
+ *par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
+ *par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
+ *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
+ *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
+}
+
+#include "cpu/amd/sc520/raminit.c"
+
+struct mem_controller {
+ int i;
+};
+
+static int spd_read_byte(unsigned device, unsigned address) { }
+
+static inline void dumpmem(void){
+ int i, j;
+ unsigned char *l;
+ unsigned char c;
+
+ for(i = 0x4000; i < 0x5000; i += 16) {
+ print_err_hex32(i); print_err(":");
+ for(j = 0; j < 16; j++) {
+ l = (unsigned char *)i + j;
+ c = *l;
+ print_err_hex8(c);
+ print_err(" ");
+ }
+ print_err("\n");
+ }
+}
+
+static inline void irqinit(void){
+ volatile unsigned char *cp;
+#if 0
+/* these values taken from the msm board itself.
+ * and they cause the board to not even come out of calibrating_delay_loop
+ * if you can believe it. Our problem right now is no IDE or serial interrupts
+ * So we'll try to put interrupts in, one at a time. IDE first.
+ */
+ cp = (volatile unsigned char *) 0xfffefd00;
+ *cp = 0x11;
+ cp = (volatile unsigned char *) 0xfffefd02;
+ *cp = 0x02;
+ cp = (volatile unsigned char *) 0xfffefd03;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd04;
+ *cp = 0xf7;
+ cp = (volatile unsigned char *) 0xfffefd08;
+ *cp = 0xf7;
+ cp = (volatile unsigned char *) 0xfffefd0a;
+ *cp = 0x8b;
+ cp = (volatile unsigned char *) 0xfffefd10;
+ *cp = 0x18;
+ cp = (volatile unsigned char *) 0xfffefd14;
+ *cp = 0x09;
+ cp = (volatile unsigned char *) 0xfffefd18;
+ *cp = 0x88;
+ cp = (volatile unsigned char *) 0xfffefd1a;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd1b;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd1c;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd20;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd21;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd22;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd28;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd29;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd30;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd31;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd32;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd33;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd40;
+ *cp = 0x10;
+ cp = (volatile unsigned char *) 0xfffefd41;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd42;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd43;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd44;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd45;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd46;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd50;
+ *cp = 0x37;
+ cp = (volatile unsigned char *) 0xfffefd51;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd52;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd53;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd54;
+ *cp = 0x37;
+ cp = (volatile unsigned char *) 0xfffefd55;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd56;
+ *cp = 0x37;
+ cp = (volatile unsigned char *) 0xfffefd57;
+ *cp = 0x00;
+ cp = (volatile unsigned char *) 0xfffefd58;
+ *cp = 0xff;
+ cp = (volatile unsigned char *) 0xfffefd59;
+ *cp = 0xff;
+ cp = (volatile unsigned char *) 0xfffefd5a;
+ *cp = 0xff;
+#endif
+#if 0
+ /* this fails too */
+ /* IDE only ... */
+ cp = (volatile unsigned char *) 0xfffefd56;
+ *cp = 0xe;
+#endif
+}
+
+#include <cpu/intel/romstage.h>
+static void main(unsigned long bist)
+{
+ volatile int i;
+ for(i = 0; i < 100; i++)
+ ;
+
+ setupsc520();
+ irqinit();
+ console_init();
+ for(i = 0; i < 100; i++)
+ print_err("fill usart\n");
+ // while(1)
+ print_err("HI THERE!\n");
+ // sizemem();
+ staticmem();
+
+/* Void warranty when label is removed. */
+dummy_romcc_workaround_label:
+ do { } while (0);
+
+ print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60);
+ print_err("\n");
+
+ // while(1)
+ print_err("STATIC MEM DONE\n");
+ post_code(0xee);
+ print_err("loop forever ...\n");
+
+#if 0
+
+ /* clear memory 1meg */
+ __asm__ volatile(
+ "1: \n\t"
+ "movl %0, %%fs:(%1)\n\t"
+ "addl $4,%1\n\t"
+ "subl $4,%2\n\t"
+ "jnz 1b\n\t"
+ :
+ : "a" (0), "D" (0), "c" (1024*1024)
+ );
+
+
+#endif
+
+#if 0
+ dump_pci_devices();
+#endif
+#if 0
+ dump_pci_device(PCI_DEV(0, 0, 0));
+#endif
+
+#if 1
+ {
+ volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000;
+ volatile unsigned char *dst = (unsigned char *) 0x4000;
+ for(i = 0; i < 0x20000; i++) {
+ /*
+ print_err("Set dst "); print_err_hex32((unsigned long) dst);
+ print_err(" to "); print_err_hex32(*src); print_err("\n");
+ */
+ *dst = *src;
+ //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n");
+ dst++, src++;
+ post_code(i & 0xff);
+ }
+ }
+ dumpmem();
+ post_code(0x00);
+
+ print_err("loop forever\n");
+ post_code(0xdd);
+ __asm__ volatile(
+ "movl %0, %%edi\n\t"
+ "jmp *%%edi\n\t"
+ :
+ : "a" (0x4000)
+ );
+
+ print_err("Oh dear, I'm afraid it didn't work...\n");
+
+ while(1);
+#endif
+}
diff --git a/src/mainboard/digital_logic/msm800sev/Kconfig b/src/mainboard/digital_logic/msm800sev/Kconfig
new file mode 100644
index 0000000..fa06f3e
--- /dev/null
+++ b/src/mainboard/digital_logic/msm800sev/Kconfig
@@ -0,0 +1,27 @@
+if BOARD_DIGITAL_LOGIC_MSM800SEV
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_GEODE_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_256
+ select POWER_BUTTON_FORCE_ENABLE
+
+config MAINBOARD_DIR
+ string
+ default digital_logic/msm800sev
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MSM800SEV"
+
+config IRQ_SLOT_COUNT
+ int
+ default 9
+
+endif # BOARD_DIGITAL_LOGIC_MSM800SEV
diff --git a/src/mainboard/digital_logic/msm800sev/board_info.txt b/src/mainboard/digital_logic/msm800sev/board_info.txt
new file mode 100644
index 0000000..0a8aebd
--- /dev/null
+++ b/src/mainboard/digital_logic/msm800sev/board_info.txt
@@ -0,0 +1,2 @@
+Category: half
+Board URL: http://www.digital_logic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV
diff --git a/src/mainboard/digital_logic/msm800sev/cmos.layout b/src/mainboard/digital_logic/msm800sev/cmos.layout
new file mode 100644
index 0000000..9050c3d
--- /dev/null
+++ b/src/mainboard/digital_logic/msm800sev/cmos.layout
@@ -0,0 +1,72 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/digital_logic/msm800sev/devicetree.cb b/src/mainboard/digital_logic/msm800sev/devicetree.cb
new file mode 100644
index 0000000..839b767
--- /dev/null
+++ b/src/mainboard/digital_logic/msm800sev/devicetree.cb
@@ -0,0 +1,86 @@
+chip northbridge/amd/lx
+ device domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ # How to get these? Boot linux and do this:
+ # rdmsr 0x51400025
+ register "lpc_serirq_enable" = "0x0000105a"
+ # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ # mode is high 10 bits (determined from code)
+ register "lpc_serirq_mode" = "1"
+ # Don't yet know how to find this.
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci f.0 on # ISA Bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci f.1 on end # Flash controller
+ device pci f.2 on end # IDE controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+
+ # APIC cluster is late CPU init.
+ device cpu_cluster 0 on
+ chip cpu/amd/geode_lx
+ device lapic 0 on end
+ end
+ end
+
+end
+
diff --git a/src/mainboard/digital_logic/msm800sev/irq_tables.c b/src/mainboard/digital_logic/msm800sev/irq_tables.c
new file mode 100644
index 0000000..53cbb27
--- /dev/null
+++ b/src/mainboard/digital_logic/msm800sev/irq_tables.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 5
+#define PIRQC 10
+#define PIRQD 10
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x100b, /* Vendor */
+ 0x2b, /* Device */
+ 0, /* Miniport data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xe, /* u8 checksum. This has to be set to some
+ value that would give 0 after the sum of all
+ bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0},
+ {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
+ {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
+ {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
+ {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/digital_logic/msm800sev/mainboard.c b/src/mainboard/digital_logic/msm800sev/mainboard.c
new file mode 100644
index 0000000..352353f
--- /dev/null
+++ b/src/mainboard/digital_logic/msm800sev/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "MSM800SEV ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "MSM800SEV EXIT %s\n", __func__);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/digital_logic/msm800sev/romstage.c b/src/mainboard/digital_logic/msm800sev/romstage.c
new file mode 100644
index 0000000..8bfe8e5
--- /dev/null
+++ b/src/mainboard/digital_logic/msm800sev/romstage.c
@@ -0,0 +1,82 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+#include "northbridge/amd/lx/raminit.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/lx/pll_reset.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+
+ static const struct mem_controller memctrl [] = {
+ {.channel0 = {DIMM0, DIMM1}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* NOTE: must do this AFTER the early_setup!
+ * it is counting on some early MSR setup
+ * for cs5536
+ */
+ cs5536_disable_internal_uart();
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset();
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Switch from Cache as RAM to real RAM */
+ /* There are two ways we could think about this.
+ 1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.
+ Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
+ 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
+ That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
+ as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real
+ RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
+ where LB would like it, you need to write some code to do a copy from cache to RAM
+
+ We use method 1 on Norwich.
+ */
+ post_code(0x02);
+ __asm__("wbinvd\n");
+ print_err("Past wbinvd\n");
+ /* we are finding the return does not work on this board. Explicitly call the label that is
+ * after the call to us. This is gross, but sometimes at this level it is the only way out
+ */
+ done_cache_as_ram_main();
+}
diff --git a/src/mainboard/digitallogic/Kconfig b/src/mainboard/digitallogic/Kconfig
deleted file mode 100644
index 9f490b0..0000000
--- a/src/mainboard/digitallogic/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-if VENDOR_DIGITALLOGIC
-
-choice
- prompt "Mainboard model"
-
-config BOARD_DIGITALLOGIC_ADL855PC
- bool "smartModule855"
-config BOARD_DIGITALLOGIC_MSM586SEG
- bool "MSM586SEG"
-config BOARD_DIGITALLOGIC_MSM800SEV
- bool "MSM800SEV"
-
-endchoice
-
-source "src/mainboard/digitallogic/adl855pc/Kconfig"
-source "src/mainboard/digitallogic/msm586seg/Kconfig"
-source "src/mainboard/digitallogic/msm800sev/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "DIGITAL-LOGIC"
-
-endif # VENDOR_DIGITALLOGIC
diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig
deleted file mode 100644
index 8c57a89..0000000
--- a/src/mainboard/digitallogic/adl855pc/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-if BOARD_DIGITALLOGIC_ADL855PC
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SOCKET_MPGA479M
- select NORTHBRIDGE_INTEL_I855
- select SOUTHBRIDGE_INTEL_I82801DX
- select SUPERIO_WINBOND_W83627HF
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select BOARD_ROMSIZE_KB_1024
-
-config MAINBOARD_DIR
- string
- default digitallogic/adl855pc
-
-config MAINBOARD_PART_NUMBER
- string
- default "smartModule855"
-
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
-config IRQ_SLOT_COUNT
- int
- default 5
-
-endif # BOARD_DIGITALLOGIC_ADL855PC
diff --git a/src/mainboard/digitallogic/adl855pc/board_info.txt b/src/mainboard/digitallogic/adl855pc/board_info.txt
deleted file mode 100644
index 7680e6f..0000000
--- a/src/mainboard/digitallogic/adl855pc/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: half
diff --git a/src/mainboard/digitallogic/adl855pc/cmos.layout b/src/mainboard/digitallogic/adl855pc/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/digitallogic/adl855pc/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb
deleted file mode 100644
index 3a9603b..0000000
--- a/src/mainboard/digitallogic/adl855pc/devicetree.cb
+++ /dev/null
@@ -1,56 +0,0 @@
-chip northbridge/intel/i855
- device domain 0 on
- device pci 0.0 on end
- device pci 1.0 on end
- chip southbridge/intel/i82801dx
-# pci 11.0 on end
-# pci 11.1 on end
-# pci 11.2 on end
-# pci 11.3 on end
-# pci 11.4 on end
-# pci 11.5 on end
-# pci 11.6 on end
-# pci 12.0 on end
- register "enable_usb" = "0"
- register "enable_native_ide" = "0"
- chip superio/winbond/w83627hf # link 1
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off end # CIR
- device pnp 2e.7 off end # GAME_MIDI_GIPO1
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
- end
- end
- device cpu_cluster 0 on
- chip cpu/intel/socket_mPGA479M
- device lapic 0 on end
- end
- end
-end
diff --git a/src/mainboard/digitallogic/adl855pc/irq_tables.c b/src/mainboard/digitallogic/adl855pc/irq_tables.c
deleted file mode 100644
index 94adba1..0000000
--- a/src/mainboard/digitallogic/adl855pc/irq_tables.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-
- Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0, /* Where the interrupt router lies (bus) */
- 0x88, /* Where the interrupt router lies (dev) */
- 0x1c20, /* IRQs devoted exclusively to PCI usage */
- 0x1106, /* Vendor */
- 0x8231, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* 8231 ethernet */
- {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
- /* 8231 internal */
- {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
- /* PCI slot */
- {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
- {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
- {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
deleted file mode 100644
index 093c60b..0000000
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ /dev/null
@@ -1,64 +0,0 @@
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <stdlib.h>
-#include <lib.h>
-#include "drivers/pc80/udelay_io.c"
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include "southbridge/intel/i82801dx/i82801dx.h"
-#include "northbridge/intel/i855/raminit.h"
-#include "northbridge/intel/i855/debug.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include "cpu/x86/bist.h"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i855/raminit.c"
-#include "northbridge/intel/i855/reset_test.c"
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- if (bist == 0) {
-#if 0
- enable_lapic();
- init_timer();
-#endif
- }
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
-#if 0
- print_pci_devices();
-#endif
-
- if (!bios_reset_detected()) {
- enable_smbus();
-#if 0
- dump_spd_registers();
- dump_smbus_registers();
-#endif
- sdram_set_registers();
- sdram_set_spd_registers();
- sdram_enable();
- }
-
-#if 0
- dump_pci_devices();
- dump_pci_device(PCI_DEV(0, 0, 0));
-#endif
-}
diff --git a/src/mainboard/digitallogic/msm586seg/Kconfig b/src/mainboard/digitallogic/msm586seg/Kconfig
deleted file mode 100644
index 4cd6f11..0000000
--- a/src/mainboard/digitallogic/msm586seg/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-if BOARD_DIGITALLOGIC_MSM586SEG
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SC520
- select HAVE_PIRQ_TABLE
- select HAVE_OPTION_TABLE
- select BOARD_ROMSIZE_KB_512
- select ROMCC
-
-config MAINBOARD_DIR
- string
- default digitallogic/msm586seg
-
-config MAINBOARD_PART_NUMBER
- string
- default "MSM586SEG"
-
-config IRQ_SLOT_COUNT
- int
- default 2
-
-endif # BOARD_DIGITALLOGIC_MSM586SEG
diff --git a/src/mainboard/digitallogic/msm586seg/board_info.txt b/src/mainboard/digitallogic/msm586seg/board_info.txt
deleted file mode 100644
index 90fda6d..0000000
--- a/src/mainboard/digitallogic/msm586seg/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: half
-Board URL: http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM586SEG
diff --git a/src/mainboard/digitallogic/msm586seg/cmos.layout b/src/mainboard/digitallogic/msm586seg/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/digitallogic/msm586seg/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/digitallogic/msm586seg/devicetree.cb b/src/mainboard/digitallogic/msm586seg/devicetree.cb
deleted file mode 100644
index e43ebff..0000000
--- a/src/mainboard/digitallogic/msm586seg/devicetree.cb
+++ /dev/null
@@ -1,7 +0,0 @@
-chip cpu/amd/sc520
- device domain 0 on
- device pci 0.0 on end
- device pci 12.0 on end # enet
- device pci 14.0 on end # 69000
- end
-end
diff --git a/src/mainboard/digitallogic/msm586seg/irq_tables.c b/src/mainboard/digitallogic/msm586seg/irq_tables.c
deleted file mode 100644
index 15dcddd..0000000
--- a/src/mainboard/digitallogic/msm586seg/irq_tables.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x122e, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x12<<3)|0x0, {{0x30, 0x8000}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x00}}, 0x0, 0x0},
- {0x00,(0x14<<3)|0x0, {{0x30, 0x8000}, {0x31, 0x0}, {0x32, 0x0}, {0x33, 0x00}}, 0x0, 0x0},
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c
deleted file mode 100644
index 0310176..0000000
--- a/src/mainboard/digitallogic/msm586seg/mainboard.c
+++ /dev/null
@@ -1,133 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <cpu/amd/sc520.h>
-
-
-static void irqdump(void)
-{
- volatile unsigned char *irq;
- void *mmcr;
- int i;
- int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
- 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
- 0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
- 0xd30, 0xd31, 0xd32, 0xd33,
- 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
- 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
- -1};
- mmcr = (void *) 0xfffef000;
-
- printk(BIOS_ERR, "mmcr is %p\n", mmcr);
- for(i = 0; irqlist[i] >= 0; i++) {
- irq = mmcr + irqlist[i];
- printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
- }
-
-}
-
-/* TODO: finish up mmcr struct in sc520.h, and;
- - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
-*/
-static void mainboard_enable(struct device *dev)
-{
- //volatile struct mmcrpic *pic = MMCRPIC;
- volatile struct mmcr *mmcr = MMCRDEFAULT;
-
- /* msm586seg has this register set to a weird value.
- * follow the board, not the manual!
- */
-
- /* currently, nothing in the device to use, so ignore it. */
- printk(BIOS_ERR, "digital logic msm586 seg ENTER %s\n", __func__);
-
-
- /* from fuctory bios */
- /* NOTE: the following interrupt settings made interrupts work
- * for hard drive, and serial, but not for ethernet
- */
- /* just do what they say and nobody gets hurt. */
- mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE;
- /* all ints to level */
- mmcr->pic.mpicmode = 0;
- mmcr->pic.sl1picmode = 0;
- mmcr->pic.sl2picmode = 0x80;
-
- mmcr->pic.intpinpol = 0;
-
- mmcr->pic.pit0map = 1;
- mmcr->pic.uart1map = 0xc;
- mmcr->pic.uart2map = 0xb;
- mmcr->pic.rtcmap = 3;
- mmcr->pic.ferrmap = 8;
- mmcr->pic.gp0imap = 6;
- mmcr->pic.gp1imap = 2;
- mmcr->pic.gp2imap = 7;
- mmcr->pic.gp6imap = 0x15;
- mmcr->pic.gp7imap = 0x16;
- mmcr->pic.gp10imap = 0x9;
- mmcr->pic.gp9imap = 0x4;
-
- irqdump();
- printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
-
- printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
- printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22);
-
- /* The following block has NOT proven sufficient to get
- * the VGA hardware to talk to us
- */
- /* let's set some mmcr stuff per the BIOS settings */
- mmcr->dbctl.dbctl = 0x10;
- mmcr->sysarb.ctl = 6;
- mmcr->sysarb.menb = 0xf;
- mmcr->sysarb.prictl = 0xc0000f0f;
- /* this is bios setting, depends on sysarb above */
- mmcr->hostbridge.ctl = 0x108;
- printk(BIOS_ERR, "digital logic msm586 seg EXIT %s\n", __func__);
-
- /* pio */
- mmcr->pio.data31_16 = 0xffbf;
-
- /* pci stuff */
- mmcr->pic.pciintamap = 0xa;
-
- /* END block where vga hardware still will not talk to us */
- /* all we get from VGA I/O addresses are ffff etc.
- */
- mmcr->sysmap.adddecctl = 0x10;
-
- /* VGA now talks to us, so this adddecctl was the trick.
- * still no interrupts from enet.
- * Let's try fixing the piodata stuff, as there may be
- * some wire there not documented.
- */
- mmcr->pio.data31_16 = 0xffbf;
- /* also, our sl?picmode needs to match fuctory bios */
- mmcr->pic.sl1picmode = 0x80;
- mmcr->pic.sl2picmode = 0x0;
- /* and, finally, they do set gp5imap and we don't.
- */
- mmcr->pic.gp5imap = 0xd;
- /* remaining problem: almost certainly, the irq table is bogus
- * NO SHOCK as it came from fuctory bios.
- * but let's try these 4 changes for now and see what shakes.
- */
- /* still not interrupts. */
- /* their IRQ table is wrong. Just hardwire it */
- {
- unsigned char pciints[4] = {15, 15, 15, 15};
- pci_assign_irqs(0, 12, pciints);
- }
- /* the assigned failed but we just noticed -- there is no
- * dma mapping, and selftest on e100 requires that dma work
- */
- /* follow fuctory here */
- mmcr->dmacontrol.extchanmapa = 0x3210;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c
deleted file mode 100644
index ab944a4..0000000
--- a/src/mainboard/digitallogic/msm586seg/romstage.c
+++ /dev/null
@@ -1,240 +0,0 @@
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include "cpu/x86/bist.h"
-
-void setup_pars(void)
-{
- volatile unsigned long *par;
- /* as per the book: */
- /* PAR register setup */
- /* set up the PAR registers as they are on the MSM586SEG */
- par = (unsigned long *) 0xfffef088;
-
- /* NOTE: move this to mainboard.c ASAP */
- *par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
- *par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
- *par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
- *par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
- *par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
- *par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
- *par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
- *par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
- *par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
- *par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
- *par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
- *par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
- *par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
- *par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
- *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
- *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
-}
-
-#include "cpu/amd/sc520/raminit.c"
-
-struct mem_controller {
- int i;
-};
-
-static int spd_read_byte(unsigned device, unsigned address) { }
-
-static inline void dumpmem(void){
- int i, j;
- unsigned char *l;
- unsigned char c;
-
- for(i = 0x4000; i < 0x5000; i += 16) {
- print_err_hex32(i); print_err(":");
- for(j = 0; j < 16; j++) {
- l = (unsigned char *)i + j;
- c = *l;
- print_err_hex8(c);
- print_err(" ");
- }
- print_err("\n");
- }
-}
-
-static inline void irqinit(void){
- volatile unsigned char *cp;
-#if 0
-/* these values taken from the msm board itself.
- * and they cause the board to not even come out of calibrating_delay_loop
- * if you can believe it. Our problem right now is no IDE or serial interrupts
- * So we'll try to put interrupts in, one at a time. IDE first.
- */
- cp = (volatile unsigned char *) 0xfffefd00;
- *cp = 0x11;
- cp = (volatile unsigned char *) 0xfffefd02;
- *cp = 0x02;
- cp = (volatile unsigned char *) 0xfffefd03;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd04;
- *cp = 0xf7;
- cp = (volatile unsigned char *) 0xfffefd08;
- *cp = 0xf7;
- cp = (volatile unsigned char *) 0xfffefd0a;
- *cp = 0x8b;
- cp = (volatile unsigned char *) 0xfffefd10;
- *cp = 0x18;
- cp = (volatile unsigned char *) 0xfffefd14;
- *cp = 0x09;
- cp = (volatile unsigned char *) 0xfffefd18;
- *cp = 0x88;
- cp = (volatile unsigned char *) 0xfffefd1a;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd1b;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd1c;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd20;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd21;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd22;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd28;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd29;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd30;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd31;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd32;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd33;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd40;
- *cp = 0x10;
- cp = (volatile unsigned char *) 0xfffefd41;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd42;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd43;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd44;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd45;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd46;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd50;
- *cp = 0x37;
- cp = (volatile unsigned char *) 0xfffefd51;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd52;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd53;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd54;
- *cp = 0x37;
- cp = (volatile unsigned char *) 0xfffefd55;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd56;
- *cp = 0x37;
- cp = (volatile unsigned char *) 0xfffefd57;
- *cp = 0x00;
- cp = (volatile unsigned char *) 0xfffefd58;
- *cp = 0xff;
- cp = (volatile unsigned char *) 0xfffefd59;
- *cp = 0xff;
- cp = (volatile unsigned char *) 0xfffefd5a;
- *cp = 0xff;
-#endif
-#if 0
- /* this fails too */
- /* IDE only ... */
- cp = (volatile unsigned char *) 0xfffefd56;
- *cp = 0xe;
-#endif
-}
-
-#include <cpu/intel/romstage.h>
-static void main(unsigned long bist)
-{
- volatile int i;
- for(i = 0; i < 100; i++)
- ;
-
- setupsc520();
- irqinit();
- console_init();
- for(i = 0; i < 100; i++)
- print_err("fill usart\n");
- // while(1)
- print_err("HI THERE!\n");
- // sizemem();
- staticmem();
-
-/* Void warranty when label is removed. */
-dummy_romcc_workaround_label:
- do { } while (0);
-
- print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60);
- print_err("\n");
-
- // while(1)
- print_err("STATIC MEM DONE\n");
- post_code(0xee);
- print_err("loop forever ...\n");
-
-#if 0
-
- /* clear memory 1meg */
- __asm__ volatile(
- "1: \n\t"
- "movl %0, %%fs:(%1)\n\t"
- "addl $4,%1\n\t"
- "subl $4,%2\n\t"
- "jnz 1b\n\t"
- :
- : "a" (0), "D" (0), "c" (1024*1024)
- );
-
-
-#endif
-
-#if 0
- dump_pci_devices();
-#endif
-#if 0
- dump_pci_device(PCI_DEV(0, 0, 0));
-#endif
-
-#if 1
- {
- volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000;
- volatile unsigned char *dst = (unsigned char *) 0x4000;
- for(i = 0; i < 0x20000; i++) {
- /*
- print_err("Set dst "); print_err_hex32((unsigned long) dst);
- print_err(" to "); print_err_hex32(*src); print_err("\n");
- */
- *dst = *src;
- //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n");
- dst++, src++;
- post_code(i & 0xff);
- }
- }
- dumpmem();
- post_code(0x00);
-
- print_err("loop forever\n");
- post_code(0xdd);
- __asm__ volatile(
- "movl %0, %%edi\n\t"
- "jmp *%%edi\n\t"
- :
- : "a" (0x4000)
- );
-
- print_err("Oh dear, I'm afraid it didn't work...\n");
-
- while(1);
-#endif
-}
diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig
deleted file mode 100644
index bc8e3ac..0000000
--- a/src/mainboard/digitallogic/msm800sev/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-if BOARD_DIGITALLOGIC_MSM800SEV
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_GEODE_LX
- select NORTHBRIDGE_AMD_LX
- select SOUTHBRIDGE_AMD_CS5536
- select SUPERIO_WINBOND_W83627HF
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_256
- select POWER_BUTTON_FORCE_ENABLE
-
-config MAINBOARD_DIR
- string
- default digitallogic/msm800sev
-
-config MAINBOARD_PART_NUMBER
- string
- default "MSM800SEV"
-
-config IRQ_SLOT_COUNT
- int
- default 9
-
-endif # BOARD_DIGITALLOGIC_MSM800SEV
diff --git a/src/mainboard/digitallogic/msm800sev/board_info.txt b/src/mainboard/digitallogic/msm800sev/board_info.txt
deleted file mode 100644
index 21476ad..0000000
--- a/src/mainboard/digitallogic/msm800sev/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: half
-Board URL: http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV
diff --git a/src/mainboard/digitallogic/msm800sev/cmos.layout b/src/mainboard/digitallogic/msm800sev/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/digitallogic/msm800sev/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb
deleted file mode 100644
index 839b767..0000000
--- a/src/mainboard/digitallogic/msm800sev/devicetree.cb
+++ /dev/null
@@ -1,86 +0,0 @@
-chip northbridge/amd/lx
- device domain 0 on
- device pci 1.0 on end
- device pci 1.1 on end
- chip southbridge/amd/cs5536
- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
- # SIRQ Mode = Active(Quiet) mode. Save power....
- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
- # How to get these? Boot linux and do this:
- # rdmsr 0x51400025
- register "lpc_serirq_enable" = "0x0000105a"
- # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
- register "lpc_serirq_polarity" = "0x0000EFA5"
- # mode is high 10 bits (determined from code)
- register "lpc_serirq_mode" = "1"
- # Don't yet know how to find this.
- register "enable_gpio_int_route" = "0x0D0C0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "0" #0: host, 1:device
- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "0"
- register "com1_address" = "0x3F8"
- register "com1_irq" = "4"
- register "com2_enable" = "0"
- register "com2_address" = "0x2F8"
- register "com2_irq" = "3"
- register "unwanted_vpci[0]" = "0" # End of list has a zero
- device pci f.0 on # ISA Bridge
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci f.1 on end # Flash controller
- device pci f.2 on end # IDE controller
- device pci f.3 on end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
-
- # APIC cluster is late CPU init.
- device cpu_cluster 0 on
- chip cpu/amd/geode_lx
- device lapic 0 on end
- end
- end
-
-end
-
diff --git a/src/mainboard/digitallogic/msm800sev/irq_tables.c b/src/mainboard/digitallogic/msm800sev/irq_tables.c
deleted file mode 100644
index 53cbb27..0000000
--- a/src/mainboard/digitallogic/msm800sev/irq_tables.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 5
-#define PIRQC 10
-#define PIRQD 10
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x100b, /* Vendor */
- 0x2b, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xe, /* u8 checksum. This has to be set to some
- value that would give 0 after the sum of all
- bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0},
- {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
- {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
- {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
- {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/digitallogic/msm800sev/mainboard.c b/src/mainboard/digitallogic/msm800sev/mainboard.c
deleted file mode 100644
index 352353f..0000000
--- a/src/mainboard/digitallogic/msm800sev/mainboard.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "MSM800SEV ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "MSM800SEV EXIT %s\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
deleted file mode 100644
index 8bfe8e5..0000000
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ /dev/null
@@ -1,82 +0,0 @@
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <console/console.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/lxdef.h>
-#include <cpu/amd/car.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-#include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include "northbridge/amd/lx/raminit.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
-
- static const struct mem_controller memctrl [] = {
- {.channel0 = {DIMM0, DIMM1}}
- };
-
- SystemPreInit();
- msr_init();
-
- cs5536_early_setup();
-
- /* NOTE: must do this AFTER the early_setup!
- * it is counting on some early MSR setup
- * for cs5536
- */
- cs5536_disable_internal_uart();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pll_reset();
-
- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
- sdram_initialize(1, memctrl);
-
- /* Switch from Cache as RAM to real RAM */
- /* There are two ways we could think about this.
- 1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.
- Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
- 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
- That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
- as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real
- RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
- where LB would like it, you need to write some code to do a copy from cache to RAM
-
- We use method 1 on Norwich.
- */
- post_code(0x02);
- __asm__("wbinvd\n");
- print_err("Past wbinvd\n");
- /* we are finding the return does not work on this board. Explicitly call the label that is
- * after the call to us. This is gross, but sometimes at this level it is the only way out
- */
- done_cache_as_ram_main();
-}
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index c51ee35..8f0dbf3 100644
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Original take from digitallogic/adl855pc
+ * Original take from digital_logic/adl855pc
*
* Copyright (C) 2010 Travelping GmbH <info at travelping.com>
*
diff --git a/src/mainboard/linutop/linutop1/board_info.txt b/src/mainboard/linutop/linutop1/board_info.txt
index e9d3d1e..9b630eb 100644
--- a/src/mainboard/linutop/linutop1/board_info.txt
+++ b/src/mainboard/linutop/linutop1/board_info.txt
@@ -1,4 +1,4 @@
Category: settop
Board URL: http://www.linutop.com
Flashrom support: y
-Clone of: artecgroup/dbe61
+Clone of: artec_group/dbe61
diff --git a/src/mainboard/packard_bell/Kconfig b/src/mainboard/packard_bell/Kconfig
new file mode 100644
index 0000000..168ebd9
--- /dev/null
+++ b/src/mainboard/packard_bell/Kconfig
@@ -0,0 +1,19 @@
+if VENDOR_PACKARD_BELL
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_PACKARD_BELL_MS2290
+ bool "EasyNote LM85 (MS2290)"
+ help
+ EasyNote LM85 laptop
+
+endchoice
+
+source "src/mainboard/packard_bell/ms2290/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Packard Bell"
+
+endif # VENDOR_PACKARD_BELL
diff --git a/src/mainboard/packard_bell/ms2290/Kconfig b/src/mainboard/packard_bell/ms2290/Kconfig
new file mode 100644
index 0000000..1209ada
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/Kconfig
@@ -0,0 +1,61 @@
+if BOARD_PACKARD_BELL_MS2290
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select NORTHBRIDGE_INTEL_NEHALEM
+ select SOUTHBRIDGE_INTEL_IBEXPEAK
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_INT15
+ select EC_ACPI
+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
+
+config MAINBOARD_DIR
+ string
+ default packard_bell/ms2290
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "EasyNote LM85"
+
+config MAINBOARD_VERSION
+ string
+ default "V1.20"
+
+config MAINBOARD_VENDOR
+ string
+ default "Packard Bell"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 4
+
+config CPU_ADDR_BITS
+ int
+ default 36
+
+endif
diff --git a/src/mainboard/packard_bell/ms2290/Makefile.inc b/src/mainboard/packard_bell/ms2290/Makefile.inc
new file mode 100644
index 0000000..b47ace2
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/packard_bell/ms2290/acpi/ac.asl b/src/mainboard/packard_bell/ms2290/acpi/ac.asl
new file mode 100644
index 0000000..f9f0a3a
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi/ac.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device(AC)
+{
+ Name(_HID, "ACPI0003")
+ Name(_UID, 0x00)
+ Name(_PCL, Package() { \_SB } )
+
+ Method(_PSR, 0, NotSerialized)
+ {
+ return (HPAC)
+ }
+
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+}
+
+/* AC status change */
+Method(_Q50, 0, NotSerialized)
+{
+ Notify (AC, 0x80)
+}
+
+/* AC status change */
+Method(_Q51, 0, NotSerialized)
+{
+ Notify (AC, 0x80)
+}
diff --git a/src/mainboard/packard_bell/ms2290/acpi/battery.asl b/src/mainboard/packard_bell/ms2290/acpi/battery.asl
new file mode 100644
index 0000000..1ca2cf1
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi/battery.asl
@@ -0,0 +1,155 @@
+/* Arg0: Battery
+ * Arg1: Battery Status Package
+ * Arg2: charging
+ * Arg3: discharging
+ */
+Method(BSTA, 4, NotSerialized)
+{
+ Acquire(ECLK, 0xffff)
+ Store(0, Local0)
+
+ Store(0, PAGE)
+
+ Store(BAPR, Local2)
+
+ if (Arg2) // charging
+ {
+ Or(2, Local0, Local0)
+
+ If (LGreaterEqual (Local2, 0x8000)) {
+ Store(0, Local2)
+ }
+ }
+
+ if (Arg3) // discharging
+ {
+ Or(1, Local0, Local0)
+ Subtract(0x10000, Local2, Local2)
+ }
+
+ Store(Local0, Index(Arg1, 0x00))
+
+ Store(0, PAGE)
+ Store(BARC, Index(Arg1, 2))
+ Store(Local2, Index(Arg1, 1))
+
+ Store(0, PAGE)
+ Store(BAVO, Index(Arg1, 3))
+ Release(ECLK)
+ Return (Arg1)
+}
+
+Method(BINF, 2, NotSerialized)
+{
+ Acquire(ECLK, 0xffff)
+ Store(0, PAGE)
+ Store(BAFC, Local2)
+ Store(1, PAGE)
+ Store(BADC, Local1)
+
+ Store(Local1, Index(Arg0, 1)) // Design Capacity
+ Store(Local2, Index(Arg0, 2)) // Last full charge capacity
+ Store(1, PAGE)
+ Store(BADV, Index(Arg0, 4)) // Design Voltage
+ Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity
+
+ Store(1, PAGE)
+ Store (BASN, Local0)
+ Name (SERN, Buffer (0x06) { " " })
+ Store (4, Local1)
+ While (Local0)
+ {
+ Divide (Local0, 0x0A, Local2, Local0)
+ Add (Local2, 48, Index (SERN, Local1))
+ Decrement (Local1)
+ }
+ Store (SERN, Index (Arg0, 10)) // Serial Number
+
+ Name (TYPE, Buffer() { 0, 0, 0, 0, 0 })
+ Store(4, PAGE)
+ Store(BATY, TYPE)
+ Store(TYPE, Index (Arg0, 11)) // Battery type
+ Store(5, PAGE)
+ Store(BAOE, Index (Arg0, 12)) // OEM information
+ Store(2, PAGE)
+ Store(BANA, Index (Arg0, 9)) // Model number
+ Release(ECLK)
+ Return (Arg0)
+}
+
+Device (BAT0)
+{
+ Name (_HID, EisaId ("PNP0C0A"))
+ Name (_UID, 0x00)
+ Name (_PCL, Package () { \_SB })
+
+ Name (BATS, Package ()
+ {
+ 0x00, // 0: PowerUnit: Report in mWh
+ 0xFFFFFFFF, // 1: Design cap
+ 0xFFFFFFFF, // 2: Last full charge cap
+ 0x01, // 3: Battery Technology
+ 10800, // 4: Design Voltage (mV)
+ 0x00, // 5: Warning design capacity
+ 200, // 6: Low design capacity
+ 1, // 7: granularity1
+ 1, // 8: granularity2
+ "", // 9: Model number
+ "", // A: Serial number
+ "", // B: Battery Type
+ "" // C: OEM information
+ })
+
+ Method (_BIF, 0, NotSerialized)
+ {
+ Return (BINF(BATS, 0))
+ }
+
+ Name (BATI, Package ()
+ {
+ 0, // Battery State
+ // Bit 0 - discharge
+ // Bit 1 - charge
+ // Bit 2 - critical state
+ 0, // Battery present Rate
+ 0, // Battery remaining capacity
+ 0 // Battery present voltage
+ })
+
+ Method (_BST, 0, NotSerialized)
+ {
+ if (B0PR) {
+ Return (BSTA(0, BATI, B0CH, B0DI))
+ } else {
+ Return (BATS)
+ }
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ if (B0PR) {
+ Return (0x1f)
+ } else {
+ Return (0x0f)
+ }
+ }
+}
+
+/* Battery attach/detach */
+Method(_Q40, 0, NotSerialized)
+{
+ Notify(BAT0, 0x81)
+}
+Method(_Q41, 0, NotSerialized)
+{
+ Notify(BAT0, 0x81)
+}
+
+Method(_Q48, 0, NotSerialized)
+{
+ Notify(BAT0, 0x80)
+}
+Method(_Q4C, 0, NotSerialized)
+{
+ Notify(BAT0, 0x80)
+}
diff --git a/src/mainboard/packard_bell/ms2290/acpi/ec.asl b/src/mainboard/packard_bell/ms2290/acpi/ec.asl
new file mode 100644
index 0000000..3735f20
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi/ec.asl
@@ -0,0 +1,136 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+
+ Name (_GPE, 0x17)
+ Mutex (ECLK, 0)
+
+ OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100)
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x8),
+ PAGE, 8, /* Information Page Selector */
+ Offset (0x70),
+ , 1,
+ LIDS, 1,
+ , 3,
+ HPAC, 1,
+ Offset (0x88),
+ B0PR, 1, /* Battery 0 present */
+ B0CH, 1, /* Battery 0 charging */
+ B0DI, 1, /* Battery 0 discharging */
+ Offset (0xA8),
+ TMP0, 8,
+ TMP1, 8,
+ }
+
+ Device(LID)
+ {
+ Name(_HID, "PNP0C0D")
+ Method(_LID, 0, NotSerialized)
+ {
+ return (LIDS)
+ }
+ }
+
+ Method(_Q52, 0, NotSerialized)
+ {
+ Notify(LID, 0x80)
+ }
+
+ Method(_Q53, 0, NotSerialized)
+ {
+ Notify(^LID, 0x80)
+ }
+
+ /* PAGE = 0 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xe0),
+ BARC, 16, /* Battery remaining capacity */
+ BAFC, 16, /* Battery full charge capacity */
+ , 16,
+ BAPR, 16, /* Battery present rate */
+ BAVO, 16, /* Battery Voltage */
+ }
+
+ /* PAGE = 1 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xe0),
+ BADC, 16, /* Design Capacity */
+ BADV, 16, /* Design voltage */
+ BASN, 16
+ }
+
+ /* PAGE = 2 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xe0),
+ BANA, 128, /* Battery name */
+ }
+
+ /* PAGE = 4 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xe0),
+ BATY, 128, /* Battery type */
+ }
+
+ /* PAGE = 5 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xe0),
+ BAOE, 128, /* Battery OEM info */
+ }
+
+ Method (_CRS, 0)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 1, 1)
+ IO (Decode16, 0x66, 0x66, 1, 1)
+ })
+ Return (ECMD)
+ }
+ Method (_INI, 0, NotSerialized)
+ {
+ }
+
+ /* Decrease brightness. */
+ Method(_Q1D, 0, NotSerialized)
+ {
+ \_SB.PCI0.GFX0.LCD0.DECB()
+ }
+ /* Increase brightness. */
+ Method(_Q1C, 0, NotSerialized)
+ {
+ \_SB.PCI0.GFX0.LCD0.INCB()
+ }
+
+#include "battery.asl"
+#include "ac.asl"
+#include "thermal.asl"
+}
diff --git a/src/mainboard/packard_bell/ms2290/acpi/gpe.asl b/src/mainboard/packard_bell/ms2290/acpi/gpe.asl
new file mode 100644
index 0000000..cd9d784
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi/gpe.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_GPE)
+{
+}
diff --git a/src/mainboard/packard_bell/ms2290/acpi/nehalem_pci_irqs.asl b/src/mainboard/packard_bell/ms2290/acpi/nehalem_pci_irqs.asl
new file mode 100644
index 0000000..1f782c8
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi/nehalem_pci_irqs.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing.
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, 0, 0x10 },
+ Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
+ Package() { 0x0003ffff, 0, 0, 0x10 },
+ Package() { 0x0016ffff, 0, 0, 0x10 }, // ME
+ Package() { 0x0016ffff, 1, 0, 0x11 }, // ME
+ Package() { 0x0016ffff, 2, 0, 0x12 }, // ME
+ Package() { 0x0016ffff, 3, 0, 0x13 }, // ME
+ Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet
+ Package() { 0x001affff, 0, 0, 0x14 }, // USB
+ Package() { 0x001affff, 1, 0, 0x15 }, // USB
+ Package() { 0x001affff, 2, 0, 0x16 }, // USB
+ Package() { 0x001affff, 3, 0, 0x17 }, // USB
+ Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
+ Package() { 0x001cffff, 0, 0, 0x10 }, // PCI bridge
+ Package() { 0x001cffff, 1, 0, 0x11 }, // PCI bridge
+ Package() { 0x001cffff, 2, 0, 0x12 }, // PCI bridge
+ Package() { 0x001cffff, 3, 0, 0x13 }, // PCI bridge
+ Package() { 0x001dffff, 0, 0, 0x10 }, // USB
+ Package() { 0x001dffff, 1, 0, 0x11 }, // USB
+ Package() { 0x001dffff, 2, 0, 0x12 }, // USB
+ Package() { 0x001dffff, 3, 0, 0x13 }, // USB
+ Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
+ Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
+ Package() { 0x001fffff, 2, 0, 0x11 }, // SATA
+ Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS
+ })
+ } Else {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME
+ Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME
+ Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME
+ Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME
+ Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB
+ Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB
+ Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB
+ Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB
+ Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCI
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // PCI
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // PCI
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // PCI
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus
+ })
+ }
+}
diff --git a/src/mainboard/packard_bell/ms2290/acpi/platform.asl b/src/mainboard/packard_bell/ms2290/acpi/platform.asl
new file mode 100644
index 0000000..a254a9e
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi/platform.asl
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, /* APM command */
+ APMS, 8 /* APM status */
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) /* SMI Function */
+ Store (0, TRP0) /* Generate trap */
+ Return (SMIF) /* Return value of SMI handler */
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice. */
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Not implemented. */
+ Return(Package(){0,0})
+}
+
+/* System Bus */
+
+Scope(\_SB)
+{
+ /* This method is placed on the top level, so we can make sure it's the
+ * first executed _INI method.
+ */
+ Method(_INI, 0)
+ {
+ /* The DTS data in NVS is probably not up to date.
+ * Update temperature values and make sure AP thermal
+ * interrupts can happen
+ */
+
+ /* TRAP(71) */ /* TODO */
+
+ /* Determine the Operating System and save the value in OSYS.
+ * We have to do this in order to be able to work around
+ * certain windows bugs.
+ *
+ * OSYS value | Operating System
+ * -----------+------------------
+ * 2000 | Windows 2000
+ * 2001 | Windows XP(+SP1)
+ * 2002 | Windows XP SP2
+ * 2006 | Windows Vista
+ * ???? | Windows 7
+ */
+
+ /* Let's assume we're running at least Windows 2000 */
+ Store (2000, OSYS)
+
+ If (CondRefOf(_OSI, Local0)) {
+ If (_OSI("Windows 2001")) {
+ Store (2001, OSYS)
+ }
+
+ If (_OSI("Windows 2001 SP1")) {
+ Store (2001, OSYS)
+ }
+
+ If (_OSI("Windows 2001 SP2")) {
+ Store (2002, OSYS)
+ }
+
+ If (_OSI("Windows 2001.1")) {
+ Store (2001, OSYS)
+ }
+
+ If (_OSI("Windows 2001.1 SP1")) {
+ Store (2001, OSYS)
+ }
+
+ If (_OSI("Windows 2006")) {
+ Store (2006, OSYS)
+ }
+
+ If (_OSI("Windows 2006.1")) {
+ Store (2006, OSYS)
+ }
+
+ If (_OSI("Windows 2006 SP1")) {
+ Store (2006, OSYS)
+ }
+
+ If (_OSI("Windows 2009")) {
+ Store (2009, OSYS)
+ }
+
+ If (_OSI("Windows 2012")) {
+ Store (2012, OSYS)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/packard_bell/ms2290/acpi/superio.asl b/src/mainboard/packard_bell/ms2290/acpi/superio.asl
new file mode 100644
index 0000000..a2657f1
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi/superio.asl
@@ -0,0 +1 @@
+#include "../../../../drivers/pc80/ps2_controller.asl"
diff --git a/src/mainboard/packard_bell/ms2290/acpi/thermal.asl b/src/mainboard/packard_bell/ms2290/acpi/thermal.asl
new file mode 100644
index 0000000..735171b
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi/thermal.asl
@@ -0,0 +1,48 @@
+Scope(\_TZ)
+{
+ Name (MEBT, 0)
+
+ Method(C2K, 1, NotSerialized)
+ {
+ Multiply(Arg0, 10, Local0)
+ Add (Local0, 2732, Local0)
+ if (LLessEqual(Local0, 2732)) {
+ Return (3000)
+ }
+
+ if (LGreater(Local0, 4012)) {
+ Return (3000)
+ }
+ Return (Local0)
+ }
+
+ ThermalZone(THM0)
+ {
+ Method(_CRT, 0, NotSerialized) {
+ Return (C2K(127))
+ }
+ Method(_TMP) {
+ /* Avoid tripping alarm if ME isn't booted at all yet */
+ If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) {
+ Return (C2K(40))
+ }
+ Store (1, MEBT)
+ Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
+ }
+ }
+
+ ThermalZone(THM1)
+ {
+ Method(_CRT, 0, NotSerialized) {
+ Return (C2K(99))
+ }
+
+ Method(_PSV, 0, NotSerialized) {
+ Return (C2K(94))
+ }
+
+ Method(_TMP) {
+ Return (C2K(\_SB.PCI0.LPCB.EC.TMP1))
+ }
+ }
+}
diff --git a/src/mainboard/packard_bell/ms2290/acpi_tables.c b/src/mainboard/packard_bell/ms2290/acpi_tables.c
new file mode 100644
index 0000000..b8979f4
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/acpi_tables.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "southbridge/intel/ibexpeak/nvs.h"
+
+void acpi_create_gnvs(global_nvs_t * gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 1, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2,
+ MP_IRQ_POLARITY_DEFAULT |
+ MP_IRQ_TRIGGER_DEFAULT);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9,
+ MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_LEVEL);
+
+ /* LAPIC_NMI */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 0,
+ MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 1, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 2, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 3, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ /* Not implemented */
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
diff --git a/src/mainboard/packard_bell/ms2290/board_info.txt b/src/mainboard/packard_bell/ms2290/board_info.txt
new file mode 100644
index 0000000..7df53c3
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/board_info.txt
@@ -0,0 +1,6 @@
+Board name: EasyNote LM85 (MS2290)
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
diff --git a/src/mainboard/packard_bell/ms2290/cmos.default b/src/mainboard/packard_bell/ms2290/cmos.default
new file mode 100644
index 0000000..5820bfa
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+last_boot=Fallback
+baud_rate=115200
+debug_level=Spew
+power_on_after_fail=Enable
+nmi=Enable
+sata_mode=AHCI
diff --git a/src/mainboard/packard_bell/ms2290/cmos.layout b/src/mainboard/packard_bell/ms2290/cmos.layout
new file mode 100644
index 0000000..7f73e5f
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/cmos.layout
@@ -0,0 +1,138 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2013 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: northbridge
+424 3 e 10 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+8 0 Secondary
+8 1 Primary
+9 0 AHCI
+9 1 Compatible
+10 0 32M
+10 1 48M
+10 2 64M
+10 3 128M
+10 5 96M
+10 6 160M
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/packard_bell/ms2290/devicetree.cb b/src/mainboard/packard_bell/ms2290/devicetree.cb
new file mode 100644
index 0000000..19f6c9c
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/devicetree.cb
@@ -0,0 +1,104 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/nehalem
+
+ register "gpu_dp_b_hotplug" = "0x04"
+ register "gpu_dp_c_hotplug" = "0x04"
+ register "gpu_dp_d_hotplug" = "0x04"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_up_delay" = "300"
+ register "gpu_panel_power_down_delay" = "300"
+ register "gpu_panel_power_backlight_on_delay" = "3000"
+ register "gpu_panel_power_backlight_off_delay" = "3000"
+ register "gpu_cpu_backlight" = "0x58d"
+ register "gpu_pch_backlight" = "0x061a061a"
+ register "gfx.use_spread_spectrum_clock" = "0"
+ register "gfx.lvds_dual_channel" = "1"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.lvds_num_lanes" = "4"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/model_2065x
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on # Host bridge
+ subsystemid 0x1025 0x0379
+ end
+ device pci 02.0 on # VGA controller
+ subsystemid 0x1025 0x0379
+ end
+ chip southbridge/intel/ibexpeak
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x0b"
+ register "pirqf_routing" = "0x0b"
+ register "pirqg_routing" = "0x0b"
+ register "pirqh_routing" = "0x0b"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi7_routing" = "2"
+ register "gpi8_routing" = "2"
+
+ register "sata_port_map" = "0x11"
+
+ register "gpe0_en" = "0x01800046"
+ register "alt_gp_smi_en" = "0x0000"
+ register "gen1_dec" = "0x040069"
+
+ device pci 1a.0 on # USB2 EHCI
+ subsystemid 0x1025 0x0379
+ end
+
+ device pci 1b.0 on # Audio Controller
+ subsystemid 0x1025 0x0379
+ end
+
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #1
+
+ device pci 1d.0 on # USB2 EHCI
+ subsystemid 0x1025 0x0379
+ end
+ device pci 1f.0 on # PCI-LPC bridge
+ subsystemid 0x1025 0x0379
+ end
+ device pci 1f.2 on # IDE/SATA
+ subsystemid 0x1025 0x0379
+ end
+ device pci 1f.3 on # SMBUS
+ subsystemid 0x1025 0x0379
+ end
+ end
+ end
+end
diff --git a/src/mainboard/packard_bell/ms2290/dsdt.asl b/src/mainboard/packard_bell/ms2290/dsdt.asl
new file mode 100644
index 0000000..f0eb8ec
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/dsdt.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define HAVE_LCD_SCREEN 1
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, /* DSDT revision: ACPI v3.0 */
+ "COREv4", /* OEM id */
+ "COREBOOT", /* OEM table id */
+ 0x20140108 /* OEM revision */
+)
+{
+ /* Some generic macros */
+ #include "acpi/platform.asl"
+
+ /* global NVS and variables */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ /* General Purpose Events */
+ #include "acpi/gpe.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/nehalem/acpi/nehalem.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ Device (UNCR)
+ {
+ Name (_BBN, 0xFF)
+ Name (_ADR, 0x00)
+ Name (RID, 0x00)
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, /* Granularity */
+ 0x00FF, /* Range Minimum */
+ 0x00FF, /* Range Maximum */
+ 0x0000, /* Translation Offset */
+ 0x0001, /* Length */
+ ,, )
+ })
+ Device (SAD)
+ {
+ Name (_ADR, 0x01)
+ Name (RID, 0x00)
+ OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
+ Field (SADC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ PAM0, 8,
+ PAM1, 8,
+ PAM2, 8,
+ PAM3, 8,
+ PAM4, 8,
+ PAM5, 8,
+ PAM6, 8
+ }
+ }
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/packard_bell/ms2290/fadt.c b/src/mainboard/packard_bell/ms2290/fadt.c
new file mode 100644
index 0000000..0639026
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/fadt.c
@@ -0,0 +1,160 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase =
+ pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+ 0x40) & 0xfffe;
+
+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (unsigned long)facs;
+ fadt->dsdt = (unsigned long)dsdt;
+ fadt->model = 0x00;
+ fadt->preferred_pm_profile = PM_MOBILE;
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 0x10;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 0x23;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x32;
+ fadt->iapc_boot_arch = 0x00;
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_DOCKING_SUPPORTED;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 0;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 32;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 0;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 128;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 0;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *)fadt, header->length);
+}
diff --git a/src/mainboard/packard_bell/ms2290/hda_verb.c b/src/mainboard/packard_bell/ms2290/hda_verb.c
new file mode 100644
index 0000000..4ec3b36
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/hda_verb.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Vladimir Serbinenko.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License,
+ * or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */
+ 0x10250379, /* Subsystem ID */
+ 0x00000006, /* Number of 4 dword sets */
+
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x10250379),
+
+ /* NID 0x14. */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x99130110),
+
+ /* NID 0x18. */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830),
+
+ /* NID 0x19. */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x99A30920),
+
+ /* NID 0x1D. */
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x4017992D),
+
+ /* NID 0x21. */
+ AZALIA_PIN_CFG(0x0, 0x21, 0x0321101F),
+
+ 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */
+ 0x80860101, /* Subsystem ID */
+ 0x00000004, /* Number of 4 dword sets */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x04. */
+ AZALIA_PIN_CFG(0x3, 0x04, 0x18560010),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x58560020),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/packard_bell/ms2290/mainboard.c b/src/mainboard/packard_bell/ms2290/mainboard.c
new file mode 100644
index 0000000..c14e9b7
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/mainboard.c
@@ -0,0 +1,136 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <northbridge/intel/nehalem/nehalem.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+
+#include <pc80/mc146818rtc.h>
+#include <arch/x86/include/arch/acpigen.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+#include <drivers/intel/gma/int15.h>
+#include <arch/interrupt.h>
+#endif
+#include <pc80/keyboard.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <smbios.h>
+
+static acpi_cstate_t cst_entries[] = {
+ {1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}},
+ {2, 1, 500, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
+ {2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
+};
+
+int get_cst_entries(acpi_cstate_t ** entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
+
+
+
+static void mainboard_enable(device_t dev)
+{
+ u16 pmbase;
+
+ printk(BIOS_SPEW, "starting SPI configuration\n");
+
+ /* Configure SPI. */
+ RCBA32(0x3800) = 0x07ff0500;
+ RCBA32(0x3804) = 0x3f046008;
+ RCBA32(0x3808) = 0x0058efc0;
+ RCBA32(0x384c) = 0x92000000;
+ RCBA32(0x3850) = 0x00000a0b;
+ RCBA32(0x3858) = 0x07ff0500;
+ RCBA32(0x385c) = 0x04ff0003;
+ RCBA32(0x3860) = 0x00020001;
+ RCBA32(0x3864) = 0x00000fff;
+ RCBA32(0x3874) = 0;
+ RCBA32(0x3890) = 0xf8400000;
+ RCBA32(0x3894) = 0x143b5006;
+ RCBA32(0x3898) = 0x05200302;
+ RCBA32(0x389c) = 0x0601209f;
+ RCBA32(0x38b0) = 0x00000004;
+ RCBA32(0x38b4) = 0x03040002;
+ RCBA32(0x38c0) = 0x00000007;
+ RCBA32(0x38c8) = 0x00002005;
+ RCBA32(0x38c4) = 0x00802005;
+ RCBA32(0x3804) = 0x3f04e008;
+
+ printk(BIOS_SPEW, "SPI configured\n");
+
+ int i;
+ const u8 dmp[256] = {
+ 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11,
+ 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0xf4, 0x01, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x62, 0x01, 0x04, 0x00, 0x08, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0x42, 0x07, 0x09, 0x09, 0xf0, 0x00, 0x00, 0xf0, 0xa9, 0x00, 0x00, 0x06, 0x00, 0x00, 0xff, 0x00,
+ 0x00, 0x01, 0x00, 0x04, 0xff, 0xff, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0b,
+ 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x28, 0x1b, 0x21, 0x00, 0x2c, 0x3b, 0x13, 0x00,
+ 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x55, 0x5a, 0x57, 0x5c, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00,
+ 0x52, 0x10, 0x52, 0x10, 0x64, 0x00, 0x00, 0x00, 0x74, 0x30, 0x00, 0x60, 0x00, 0x00, 0xaf, 0x0b,
+ 0x30, 0x45, 0x2e, 0x30, 0x38, 0x41, 0x43, 0x2e, 0x30, 0x31, 0x2e, 0x31, 0x36, 0x20, 0x00, 0x00,
+ };
+
+ for (i = 0; i < 256; i++)
+ ec_write (i, dmp[i]);
+
+ pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+ PMBASE) & 0xff80;
+
+ printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
+
+ outl(0, pmbase + SMI_EN);
+
+ enable_lapic();
+ pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE,
+ DEFAULT_GPIOBASE | 1);
+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL,
+ 0x10);
+
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2);
+
+ /* This sneaked in here, because EasyNote has no SuperIO chip.
+ */
+ pc_keyboard_init();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/packard_bell/ms2290/romstage.c b/src/mainboard/packard_bell/ms2290/romstage.c
new file mode 100644
index 0000000..c4a278e
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/romstage.c
@@ -0,0 +1,330 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <ec/acpi/ec.h>
+#include <delay.h>
+#include <timestamp.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+
+#include "arch/early_variables.h"
+#include "southbridge/intel/ibexpeak/pch.h"
+#include "northbridge/intel/nehalem/nehalem.h"
+
+#include "northbridge/intel/nehalem/raminit.h"
+#include "southbridge/intel/ibexpeak/me.h"
+
+static void pch_enable_lpc(void)
+{
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMA_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001);
+
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+
+ pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0);
+ pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8);
+
+ pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
+ (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
+
+ pci_write_config32(PCH_LPC_DEV, ETR3,
+ pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
+}
+
+static void rcba_config(void)
+{
+ static const u32 rcba_dump3[] = {
+ /* 30fc */ 0x00000000,
+ /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321,
+ /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002,
+ /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000,
+ /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654,
+ /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210,
+ /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000,
+ /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
+ /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
+ /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,
+ /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
+ /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,
+ /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,
+ /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,
+ /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,
+ /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f,
+ /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,
+ /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,
+ /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
+ /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
+ /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
+ /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,
+ /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,
+ /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
+ /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
+ /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
+ /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,
+ /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000,
+ /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
+ };
+ unsigned i;
+ for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
+ RCBA32(4 * i + 0x30fc) = rcba_dump3[i];
+ (void)RCBA32(4 * i + 0x30fc);
+ }
+}
+
+static inline void write_acpi32(u32 addr, u32 val)
+{
+ outl(val, DEFAULT_PMBASE | addr);
+}
+
+static inline void write_acpi16(u32 addr, u16 val)
+{
+ outw(val, DEFAULT_PMBASE | addr);
+}
+
+static inline u32 read_acpi32(u32 addr)
+{
+ return inl(DEFAULT_PMBASE | addr);
+}
+
+static inline u16 read_acpi16(u32 addr)
+{
+ return inw(DEFAULT_PMBASE | addr);
+}
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+ u32 reg32;
+ int s3resume = 0;
+ const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
+
+ timestamp_init(rdtsc ());
+
+ /* SERR pin is confused on reset. Clear NMI. */
+ outb(4, 0x61);
+ outb(0, 0x61);
+
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ if (bist == 0)
+ enable_lapic();
+
+ nehalem_early_initialization(NEHALEM_MOBILE);
+
+ pch_enable_lpc();
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+ outl (0x796bd9c3, DEFAULT_GPIOBASE);
+ outl (0x86fec7c2, DEFAULT_GPIOBASE + 4);
+ outl (0xe4e8d7fe, DEFAULT_GPIOBASE + 0xc);
+ outl (0, DEFAULT_GPIOBASE + 0x18);
+ outl (0x00004182, DEFAULT_GPIOBASE + 0x2c);
+ outl (0x123360f8, DEFAULT_GPIOBASE + 0x30);
+ outl (0x1f47bfa8, DEFAULT_GPIOBASE + 0x34);
+ outl (0xfffe7fb6, DEFAULT_GPIOBASE + 0x38);
+
+
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ rcba_config();
+
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ /* Read PM1_CNT */
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+ if (((reg32 >> 10) & 7) == 5) {
+ u8 reg8;
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
+ printk(BIOS_DEBUG, "a2: %02x\n", reg8);
+ if (!(reg8 & 0x20)) {
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
+ } else {
+ if (acpi_s3_resume_allowed()) {
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ s3resume = 1;
+ } else {
+ printk(BIOS_DEBUG,
+ "Resume from S3 detected, but disabled.\n");
+ }
+ }
+ }
+
+ /* Enable SMBUS. */
+ enable_smbus();
+
+ write_acpi16(0x2, 0x0);
+ write_acpi32(0x28, 0x0);
+ write_acpi32(0x2c, 0x0);
+ if (!s3resume) {
+ read_acpi32(0x4);
+ read_acpi32(0x20);
+ read_acpi32(0x34);
+ write_acpi16(0x0, 0x900);
+ write_acpi32(0x20, 0xffff7ffe);
+ write_acpi32(0x34, 0x56974);
+ pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
+ pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);
+ }
+
+ early_thermal_init();
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ chipset_init(s3resume);
+ raminit(s3resume, spd_addrmap);
+
+ timestamp_add_now(TS_AFTER_INITRAM);
+
+ intel_early_me_status();
+
+ if (s3resume) {
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ }
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+ if (s3resume) {
+ void *resume_backup_memory;
+
+ resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+ /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+ * through stage 2. We could keep stuff like stack and heap in high tables
+ * memory completely, but that's a wonderful clean up task for another
+ * day.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
+ HIGH_MEMORY_SAVE);
+
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ quick_ram_check();
+ }
+#endif
+
+ timestamp_add_now(TS_END_ROMSTAGE);
+}
diff --git a/src/mainboard/packard_bell/ms2290/smihandler.c b/src/mainboard/packard_bell/ms2290/smihandler.c
new file mode 100644
index 0000000..f04ff90
--- /dev/null
+++ b/src/mainboard/packard_bell/ms2290/smihandler.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/ibexpeak/nvs.h"
+#include "southbridge/intel/ibexpeak/pch.h"
+#include "southbridge/intel/ibexpeak/me.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_2065x/model_2065x.h>
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <delay.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+}
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_2065x_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+ case APM_CNT_ACPI_ENABLE:
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/packardbell/Kconfig b/src/mainboard/packardbell/Kconfig
deleted file mode 100644
index d0712ae..0000000
--- a/src/mainboard/packardbell/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if VENDOR_PACKARDBELL
-
-choice
- prompt "Mainboard model"
-
-config BOARD_PACKARDBELL_MS2290
- bool "EasyNote LM85 (MS2290)"
- help
- EasyNote LM85 laptop
-
-endchoice
-
-source "src/mainboard/packardbell/ms2290/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Packard Bell"
-
-endif # VENDOR_PACKARDBELL
diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig
deleted file mode 100644
index 58053e2..0000000
--- a/src/mainboard/packardbell/ms2290/Kconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-if BOARD_PACKARDBELL_MS2290
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select SYSTEM_TYPE_LAPTOP
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
- select NORTHBRIDGE_INTEL_NEHALEM
- select SOUTHBRIDGE_INTEL_IBEXPEAK
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select BOARD_ROMSIZE_KB_4096
- select HAVE_ACPI_TABLES
- select HAVE_ACPI_RESUME
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select INTEL_INT15
- select EC_ACPI
- select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
-
-config MAINBOARD_DIR
- string
- default packardbell/ms2290
-
-config MAINBOARD_PART_NUMBER
- string
- default "EasyNote LM85"
-
-config MAINBOARD_VERSION
- string
- default "V1.20"
-
-config MAINBOARD_VENDOR
- string
- default "Packard Bell"
-
-config MMCONF_BASE_ADDRESS
- hex
- default 0xe0000000
-
-config IRQ_SLOT_COUNT
- int
- default 18
-
-config USBDEBUG_HCD_INDEX
- int
- default 2
-
-config DRAM_RESET_GATE_GPIO
- int
- default 60
-
-config MAX_CPUS
- int
- default 4
-
-config CPU_ADDR_BITS
- int
- default 36
-
-endif
diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc
deleted file mode 100644
index b47ace2..0000000
--- a/src/mainboard/packardbell/ms2290/Makefile.inc
+++ /dev/null
@@ -1,20 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/packardbell/ms2290/acpi/ac.asl b/src/mainboard/packardbell/ms2290/acpi/ac.asl
deleted file mode 100644
index f9f0a3a..0000000
--- a/src/mainboard/packardbell/ms2290/acpi/ac.asl
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-Device(AC)
-{
- Name(_HID, "ACPI0003")
- Name(_UID, 0x00)
- Name(_PCL, Package() { \_SB } )
-
- Method(_PSR, 0, NotSerialized)
- {
- return (HPAC)
- }
-
- Method(_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
-}
-
-/* AC status change */
-Method(_Q50, 0, NotSerialized)
-{
- Notify (AC, 0x80)
-}
-
-/* AC status change */
-Method(_Q51, 0, NotSerialized)
-{
- Notify (AC, 0x80)
-}
diff --git a/src/mainboard/packardbell/ms2290/acpi/battery.asl b/src/mainboard/packardbell/ms2290/acpi/battery.asl
deleted file mode 100644
index 1ca2cf1..0000000
--- a/src/mainboard/packardbell/ms2290/acpi/battery.asl
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Arg0: Battery
- * Arg1: Battery Status Package
- * Arg2: charging
- * Arg3: discharging
- */
-Method(BSTA, 4, NotSerialized)
-{
- Acquire(ECLK, 0xffff)
- Store(0, Local0)
-
- Store(0, PAGE)
-
- Store(BAPR, Local2)
-
- if (Arg2) // charging
- {
- Or(2, Local0, Local0)
-
- If (LGreaterEqual (Local2, 0x8000)) {
- Store(0, Local2)
- }
- }
-
- if (Arg3) // discharging
- {
- Or(1, Local0, Local0)
- Subtract(0x10000, Local2, Local2)
- }
-
- Store(Local0, Index(Arg1, 0x00))
-
- Store(0, PAGE)
- Store(BARC, Index(Arg1, 2))
- Store(Local2, Index(Arg1, 1))
-
- Store(0, PAGE)
- Store(BAVO, Index(Arg1, 3))
- Release(ECLK)
- Return (Arg1)
-}
-
-Method(BINF, 2, NotSerialized)
-{
- Acquire(ECLK, 0xffff)
- Store(0, PAGE)
- Store(BAFC, Local2)
- Store(1, PAGE)
- Store(BADC, Local1)
-
- Store(Local1, Index(Arg0, 1)) // Design Capacity
- Store(Local2, Index(Arg0, 2)) // Last full charge capacity
- Store(1, PAGE)
- Store(BADV, Index(Arg0, 4)) // Design Voltage
- Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity
-
- Store(1, PAGE)
- Store (BASN, Local0)
- Name (SERN, Buffer (0x06) { " " })
- Store (4, Local1)
- While (Local0)
- {
- Divide (Local0, 0x0A, Local2, Local0)
- Add (Local2, 48, Index (SERN, Local1))
- Decrement (Local1)
- }
- Store (SERN, Index (Arg0, 10)) // Serial Number
-
- Name (TYPE, Buffer() { 0, 0, 0, 0, 0 })
- Store(4, PAGE)
- Store(BATY, TYPE)
- Store(TYPE, Index (Arg0, 11)) // Battery type
- Store(5, PAGE)
- Store(BAOE, Index (Arg0, 12)) // OEM information
- Store(2, PAGE)
- Store(BANA, Index (Arg0, 9)) // Model number
- Release(ECLK)
- Return (Arg0)
-}
-
-Device (BAT0)
-{
- Name (_HID, EisaId ("PNP0C0A"))
- Name (_UID, 0x00)
- Name (_PCL, Package () { \_SB })
-
- Name (BATS, Package ()
- {
- 0x00, // 0: PowerUnit: Report in mWh
- 0xFFFFFFFF, // 1: Design cap
- 0xFFFFFFFF, // 2: Last full charge cap
- 0x01, // 3: Battery Technology
- 10800, // 4: Design Voltage (mV)
- 0x00, // 5: Warning design capacity
- 200, // 6: Low design capacity
- 1, // 7: granularity1
- 1, // 8: granularity2
- "", // 9: Model number
- "", // A: Serial number
- "", // B: Battery Type
- "" // C: OEM information
- })
-
- Method (_BIF, 0, NotSerialized)
- {
- Return (BINF(BATS, 0))
- }
-
- Name (BATI, Package ()
- {
- 0, // Battery State
- // Bit 0 - discharge
- // Bit 1 - charge
- // Bit 2 - critical state
- 0, // Battery present Rate
- 0, // Battery remaining capacity
- 0 // Battery present voltage
- })
-
- Method (_BST, 0, NotSerialized)
- {
- if (B0PR) {
- Return (BSTA(0, BATI, B0CH, B0DI))
- } else {
- Return (BATS)
- }
- }
-
- Method (_STA, 0, NotSerialized)
- {
- if (B0PR) {
- Return (0x1f)
- } else {
- Return (0x0f)
- }
- }
-}
-
-/* Battery attach/detach */
-Method(_Q40, 0, NotSerialized)
-{
- Notify(BAT0, 0x81)
-}
-Method(_Q41, 0, NotSerialized)
-{
- Notify(BAT0, 0x81)
-}
-
-Method(_Q48, 0, NotSerialized)
-{
- Notify(BAT0, 0x80)
-}
-Method(_Q4C, 0, NotSerialized)
-{
- Notify(BAT0, 0x80)
-}
diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl
deleted file mode 100644
index 3735f20..0000000
--- a/src/mainboard/packardbell/ms2290/acpi/ec.asl
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-Device(EC)
-{
- Name (_HID, EISAID("PNP0C09"))
- Name (_UID, 0)
-
- Name (_GPE, 0x17)
- Mutex (ECLK, 0)
-
- OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100)
- Field (ERAM, ByteAcc, NoLock, Preserve)
- {
- Offset (0x8),
- PAGE, 8, /* Information Page Selector */
- Offset (0x70),
- , 1,
- LIDS, 1,
- , 3,
- HPAC, 1,
- Offset (0x88),
- B0PR, 1, /* Battery 0 present */
- B0CH, 1, /* Battery 0 charging */
- B0DI, 1, /* Battery 0 discharging */
- Offset (0xA8),
- TMP0, 8,
- TMP1, 8,
- }
-
- Device(LID)
- {
- Name(_HID, "PNP0C0D")
- Method(_LID, 0, NotSerialized)
- {
- return (LIDS)
- }
- }
-
- Method(_Q52, 0, NotSerialized)
- {
- Notify(LID, 0x80)
- }
-
- Method(_Q53, 0, NotSerialized)
- {
- Notify(^LID, 0x80)
- }
-
- /* PAGE = 0 */
- Field (ERAM, ByteAcc, NoLock, Preserve)
- {
- Offset (0xe0),
- BARC, 16, /* Battery remaining capacity */
- BAFC, 16, /* Battery full charge capacity */
- , 16,
- BAPR, 16, /* Battery present rate */
- BAVO, 16, /* Battery Voltage */
- }
-
- /* PAGE = 1 */
- Field (ERAM, ByteAcc, NoLock, Preserve)
- {
- Offset (0xe0),
- BADC, 16, /* Design Capacity */
- BADV, 16, /* Design voltage */
- BASN, 16
- }
-
- /* PAGE = 2 */
- Field (ERAM, ByteAcc, NoLock, Preserve)
- {
- Offset (0xe0),
- BANA, 128, /* Battery name */
- }
-
- /* PAGE = 4 */
- Field (ERAM, ByteAcc, NoLock, Preserve)
- {
- Offset (0xe0),
- BATY, 128, /* Battery type */
- }
-
- /* PAGE = 5 */
- Field (ERAM, ByteAcc, NoLock, Preserve)
- {
- Offset (0xe0),
- BAOE, 128, /* Battery OEM info */
- }
-
- Method (_CRS, 0)
- {
- Name (ECMD, ResourceTemplate()
- {
- IO (Decode16, 0x62, 0x62, 1, 1)
- IO (Decode16, 0x66, 0x66, 1, 1)
- })
- Return (ECMD)
- }
- Method (_INI, 0, NotSerialized)
- {
- }
-
- /* Decrease brightness. */
- Method(_Q1D, 0, NotSerialized)
- {
- \_SB.PCI0.GFX0.LCD0.DECB()
- }
- /* Increase brightness. */
- Method(_Q1C, 0, NotSerialized)
- {
- \_SB.PCI0.GFX0.LCD0.INCB()
- }
-
-#include "battery.asl"
-#include "ac.asl"
-#include "thermal.asl"
-}
diff --git a/src/mainboard/packardbell/ms2290/acpi/gpe.asl b/src/mainboard/packardbell/ms2290/acpi/gpe.asl
deleted file mode 100644
index cd9d784..0000000
--- a/src/mainboard/packardbell/ms2290/acpi/gpe.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-Scope (\_GPE)
-{
-}
diff --git a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl b/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl
deleted file mode 100644
index 1f782c8..0000000
--- a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Vladimir Serbinenko
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing.
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0001ffff, 0, 0, 0x10 },
- Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
- Package() { 0x0003ffff, 0, 0, 0x10 },
- Package() { 0x0016ffff, 0, 0, 0x10 }, // ME
- Package() { 0x0016ffff, 1, 0, 0x11 }, // ME
- Package() { 0x0016ffff, 2, 0, 0x12 }, // ME
- Package() { 0x0016ffff, 3, 0, 0x13 }, // ME
- Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet
- Package() { 0x001affff, 0, 0, 0x14 }, // USB
- Package() { 0x001affff, 1, 0, 0x15 }, // USB
- Package() { 0x001affff, 2, 0, 0x16 }, // USB
- Package() { 0x001affff, 3, 0, 0x17 }, // USB
- Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
- Package() { 0x001cffff, 0, 0, 0x10 }, // PCI bridge
- Package() { 0x001cffff, 1, 0, 0x11 }, // PCI bridge
- Package() { 0x001cffff, 2, 0, 0x12 }, // PCI bridge
- Package() { 0x001cffff, 3, 0, 0x13 }, // PCI bridge
- Package() { 0x001dffff, 0, 0, 0x10 }, // USB
- Package() { 0x001dffff, 1, 0, 0x11 }, // USB
- Package() { 0x001dffff, 2, 0, 0x12 }, // USB
- Package() { 0x001dffff, 3, 0, 0x13 }, // USB
- Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
- Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
- Package() { 0x001fffff, 2, 0, 0x11 }, // SATA
- Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS
- })
- } Else {
- Return (Package() {
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME
- Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME
- Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME
- Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB
- Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB
- Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCI
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // PCI
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // PCI
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // PCI
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus
- })
- }
-}
diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl
deleted file mode 100644
index a254a9e..0000000
--- a/src/mainboard/packardbell/ms2290/acpi/platform.asl
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* These come from the dynamically created CPU SSDT */
-External(PDC0)
-External(PDC1)
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
- APMC, 8, /* APM command */
- APMS, 8 /* APM status */
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) /* SMI Function */
- Store (0, TRP0) /* Generate trap */
- Return (SMIF) /* Return value of SMI handler */
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
- /* Remember the OS' IRQ routing choice. */
- Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
- /* Not implemented. */
- Return(Package(){0,0})
-}
-
-/* System Bus */
-
-Scope(\_SB)
-{
- /* This method is placed on the top level, so we can make sure it's the
- * first executed _INI method.
- */
- Method(_INI, 0)
- {
- /* The DTS data in NVS is probably not up to date.
- * Update temperature values and make sure AP thermal
- * interrupts can happen
- */
-
- /* TRAP(71) */ /* TODO */
-
- /* Determine the Operating System and save the value in OSYS.
- * We have to do this in order to be able to work around
- * certain windows bugs.
- *
- * OSYS value | Operating System
- * -----------+------------------
- * 2000 | Windows 2000
- * 2001 | Windows XP(+SP1)
- * 2002 | Windows XP SP2
- * 2006 | Windows Vista
- * ???? | Windows 7
- */
-
- /* Let's assume we're running at least Windows 2000 */
- Store (2000, OSYS)
-
- If (CondRefOf(_OSI, Local0)) {
- If (_OSI("Windows 2001")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2001 SP1")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2001 SP2")) {
- Store (2002, OSYS)
- }
-
- If (_OSI("Windows 2001.1")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2001.1 SP1")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2006")) {
- Store (2006, OSYS)
- }
-
- If (_OSI("Windows 2006.1")) {
- Store (2006, OSYS)
- }
-
- If (_OSI("Windows 2006 SP1")) {
- Store (2006, OSYS)
- }
-
- If (_OSI("Windows 2009")) {
- Store (2009, OSYS)
- }
-
- If (_OSI("Windows 2012")) {
- Store (2012, OSYS)
- }
- }
- }
-}
diff --git a/src/mainboard/packardbell/ms2290/acpi/superio.asl b/src/mainboard/packardbell/ms2290/acpi/superio.asl
deleted file mode 100644
index a2657f1..0000000
--- a/src/mainboard/packardbell/ms2290/acpi/superio.asl
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../../../drivers/pc80/ps2_controller.asl"
diff --git a/src/mainboard/packardbell/ms2290/acpi/thermal.asl b/src/mainboard/packardbell/ms2290/acpi/thermal.asl
deleted file mode 100644
index 735171b..0000000
--- a/src/mainboard/packardbell/ms2290/acpi/thermal.asl
+++ /dev/null
@@ -1,48 +0,0 @@
-Scope(\_TZ)
-{
- Name (MEBT, 0)
-
- Method(C2K, 1, NotSerialized)
- {
- Multiply(Arg0, 10, Local0)
- Add (Local0, 2732, Local0)
- if (LLessEqual(Local0, 2732)) {
- Return (3000)
- }
-
- if (LGreater(Local0, 4012)) {
- Return (3000)
- }
- Return (Local0)
- }
-
- ThermalZone(THM0)
- {
- Method(_CRT, 0, NotSerialized) {
- Return (C2K(127))
- }
- Method(_TMP) {
- /* Avoid tripping alarm if ME isn't booted at all yet */
- If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) {
- Return (C2K(40))
- }
- Store (1, MEBT)
- Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
- }
- }
-
- ThermalZone(THM1)
- {
- Method(_CRT, 0, NotSerialized) {
- Return (C2K(99))
- }
-
- Method(_PSV, 0, NotSerialized) {
- Return (C2K(94))
- }
-
- Method(_TMP) {
- Return (C2K(\_SB.PCI0.LPCB.EC.TMP1))
- }
- }
-}
diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c
deleted file mode 100644
index b8979f4..0000000
--- a/src/mainboard/packardbell/ms2290/acpi_tables.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/intel/ibexpeak/nvs.h"
-
-void acpi_create_gnvs(global_nvs_t * gnvs)
-{
- memset((void *)gnvs, 0, sizeof(*gnvs));
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
- gnvs->pcnt = dev_count_cpu();
-
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 1, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2,
- MP_IRQ_POLARITY_DEFAULT |
- MP_IRQ_TRIGGER_DEFAULT);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9,
- MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_LEVEL);
-
- /* LAPIC_NMI */
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 0,
- MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 1, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 2, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 3, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
- /* Not implemented */
- return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
- /* No NUMA, no SRAT */
- return current;
-}
diff --git a/src/mainboard/packardbell/ms2290/board_info.txt b/src/mainboard/packardbell/ms2290/board_info.txt
deleted file mode 100644
index 7df53c3..0000000
--- a/src/mainboard/packardbell/ms2290/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: EasyNote LM85 (MS2290)
-Category: laptop
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: n
diff --git a/src/mainboard/packardbell/ms2290/cmos.default b/src/mainboard/packardbell/ms2290/cmos.default
deleted file mode 100644
index 5820bfa..0000000
--- a/src/mainboard/packardbell/ms2290/cmos.default
+++ /dev/null
@@ -1,7 +0,0 @@
-boot_option=Fallback
-last_boot=Fallback
-baud_rate=115200
-debug_level=Spew
-power_on_after_fail=Enable
-nmi=Enable
-sata_mode=AHCI
diff --git a/src/mainboard/packardbell/ms2290/cmos.layout b/src/mainboard/packardbell/ms2290/cmos.layout
deleted file mode 100644
index 7f73e5f..0000000
--- a/src/mainboard/packardbell/ms2290/cmos.layout
+++ /dev/null
@@ -1,138 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-## Copyright (C) 2013 Vladimir Serbinenko
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-# -----------------------------------------------------------------
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-# -----------------------------------------------------------------
-# Status Register A
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-# -----------------------------------------------------------------
-# Status Register B
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-388 4 r 0 reboot_bits
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392 3 e 5 baud_rate
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-411 1 e 9 sata_mode
-
-# coreboot config options: northbridge
-424 3 e 10 gfx_uma_size
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 1 Emergency
-6 2 Alert
-6 3 Critical
-6 4 Error
-6 5 Warning
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-8 0 Secondary
-8 1 Primary
-9 0 AHCI
-9 1 Compatible
-10 0 32M
-10 1 48M
-10 2 64M
-10 3 128M
-10 5 96M
-10 6 160M
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb
deleted file mode 100644
index 19f6c9c..0000000
--- a/src/mainboard/packardbell/ms2290/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-chip northbridge/intel/nehalem
-
- register "gpu_dp_b_hotplug" = "0x04"
- register "gpu_dp_c_hotplug" = "0x04"
- register "gpu_dp_d_hotplug" = "0x04"
-
- # Enable Panel as LVDS and configure power delays
- register "gpu_panel_port_select" = "0" # LVDS
- register "gpu_panel_power_cycle_delay" = "6"
- register "gpu_panel_power_up_delay" = "300"
- register "gpu_panel_power_down_delay" = "300"
- register "gpu_panel_power_backlight_on_delay" = "3000"
- register "gpu_panel_power_backlight_off_delay" = "3000"
- register "gpu_cpu_backlight" = "0x58d"
- register "gpu_pch_backlight" = "0x061a061a"
- register "gfx.use_spread_spectrum_clock" = "0"
- register "gfx.lvds_dual_channel" = "1"
- register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "4"
-
- device cpu_cluster 0 on
- chip cpu/intel/model_2065x
- device lapic 0 on end
- end
- end
-
- device domain 0 on
- device pci 00.0 on # Host bridge
- subsystemid 0x1025 0x0379
- end
- device pci 02.0 on # VGA controller
- subsystemid 0x1025 0x0379
- end
- chip southbridge/intel/ibexpeak
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
- # GPI routing
- # 0 No effect (default)
- # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
- # 2 SCI (if corresponding GPIO_EN bit is also set)
- register "gpi7_routing" = "2"
- register "gpi8_routing" = "2"
-
- register "sata_port_map" = "0x11"
-
- register "gpe0_en" = "0x01800046"
- register "alt_gp_smi_en" = "0x0000"
- register "gen1_dec" = "0x040069"
-
- device pci 1a.0 on # USB2 EHCI
- subsystemid 0x1025 0x0379
- end
-
- device pci 1b.0 on # Audio Controller
- subsystemid 0x1025 0x0379
- end
-
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #1
-
- device pci 1d.0 on # USB2 EHCI
- subsystemid 0x1025 0x0379
- end
- device pci 1f.0 on # PCI-LPC bridge
- subsystemid 0x1025 0x0379
- end
- device pci 1f.2 on # IDE/SATA
- subsystemid 0x1025 0x0379
- end
- device pci 1f.3 on # SMBUS
- subsystemid 0x1025 0x0379
- end
- end
- end
-end
diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl
deleted file mode 100644
index f0eb8ec..0000000
--- a/src/mainboard/packardbell/ms2290/dsdt.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define HAVE_LCD_SCREEN 1
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x03, /* DSDT revision: ACPI v3.0 */
- "COREv4", /* OEM id */
- "COREBOOT", /* OEM table id */
- 0x20140108 /* OEM revision */
-)
-{
- /* Some generic macros */
- #include "acpi/platform.asl"
-
- /* global NVS and variables */
- #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-
- /* General Purpose Events */
- #include "acpi/gpe.asl"
-
- #include <cpu/intel/model_206ax/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <northbridge/intel/nehalem/acpi/nehalem.asl>
- #include <southbridge/intel/bd82x6x/acpi/pch.asl>
- }
- Device (UNCR)
- {
- Name (_BBN, 0xFF)
- Name (_ADR, 0x00)
- Name (RID, 0x00)
- Name (_HID, EisaId ("PNP0A03"))
- Name (_CRS, ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, /* Granularity */
- 0x00FF, /* Range Minimum */
- 0x00FF, /* Range Maximum */
- 0x0000, /* Translation Offset */
- 0x0001, /* Length */
- ,, )
- })
- Device (SAD)
- {
- Name (_ADR, 0x01)
- Name (RID, 0x00)
- OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
- Field (SADC, DWordAcc, NoLock, Preserve)
- {
- Offset (0x40),
- PAM0, 8,
- PAM1, 8,
- PAM2, 8,
- PAM3, 8,
- PAM4, 8,
- PAM5, 8,
- PAM6, 8
- }
- }
- }
- }
-
- /* Chipset specific sleep states */
- #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
-}
diff --git a/src/mainboard/packardbell/ms2290/fadt.c b/src/mainboard/packardbell/ms2290/fadt.c
deleted file mode 100644
index 0639026..0000000
--- a/src/mainboard/packardbell/ms2290/fadt.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
- u16 pmbase =
- pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
- 0x40) & 0xfffe;
-
- memset((void *)fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = sizeof(acpi_fadt_t);
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl = (unsigned long)facs;
- fadt->dsdt = (unsigned long)dsdt;
- fadt->model = 0x00;
- fadt->preferred_pm_profile = PM_MOBILE;
- fadt->sci_int = 0x9;
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = APM_CNT_PST_CONTROL;
-
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + 0x50;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x20;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 0x10;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = APM_CNT_CST_CONTROL;
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = 0x23;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x32;
- fadt->iapc_boot_arch = 0x00;
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
- ACPI_FADT_DOCKING_SUPPORTED;
-
- fadt->reset_reg.space_id = 0;
- fadt->reset_reg.bit_width = 0;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0x0;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 0;
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 0;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 32;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 0;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 128;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pmbase + 0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 0;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, header->length);
-}
diff --git a/src/mainboard/packardbell/ms2290/hda_verb.c b/src/mainboard/packardbell/ms2290/hda_verb.c
deleted file mode 100644
index 4ec3b36..0000000
--- a/src/mainboard/packardbell/ms2290/hda_verb.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Vladimir Serbinenko.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License,
- * or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */
- 0x10250379, /* Subsystem ID */
- 0x00000006, /* Number of 4 dword sets */
-
- /* NID 0x01: Subsystem ID. */
- AZALIA_SUBVENDOR(0x0, 0x10250379),
-
- /* NID 0x14. */
- AZALIA_PIN_CFG(0x0, 0x14, 0x99130110),
-
- /* NID 0x18. */
- AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830),
-
- /* NID 0x19. */
- AZALIA_PIN_CFG(0x0, 0x19, 0x99A30920),
-
- /* NID 0x1D. */
- AZALIA_PIN_CFG(0x0, 0x1D, 0x4017992D),
-
- /* NID 0x21. */
- AZALIA_PIN_CFG(0x0, 0x21, 0x0321101F),
-
- 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */
- 0x80860101, /* Subsystem ID */
- 0x00000004, /* Number of 4 dword sets */
-
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */
- AZALIA_SUBVENDOR(0x3, 0x80860101),
-
- /* NID 0x04. */
- AZALIA_PIN_CFG(0x3, 0x04, 0x18560010),
-
- /* NID 0x05. */
- AZALIA_PIN_CFG(0x3, 0x05, 0x58560020),
-
- /* NID 0x06. */
- AZALIA_PIN_CFG(0x3, 0x06, 0x58560030),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c
deleted file mode 100644
index c14e9b7..0000000
--- a/src/mainboard/packardbell/ms2290/mainboard.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <delay.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <northbridge/intel/nehalem/nehalem.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <ec/acpi/ec.h>
-
-#include <pc80/mc146818rtc.h>
-#include <arch/x86/include/arch/acpigen.h>
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-#include <drivers/intel/gma/int15.h>
-#include <arch/interrupt.h>
-#endif
-#include <pc80/keyboard.h>
-#include <cpu/x86/lapic.h>
-#include <device/pci.h>
-#include <smbios.h>
-
-static acpi_cstate_t cst_entries[] = {
- {1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}},
- {2, 1, 500, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
- {2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
-};
-
-int get_cst_entries(acpi_cstate_t ** entries)
-{
- *entries = cst_entries;
- return ARRAY_SIZE(cst_entries);
-}
-
-
-
-static void mainboard_enable(device_t dev)
-{
- u16 pmbase;
-
- printk(BIOS_SPEW, "starting SPI configuration\n");
-
- /* Configure SPI. */
- RCBA32(0x3800) = 0x07ff0500;
- RCBA32(0x3804) = 0x3f046008;
- RCBA32(0x3808) = 0x0058efc0;
- RCBA32(0x384c) = 0x92000000;
- RCBA32(0x3850) = 0x00000a0b;
- RCBA32(0x3858) = 0x07ff0500;
- RCBA32(0x385c) = 0x04ff0003;
- RCBA32(0x3860) = 0x00020001;
- RCBA32(0x3864) = 0x00000fff;
- RCBA32(0x3874) = 0;
- RCBA32(0x3890) = 0xf8400000;
- RCBA32(0x3894) = 0x143b5006;
- RCBA32(0x3898) = 0x05200302;
- RCBA32(0x389c) = 0x0601209f;
- RCBA32(0x38b0) = 0x00000004;
- RCBA32(0x38b4) = 0x03040002;
- RCBA32(0x38c0) = 0x00000007;
- RCBA32(0x38c8) = 0x00002005;
- RCBA32(0x38c4) = 0x00802005;
- RCBA32(0x3804) = 0x3f04e008;
-
- printk(BIOS_SPEW, "SPI configured\n");
-
- int i;
- const u8 dmp[256] = {
- 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11,
- 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0xf4, 0x01, 0x00, 0x00, 0x01,
- 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x62, 0x01, 0x04, 0x00, 0x08, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
- 0x42, 0x07, 0x09, 0x09, 0xf0, 0x00, 0x00, 0xf0, 0xa9, 0x00, 0x00, 0x06, 0x00, 0x00, 0xff, 0x00,
- 0x00, 0x01, 0x00, 0x04, 0xff, 0xff, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0b,
- 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x28, 0x1b, 0x21, 0x00, 0x2c, 0x3b, 0x13, 0x00,
- 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x55, 0x5a, 0x57, 0x5c, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00,
- 0x52, 0x10, 0x52, 0x10, 0x64, 0x00, 0x00, 0x00, 0x74, 0x30, 0x00, 0x60, 0x00, 0x00, 0xaf, 0x0b,
- 0x30, 0x45, 0x2e, 0x30, 0x38, 0x41, 0x43, 0x2e, 0x30, 0x31, 0x2e, 0x31, 0x36, 0x20, 0x00, 0x00,
- };
-
- for (i = 0; i < 256; i++)
- ec_write (i, dmp[i]);
-
- pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
- PMBASE) & 0xff80;
-
- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
-
- outl(0, pmbase + SMI_EN);
-
- enable_lapic();
- pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE,
- DEFAULT_GPIOBASE | 1);
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL,
- 0x10);
-
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2);
-
- /* This sneaked in here, because EasyNote has no SuperIO chip.
- */
- pc_keyboard_init();
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
deleted file mode 100644
index c4a278e..0000000
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
-
-#include <stdint.h>
-#include <string.h>
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <lib.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <ec/acpi/ec.h>
-#include <delay.h>
-#include <timestamp.h>
-#include <arch/acpi.h>
-#include <cbmem.h>
-
-#include "arch/early_variables.h"
-#include "southbridge/intel/ibexpeak/pch.h"
-#include "northbridge/intel/nehalem/nehalem.h"
-
-#include "northbridge/intel/nehalem/raminit.h"
-#include "southbridge/intel/ibexpeak/me.h"
-
-static void pch_enable_lpc(void)
-{
- /* Enable EC, PS/2 Keyboard/Mouse */
- pci_write_config16(PCH_LPC_DEV, LPC_EN,
- CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
- COMA_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001);
-
- pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
-
- pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0);
- pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8);
-
- pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
- (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
-
- pci_write_config32(PCH_LPC_DEV, ETR3,
- pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
-}
-
-static void rcba_config(void)
-{
- static const u32 rcba_dump3[] = {
- /* 30fc */ 0x00000000,
- /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321,
- /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002,
- /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000,
- /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654,
- /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210,
- /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000,
- /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
- /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
- /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,
- /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
- /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,
- /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,
- /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,
- /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,
- /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f,
- /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,
- /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,
- /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
- /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
- /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
- /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,
- /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,
- /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
- /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
- /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
- /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
- /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,
- /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000,
- /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
- };
- unsigned i;
- for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
- RCBA32(4 * i + 0x30fc) = rcba_dump3[i];
- (void)RCBA32(4 * i + 0x30fc);
- }
-}
-
-static inline void write_acpi32(u32 addr, u32 val)
-{
- outl(val, DEFAULT_PMBASE | addr);
-}
-
-static inline void write_acpi16(u32 addr, u16 val)
-{
- outw(val, DEFAULT_PMBASE | addr);
-}
-
-static inline u32 read_acpi32(u32 addr)
-{
- return inl(DEFAULT_PMBASE | addr);
-}
-
-static inline u16 read_acpi16(u32 addr)
-{
- return inw(DEFAULT_PMBASE | addr);
-}
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- u32 reg32;
- int s3resume = 0;
- const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
-
- timestamp_init(rdtsc ());
-
- /* SERR pin is confused on reset. Clear NMI. */
- outb(4, 0x61);
- outb(0, 0x61);
-
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- nehalem_early_initialization(NEHALEM_MOBILE);
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
- outl (0x796bd9c3, DEFAULT_GPIOBASE);
- outl (0x86fec7c2, DEFAULT_GPIOBASE + 4);
- outl (0xe4e8d7fe, DEFAULT_GPIOBASE + 0xc);
- outl (0, DEFAULT_GPIOBASE + 0x18);
- outl (0x00004182, DEFAULT_GPIOBASE + 0x2c);
- outl (0x123360f8, DEFAULT_GPIOBASE + 0x30);
- outl (0x1f47bfa8, DEFAULT_GPIOBASE + 0x34);
- outl (0xfffe7fb6, DEFAULT_GPIOBASE + 0x38);
-
-
- /* This should probably go away. Until now it is required
- * and mainboard specific
- */
- rcba_config();
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- u8 reg8;
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
- printk(BIOS_DEBUG, "a2: %02x\n", reg8);
- if (!(reg8 & 0x20)) {
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
- } else {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- } else {
- printk(BIOS_DEBUG,
- "Resume from S3 detected, but disabled.\n");
- }
- }
- }
-
- /* Enable SMBUS. */
- enable_smbus();
-
- write_acpi16(0x2, 0x0);
- write_acpi32(0x28, 0x0);
- write_acpi32(0x2c, 0x0);
- if (!s3resume) {
- read_acpi32(0x4);
- read_acpi32(0x20);
- read_acpi32(0x34);
- write_acpi16(0x0, 0x900);
- write_acpi32(0x20, 0xffff7ffe);
- write_acpi32(0x34, 0x56974);
- pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
- pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);
- }
-
- early_thermal_init();
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- chipset_init(s3resume);
- raminit(s3resume, spd_addrmap);
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- intel_early_me_status();
-
- if (s3resume) {
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- }
-
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume) {
- void *resume_backup_memory;
-
- resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high tables
- * memory completely, but that's a wonderful clean up task for another
- * day.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
- HIGH_MEMORY_SAVE);
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
- } else {
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
- quick_ram_check();
- }
-#endif
-
- timestamp_add_now(TS_END_ROMSTAGE);
-}
diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c
deleted file mode 100644
index f04ff90..0000000
--- a/src/mainboard/packardbell/ms2290/smihandler.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/ibexpeak/nvs.h"
-#include "southbridge/intel/ibexpeak/pch.h"
-#include "southbridge/intel/ibexpeak/me.h"
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <cpu/intel/model_2065x/model_2065x.h>
-#include <ec/acpi/ec.h>
-#include <pc80/mc146818rtc.h>
-#include <delay.h>
-
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern global_nvs_t *gnvs;
-
-static void mainboard_smm_init(void)
-{
- printk(BIOS_DEBUG, "initializing SMI\n");
-}
-
-int mainboard_io_trap_handler(int smif)
-{
- static int smm_initialized;
-
- if (!smm_initialized) {
- mainboard_smm_init();
- smm_initialized = 1;
- }
-
- switch (smif) {
-
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 1
- * On failure, the IO Trap Handler returns a value != 1 */
- return 1;
-}
-
-void mainboard_smi_gpi(u32 gpi_sts)
-{
-}
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 data)
-{
- u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
- u8 tmp;
-
- printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
- data);
-
- if (!pmbase)
- return 0;
-
- switch (data) {
- case APM_CNT_FINALIZE:
- printk(BIOS_DEBUG, "APMC: FINALIZE\n");
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "APMC#: Already finalized\n");
- return 0;
- }
-
- intel_me_finalize_smm();
- intel_pch_finalize_smm();
- intel_sandybridge_finalize_smm();
- intel_model_2065x_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- case APM_CNT_ACPI_ENABLE:
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x02;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
- break;
- case APM_CNT_ACPI_DISABLE:
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
- break;
- default:
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/pc_engines/Kconfig b/src/mainboard/pc_engines/Kconfig
new file mode 100644
index 0000000..1a38add
--- /dev/null
+++ b/src/mainboard/pc_engines/Kconfig
@@ -0,0 +1,26 @@
+if VENDOR_PC_ENGINES
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_PC_ENGINES_ALIX1C
+ bool "ALIX.1C"
+config BOARD_PC_ENGINES_ALIX2C
+ bool "ALIX.2C2 or 2C3"
+config BOARD_PC_ENGINES_ALIX2D
+ bool "ALIX.2D2 or 2D3"
+config BOARD_PC_ENGINES_ALIX6
+ bool "ALIX.6"
+
+endchoice
+
+source "src/mainboard/pc_engines/alix1c/Kconfig"
+source "src/mainboard/pc_engines/alix2c/Kconfig"
+source "src/mainboard/pc_engines/alix2d/Kconfig"
+source "src/mainboard/pc_engines/alix6/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "PC Engines"
+
+endif # VENDOR_PC_ENGINES
diff --git a/src/mainboard/pc_engines/alix1c/Kconfig b/src/mainboard/pc_engines/alix1c/Kconfig
new file mode 100644
index 0000000..8d80746
--- /dev/null
+++ b/src/mainboard/pc_engines/alix1c/Kconfig
@@ -0,0 +1,29 @@
+if BOARD_PC_ENGINES_ALIX1C
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_GEODE_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_512
+ select POWER_BUTTON_DEFAULT_DISABLE
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+
+config MAINBOARD_DIR
+ string
+ default pc_engines/alix1c
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ALIX.1C"
+
+config IRQ_SLOT_COUNT
+ int
+ default 5
+
+endif # BOARD_PC_ENGINES_ALIX1C
diff --git a/src/mainboard/pc_engines/alix1c/board_info.txt b/src/mainboard/pc_engines/alix1c/board_info.txt
new file mode 100644
index 0000000..2cbb76e
--- /dev/null
+++ b/src/mainboard/pc_engines/alix1c/board_info.txt
@@ -0,0 +1,5 @@
+Category: half
+Board URL: http://pc_engines.ch/alix1c.htm
+Flashrom support: y
+Vendor cooperation score: 4
+Vendor cooperation page: PC Engines ALIX.1C Vendor Cooperation Score
diff --git a/src/mainboard/pc_engines/alix1c/cmos.default b/src/mainboard/pc_engines/alix1c/cmos.default
new file mode 100644
index 0000000..189c691
--- /dev/null
+++ b/src/mainboard/pc_engines/alix1c/cmos.default
@@ -0,0 +1,11 @@
+boot_option=Fallback
+last_boot=Fallback
+ECC_memory=Disable
+baud_rate=115200
+power_on_after_fail=Disable
+debug_level=Spew
+boot_first=HDD
+boot_second=Fallback_Floppy
+boot_third=Fallback_Network
+boot_index=0xf
+boot_countdown=0x7f
diff --git a/src/mainboard/pc_engines/alix1c/cmos.layout b/src/mainboard/pc_engines/alix1c/cmos.layout
new file mode 100644
index 0000000..9050c3d
--- /dev/null
+++ b/src/mainboard/pc_engines/alix1c/cmos.layout
@@ -0,0 +1,72 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/pc_engines/alix1c/devicetree.cb b/src/mainboard/pc_engines/alix1c/devicetree.cb
new file mode 100644
index 0000000..85e967a
--- /dev/null
+++ b/src/mainboard/pc_engines/alix1c/devicetree.cb
@@ -0,0 +1,86 @@
+chip northbridge/amd/lx
+ device domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ # How to get these? Boot linux and do this:
+ # rdmsr 0x51400025
+ register "lpc_serirq_enable" = "0x0000105a"
+ # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ # mode is high 10 bits (determined from code)
+ register "lpc_serirq_mode" = "1"
+ # Don't yet know how to find this.
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci f.0 on # ISA Bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 on end # GPIO2
+ device pnp 2e.9 on end # GPIO3
+ device pnp 2e.a on end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci f.1 on end # Flash controller
+ device pci f.2 on end # IDE controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+
+ # APIC cluster is late CPU init.
+ device cpu_cluster 0 on
+ chip cpu/amd/geode_lx
+ device lapic 0 on end
+ end
+ end
+
+end
+
diff --git a/src/mainboard/pc_engines/alix1c/irq_tables.c b/src/mainboard/pc_engines/alix1c/irq_tables.c
new file mode 100644
index 0000000..9ee8a07
--- /dev/null
+++ b/src/mainboard/pc_engines/alix1c/irq_tables.c
@@ -0,0 +1,110 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 10
+#define PIRQC 11
+#define PIRQD 9
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+/*
+ * ALIX1.C interrupt wiring.
+ *
+ * Devices are:
+ *
+ * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
+ * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
+ * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
+ * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
+ * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
+ * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
+ * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
+ * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
+ * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
+ *
+ * The only devices that interrupt are:
+ *
+ * What Device IRQ PIN PIN WIRED TO
+ * -------------------------------------------------
+ * AES 00:01.2 0a 01 A A
+ * 3VPCI 00:0c.0 0a 01 A A
+ * eth0 00:0d.0 0b 01 A B
+ * mpci 00:0e.0 0a 01 A A
+ * usb 00:0f.3 0b 02 B B
+ * usb 00:0f.4 0b 04 D D
+ * usb 00:0f.5 0b 04 D D
+ *
+ * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
+ */
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Miniport data */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* Checksum */
+ {
+ /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
+
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+
+ /* CPU */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* PCI (slot 1) */
+ {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0},
+
+ /* On-board ethernet */
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* Mini PCI (slot 2) */
+ {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
+
+ /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/pc_engines/alix1c/mainboard.c b/src/mainboard/pc_engines/alix1c/mainboard.c
new file mode 100644
index 0000000..8f2031d
--- /dev/null
+++ b/src/mainboard/pc_engines/alix1c/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "ALIX1.C ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "ALIX1.C EXIT %s\n", __func__);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/pc_engines/alix1c/romstage.c b/src/mainboard/pc_engines/alix1c/romstage.c
new file mode 100644
index 0000000..4f80550
--- /dev/null
+++ b/src/mainboard/pc_engines/alix1c/romstage.c
@@ -0,0 +1,169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <spd.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <lib.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include "northbridge/amd/lx/raminit.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+/* The ALIX1.C has no SMBus; the setup is hard-wired. */
+static void cs5536_enable_smbus(void) { }
+
+#include "southbridge/amd/cs5536/early_setup.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+
+/* The part is a Hynix hy5du121622ctp-d43.
+ *
+ * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
+ * Hynix
+ * DDR SDRAM (5D)
+ * VDD 2.5 VDDQ 2.5 (U)
+ * 512M 8K REFRESH (12)
+ * x16 (16)
+ * 4banks (2)
+ * SSTL_2 (2)
+ * 4th GEN die (C)
+ * Normal Power Consumption (<blank> )
+ * TSOP (T)
+ * Single Die (<blank>)
+ * Lead Free (P)
+ * DDR400 3-3-3 (D43)
+ */
+/* SPD array */
+static const u8 spdbytes[] = {
+ [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
+ [SPD_BANK_DENSITY] = 0x40,
+ [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
+ [SPD_MEMORY_TYPE] = 7,
+ [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
+ [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
+ [SPD_NUM_BANKS_PER_SDRAM] = 4,
+ [SPD_PRIMARY_SDRAM_WIDTH] = 8,
+ [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
+ [SPD_NUM_COLUMNS] = 0xa,
+ [SPD_NUM_ROWS] = 3,
+ [SPD_REFRESH] = 0x3a,
+ [SPD_SDRAM_CYCLE_TIME_2ND] = 60,
+ [SPD_SDRAM_CYCLE_TIME_3RD] = 75,
+ [SPD_tRAS] = 40,
+ [SPD_tRCD] = 15,
+ [SPD_tRFC] = 70,
+ [SPD_tRP] = 15,
+ [SPD_tRRD] = 10,
+};
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ print_debug("spd_read_byte dev ");
+ print_debug_hex8(device);
+
+ if (device != DIMM0) {
+ print_debug(" returns 0xff\n");
+ return 0xff;
+ }
+
+ print_debug(" addr ");
+ print_debug_hex8(address);
+ print_debug(" returns ");
+ print_debug_hex8(spdbytes[address]);
+ print_debug("\n");
+
+ return spdbytes[address];
+}
+
+#include "northbridge/amd/lx/pll_reset.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0}},
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* NOTE: Must do this AFTER cs5536_early_setup()!
+ * It is counting on some early MSR setup for the CS5536.
+ */
+ cs5536_disable_internal_uart();
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset();
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Switch from Cache as RAM to real RAM.
+ *
+ * There are two ways we could think about this.
+ *
+ * 1. If we are using the romstage.inc ROMCC way, the stack is
+ * going to be re-setup in the code following this code. Just
+ * wbinvd the stack to clear the cache tags. We don't care
+ * where the stack used to be.
+ *
+ * 2. This file is built as a normal .c -> .o and linked in
+ * etc. The stack might be used to return etc. That means we
+ * care about what is in the stack. If we are smart we set
+ * the CAR stack to the same location as the rest of
+ * coreboot. If that is the case we can just do a wbinvd.
+ * The stack will be written into real RAM that is now setup
+ * and we continue like nothing happened. If the stack is
+ * located somewhere other than where LB would like it, you
+ * need to write some code to do a copy from cache to RAM
+ *
+ * We use method 1 on Norwich and on this board too.
+ */
+ post_code(0x02);
+ print_err("POST 02\n");
+ __asm__("wbinvd\n");
+ print_err("Past wbinvd\n");
+
+ /* We are finding the return does not work on this board. Explicitly
+ * call the label that is after the call to us. This is gross, but
+ * sometimes at this level it is the only way out.
+ */
+ done_cache_as_ram_main();
+}
diff --git a/src/mainboard/pc_engines/alix2c/Kconfig b/src/mainboard/pc_engines/alix2c/Kconfig
new file mode 100644
index 0000000..24a9772
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2c/Kconfig
@@ -0,0 +1,9 @@
+if BOARD_PC_ENGINES_ALIX2C
+
+# Dummy for abuild
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ALIX.2C"
+
+endif
diff --git a/src/mainboard/pc_engines/alix2c/board_info.txt b/src/mainboard/pc_engines/alix2c/board_info.txt
new file mode 100644
index 0000000..429c1e5
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2c/board_info.txt
@@ -0,0 +1,4 @@
+Category: half
+Board URL: http://pc_engines.ch/alix2c3.htm
+Flashrom support: y
+Clone of: pc_engines/alix2d
diff --git a/src/mainboard/pc_engines/alix2d/Kconfig b/src/mainboard/pc_engines/alix2d/Kconfig
new file mode 100644
index 0000000..f9cfec2
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2d/Kconfig
@@ -0,0 +1,30 @@
+if BOARD_PC_ENGINES_ALIX2C || BOARD_PC_ENGINES_ALIX2D || BOARD_PC_ENGINES_ALIX6
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_GEODE_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_512
+ select POWER_BUTTON_FORCE_DISABLE
+
+config MAINBOARD_DIR
+ string
+ default pc_engines/alix2d
+
+if BOARD_PC_ENGINES_ALIX2D
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ALIX.2D"
+
+endif
+
+config IRQ_SLOT_COUNT
+ int
+ default 7
+
+endif # BOARD_PC_ENGINES_ALIX2C || BOARD_PC_ENGINES_ALIX2D || BOARD_PC_ENGINES_ALIX6
diff --git a/src/mainboard/pc_engines/alix2d/board_info.txt b/src/mainboard/pc_engines/alix2d/board_info.txt
new file mode 100644
index 0000000..f52967f
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2d/board_info.txt
@@ -0,0 +1,3 @@
+Category: half
+Board URL: http://pc_engines.ch/alix2d0.htm
+Flashrom support: y
diff --git a/src/mainboard/pc_engines/alix2d/cmos.layout b/src/mainboard/pc_engines/alix2d/cmos.layout
new file mode 100644
index 0000000..9050c3d
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2d/cmos.layout
@@ -0,0 +1,72 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/pc_engines/alix2d/devicetree.cb b/src/mainboard/pc_engines/alix2d/devicetree.cb
new file mode 100644
index 0000000..d8aa3bc
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2d/devicetree.cb
@@ -0,0 +1,46 @@
+chip northbridge/amd/lx
+ device domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ # How to get these? Boot linux and do this:
+ # rdmsr 0x51400025
+ register "lpc_serirq_enable" = "0x00001002"
+ # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+ register "lpc_serirq_polarity" = "0x0000EFFD"
+ # mode is high 10 bits (determined from code)
+ register "lpc_serirq_mode" = "1"
+ # Don't yet know how to find this.
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "1"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "1" # Wired on Alix.2D13 only
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired)
+ register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired)
+ register "unwanted_vpci[2]" = "0" # End of list has a zero
+ device pci f.0 on end # ISA Bridge
+ device pci f.1 on end # Flash controller
+ device pci f.2 on end # IDE controller
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+
+ # APIC cluster is late CPU init.
+ device cpu_cluster 0 on
+ chip cpu/amd/geode_lx
+ device lapic 0 on end
+ end
+ end
+
+end
+
diff --git a/src/mainboard/pc_engines/alix2d/irq_tables.c b/src/mainboard/pc_engines/alix2d/irq_tables.c
new file mode 100644
index 0000000..cdfaa88
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2d/irq_tables.c
@@ -0,0 +1,117 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 10
+#define PIRQC 11
+#define PIRQD 9
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+/*
+ * ALIX.2D3 interrupt wiring.
+ *
+ * Devices are:
+ * 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33)
+ * 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]
+ * 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
+ * 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
+ * 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
+ * 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03)
+ * 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01)
+ * 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02)
+ * 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)
+
+ * The only devices that interrupt are:
+ *
+ * What Device IRQ PIN PIN WIRED TO
+ * -------------------------------------------------
+ * AES 00:01.2 0a 01 A A
+ * eth0 00:09.0 0b 01 A B
+ * eth1 00:0a.0 0b 01 A C
+ * eth2 00:0b.0 0b 01 A D
+ * mpci 00:0c.0 0a 01 A A
+ * mpci 00:0c.0 0b 02 B B
+ * usb 00:0f.4 0b 04 D D
+ * usb 00:0f.5 0b 04 D D
+ *
+ * The only swizzled interrupts are the ethernet controllers, where INTA is wired to
+ * interrupt controller lines B, C and D.
+ */
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Miniport data */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* Checksum */
+ {
+ /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
+
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+
+ /* CPU */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* On-board ethernet (Left) */
+ {0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* On-board ethernet (Middle, ALIX.2D3 only) */
+ {0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* On-board ethernet (Right) */
+ {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* Mini PCI (slot 1) */
+ {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* Mini PCI (slot 2, ALIX.2D2 only) */
+ {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/pc_engines/alix2d/mainboard.c b/src/mainboard/pc_engines/alix2d/mainboard.c
new file mode 100644
index 0000000..3cd08c8
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2d/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "ALIX.2D ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "ALIX.2D EXIT %s\n", __func__);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/pc_engines/alix2d/romstage.c b/src/mainboard/pc_engines/alix2d/romstage.c
new file mode 100644
index 0000000..52c5310
--- /dev/null
+++ b/src/mainboard/pc_engines/alix2d/romstage.c
@@ -0,0 +1,192 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <spd.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <lib.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include "northbridge/amd/lx/raminit.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+/* The ALIX.2D has no SMBus; the setup is hard-wired. */
+static void cs5536_enable_smbus(void) { }
+
+#include "southbridge/amd/cs5536/early_setup.c"
+
+/* The part is a Hynix hy5du121622ctp-d43.
+ *
+ * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
+ * Hynix
+ * DDR SDRAM (5D)
+ * VDD 2.5 VDDQ 2.5 (U)
+ * 512M 8K REFRESH (12)
+ * x16 (16)
+ * 4banks (2)
+ * SSTL_2 (2)
+ * 4th GEN die (C)
+ * Normal Power Consumption (<blank> )
+ * TSOP (T)
+ * Single Die (<blank>)
+ * Lead Free (P)
+ * DDR400 3-3-3 (D43)
+ */
+/* SPD array */
+static const u8 spdbytes[] = {
+ [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
+ [SPD_BANK_DENSITY] = 0x40,
+ [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
+ [SPD_MEMORY_TYPE] = 7,
+ [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
+ [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
+ [SPD_NUM_BANKS_PER_SDRAM] = 4,
+ [SPD_PRIMARY_SDRAM_WIDTH] = 8,
+ [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
+ [SPD_NUM_COLUMNS] = 0xa,
+ [SPD_NUM_ROWS] = 3,
+ [SPD_REFRESH] = 0x3a,
+ [SPD_SDRAM_CYCLE_TIME_2ND] = 60,
+ [SPD_SDRAM_CYCLE_TIME_3RD] = 75,
+ [SPD_tRAS] = 40,
+ [SPD_tRCD] = 15,
+ [SPD_tRFC] = 70,
+ [SPD_tRP] = 15,
+ [SPD_tRRD] = 10,
+};
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ print_debug("spd_read_byte dev ");
+ print_debug_hex8(device);
+
+ if (device != DIMM0) {
+ print_debug(" returns 0xff\n");
+ return 0xff;
+ }
+
+ print_debug(" addr ");
+ print_debug_hex8(address);
+ print_debug(" returns ");
+ print_debug_hex8(spdbytes[address]);
+ print_debug("\n");
+
+ return spdbytes[address];
+}
+
+#include "northbridge/amd/lx/pll_reset.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
+
+/** Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+ /*
+ * Enable LEDs GPIO outputs to light up the leds
+ * This is how the original tinyBIOS sets them after boot.
+ * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
+ * may be used here, but not after PCI Init.
+ * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
+ * leds-alix2.c driver. Coreboot dynamically assigns this space,
+ * so the driver does not work anymore.
+ * Good workaround: use the newer driver
+ * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
+ * This resets the GPIO I/O space to 0x6100.
+ * This may break other things, though.
+ */
+ outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+ outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
+ outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
+
+ /* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
+ outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
+ outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
+}
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0}},
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* NOTE: Must do this AFTER cs5536_early_setup()!
+ * It is counting on some early MSR setup for the CS5536.
+ */
+ cs5536_setup_onchipuart(1);
+ mb_gpio_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset();
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Switch from Cache as RAM to real RAM.
+ *
+ * There are two ways we could think about this.
+ *
+ * 1. If we are using the romstage.inc ROMCC way, the stack is
+ * going to be re-setup in the code following this code. Just
+ * wbinvd the stack to clear the cache tags. We don't care
+ * where the stack used to be.
+ *
+ * 2. This file is built as a normal .c -> .o and linked in
+ * etc. The stack might be used to return etc. That means we
+ * care about what is in the stack. If we are smart we set
+ * the CAR stack to the same location as the rest of
+ * coreboot. If that is the case we can just do a wbinvd.
+ * The stack will be written into real RAM that is now setup
+ * and we continue like nothing happened. If the stack is
+ * located somewhere other than where LB would like it, you
+ * need to write some code to do a copy from cache to RAM
+ *
+ * We use method 1 on Norwich and on this board too.
+ */
+ post_code(0x02);
+ print_err("POST 02\n");
+ __asm__("wbinvd\n");
+ print_err("Past wbinvd\n");
+
+ /* We are finding the return does not work on this board. Explicitly
+ * call the label that is after the call to us. This is gross, but
+ * sometimes at this level it is the only way out.
+ */
+ done_cache_as_ram_main();
+}
diff --git a/src/mainboard/pc_engines/alix6/Kconfig b/src/mainboard/pc_engines/alix6/Kconfig
new file mode 100644
index 0000000..7432a42
--- /dev/null
+++ b/src/mainboard/pc_engines/alix6/Kconfig
@@ -0,0 +1,9 @@
+if BOARD_PC_ENGINES_ALIX6
+
+# Dummy for abuild
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ALIX.6"
+
+endif
diff --git a/src/mainboard/pc_engines/alix6/board_info.txt b/src/mainboard/pc_engines/alix6/board_info.txt
new file mode 100644
index 0000000..32acd41
--- /dev/null
+++ b/src/mainboard/pc_engines/alix6/board_info.txt
@@ -0,0 +1,5 @@
+Category: half
+Board URL: http://pc_engines.ch/alix6f2.htm
+Flashrom support: y
+Clone of: pc_engines/alix2d
+
diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig
deleted file mode 100644
index 9fb477b..0000000
--- a/src/mainboard/pcengines/Kconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-if VENDOR_PCENGINES
-
-choice
- prompt "Mainboard model"
-
-config BOARD_PCENGINES_ALIX1C
- bool "ALIX.1C"
-config BOARD_PCENGINES_ALIX2C
- bool "ALIX.2C2 or 2C3"
-config BOARD_PCENGINES_ALIX2D
- bool "ALIX.2D2 or 2D3"
-config BOARD_PCENGINES_ALIX6
- bool "ALIX.6"
-
-endchoice
-
-source "src/mainboard/pcengines/alix1c/Kconfig"
-source "src/mainboard/pcengines/alix2c/Kconfig"
-source "src/mainboard/pcengines/alix2d/Kconfig"
-source "src/mainboard/pcengines/alix6/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "PC Engines"
-
-endif # VENDOR_PCENGINES
diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig
deleted file mode 100644
index bbd78a3..0000000
--- a/src/mainboard/pcengines/alix1c/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-if BOARD_PCENGINES_ALIX1C
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_GEODE_LX
- select NORTHBRIDGE_AMD_LX
- select SOUTHBRIDGE_AMD_CS5536
- select SUPERIO_WINBOND_W83627HF
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_512
- select POWER_BUTTON_DEFAULT_DISABLE
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
-
-config MAINBOARD_DIR
- string
- default pcengines/alix1c
-
-config MAINBOARD_PART_NUMBER
- string
- default "ALIX.1C"
-
-config IRQ_SLOT_COUNT
- int
- default 5
-
-endif # BOARD_PCENGINES_ALIX1C
diff --git a/src/mainboard/pcengines/alix1c/board_info.txt b/src/mainboard/pcengines/alix1c/board_info.txt
deleted file mode 100644
index d1e1417..0000000
--- a/src/mainboard/pcengines/alix1c/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: half
-Board URL: http://pcengines.ch/alix1c.htm
-Flashrom support: y
-Vendor cooperation score: 4
-Vendor cooperation page: PC Engines ALIX.1C Vendor Cooperation Score
diff --git a/src/mainboard/pcengines/alix1c/cmos.default b/src/mainboard/pcengines/alix1c/cmos.default
deleted file mode 100644
index 189c691..0000000
--- a/src/mainboard/pcengines/alix1c/cmos.default
+++ /dev/null
@@ -1,11 +0,0 @@
-boot_option=Fallback
-last_boot=Fallback
-ECC_memory=Disable
-baud_rate=115200
-power_on_after_fail=Disable
-debug_level=Spew
-boot_first=HDD
-boot_second=Fallback_Floppy
-boot_third=Fallback_Network
-boot_index=0xf
-boot_countdown=0x7f
diff --git a/src/mainboard/pcengines/alix1c/cmos.layout b/src/mainboard/pcengines/alix1c/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/pcengines/alix1c/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb
deleted file mode 100644
index 85e967a..0000000
--- a/src/mainboard/pcengines/alix1c/devicetree.cb
+++ /dev/null
@@ -1,86 +0,0 @@
-chip northbridge/amd/lx
- device domain 0 on
- device pci 1.0 on end
- device pci 1.1 on end
- chip southbridge/amd/cs5536
- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
- # SIRQ Mode = Active(Quiet) mode. Save power....
- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
- # How to get these? Boot linux and do this:
- # rdmsr 0x51400025
- register "lpc_serirq_enable" = "0x0000105a"
- # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
- register "lpc_serirq_polarity" = "0x0000EFA5"
- # mode is high 10 bits (determined from code)
- register "lpc_serirq_mode" = "1"
- # Don't yet know how to find this.
- register "enable_gpio_int_route" = "0x0D0C0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "0" #0: host, 1:device
- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "0"
- register "com1_address" = "0x3F8"
- register "com1_irq" = "4"
- register "com2_enable" = "0"
- register "com2_address" = "0x2F8"
- register "com2_irq" = "3"
- register "unwanted_vpci[0]" = "0" # End of list has a zero
- device pci f.0 on # ISA Bridge
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 on end # GPIO2
- device pnp 2e.9 on end # GPIO3
- device pnp 2e.a on end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci f.1 on end # Flash controller
- device pci f.2 on end # IDE controller
- device pci f.3 on end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
-
- # APIC cluster is late CPU init.
- device cpu_cluster 0 on
- chip cpu/amd/geode_lx
- device lapic 0 on end
- end
- end
-
-end
-
diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c
deleted file mode 100644
index 9ee8a07..0000000
--- a/src/mainboard/pcengines/alix1c/irq_tables.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright (C) 2007 Advanced Micro Devices, Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 10
-#define PIRQC 11
-#define PIRQD 9
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-/*
- * ALIX1.C interrupt wiring.
- *
- * Devices are:
- *
- * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
- * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
- * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
- * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
- * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
- * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
- * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
- * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
- * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
- *
- * The only devices that interrupt are:
- *
- * What Device IRQ PIN PIN WIRED TO
- * -------------------------------------------------
- * AES 00:01.2 0a 01 A A
- * 3VPCI 00:0c.0 0a 01 A A
- * eth0 00:0d.0 0b 01 A B
- * mpci 00:0e.0 0a 01 A A
- * usb 00:0f.3 0b 02 B B
- * usb 00:0f.4 0b 04 D D
- * usb 00:0f.5 0b 04 D D
- *
- * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
- */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Miniport data */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* Checksum */
- {
- /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
-
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-
- /* CPU */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* PCI (slot 1) */
- {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0},
-
- /* On-board ethernet */
- {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* Mini PCI (slot 2) */
- {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
-
- /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/pcengines/alix1c/mainboard.c b/src/mainboard/pcengines/alix1c/mainboard.c
deleted file mode 100644
index 8f2031d..0000000
--- a/src/mainboard/pcengines/alix1c/mainboard.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "ALIX1.C ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "ALIX1.C EXIT %s\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
deleted file mode 100644
index 4f80550..0000000
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <spd.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <console/console.h>
-#include <lib.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/lxdef.h>
-#include <cpu/amd/car.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-#include "northbridge/amd/lx/raminit.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* The ALIX1.C has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void) { }
-
-#include "southbridge/amd/cs5536/early_setup.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-
-/* The part is a Hynix hy5du121622ctp-d43.
- *
- * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
- * Hynix
- * DDR SDRAM (5D)
- * VDD 2.5 VDDQ 2.5 (U)
- * 512M 8K REFRESH (12)
- * x16 (16)
- * 4banks (2)
- * SSTL_2 (2)
- * 4th GEN die (C)
- * Normal Power Consumption (<blank> )
- * TSOP (T)
- * Single Die (<blank>)
- * Lead Free (P)
- * DDR400 3-3-3 (D43)
- */
-/* SPD array */
-static const u8 spdbytes[] = {
- [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
- [SPD_BANK_DENSITY] = 0x40,
- [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
- [SPD_MEMORY_TYPE] = 7,
- [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
- [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
- [SPD_NUM_BANKS_PER_SDRAM] = 4,
- [SPD_PRIMARY_SDRAM_WIDTH] = 8,
- [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
- [SPD_NUM_COLUMNS] = 0xa,
- [SPD_NUM_ROWS] = 3,
- [SPD_REFRESH] = 0x3a,
- [SPD_SDRAM_CYCLE_TIME_2ND] = 60,
- [SPD_SDRAM_CYCLE_TIME_3RD] = 75,
- [SPD_tRAS] = 40,
- [SPD_tRCD] = 15,
- [SPD_tRFC] = 70,
- [SPD_tRP] = 15,
- [SPD_tRRD] = 10,
-};
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- print_debug("spd_read_byte dev ");
- print_debug_hex8(device);
-
- if (device != DIMM0) {
- print_debug(" returns 0xff\n");
- return 0xff;
- }
-
- print_debug(" addr ");
- print_debug_hex8(address);
- print_debug(" returns ");
- print_debug_hex8(spdbytes[address]);
- print_debug("\n");
-
- return spdbytes[address];
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- static const struct mem_controller memctrl[] = {
- {.channel0 = {DIMM0}},
- };
-
- SystemPreInit();
- msr_init();
-
- cs5536_early_setup();
-
- /* NOTE: Must do this AFTER cs5536_early_setup()!
- * It is counting on some early MSR setup for the CS5536.
- */
- cs5536_disable_internal_uart();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pll_reset();
-
- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
- sdram_initialize(1, memctrl);
-
- /* Switch from Cache as RAM to real RAM.
- *
- * There are two ways we could think about this.
- *
- * 1. If we are using the romstage.inc ROMCC way, the stack is
- * going to be re-setup in the code following this code. Just
- * wbinvd the stack to clear the cache tags. We don't care
- * where the stack used to be.
- *
- * 2. This file is built as a normal .c -> .o and linked in
- * etc. The stack might be used to return etc. That means we
- * care about what is in the stack. If we are smart we set
- * the CAR stack to the same location as the rest of
- * coreboot. If that is the case we can just do a wbinvd.
- * The stack will be written into real RAM that is now setup
- * and we continue like nothing happened. If the stack is
- * located somewhere other than where LB would like it, you
- * need to write some code to do a copy from cache to RAM
- *
- * We use method 1 on Norwich and on this board too.
- */
- post_code(0x02);
- print_err("POST 02\n");
- __asm__("wbinvd\n");
- print_err("Past wbinvd\n");
-
- /* We are finding the return does not work on this board. Explicitly
- * call the label that is after the call to us. This is gross, but
- * sometimes at this level it is the only way out.
- */
- done_cache_as_ram_main();
-}
diff --git a/src/mainboard/pcengines/alix2c/Kconfig b/src/mainboard/pcengines/alix2c/Kconfig
deleted file mode 100644
index 8bed484..0000000
--- a/src/mainboard/pcengines/alix2c/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if BOARD_PCENGINES_ALIX2C
-
-# Dummy for abuild
-
-config MAINBOARD_PART_NUMBER
- string
- default "ALIX.2C"
-
-endif
diff --git a/src/mainboard/pcengines/alix2c/board_info.txt b/src/mainboard/pcengines/alix2c/board_info.txt
deleted file mode 100644
index b039edc..0000000
--- a/src/mainboard/pcengines/alix2c/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: half
-Board URL: http://pcengines.ch/alix2c3.htm
-Flashrom support: y
-Clone of: pcengines/alix2d
diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
deleted file mode 100644
index a350e11..0000000
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-if BOARD_PCENGINES_ALIX2C || BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_GEODE_LX
- select NORTHBRIDGE_AMD_LX
- select SOUTHBRIDGE_AMD_CS5536
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_512
- select POWER_BUTTON_FORCE_DISABLE
-
-config MAINBOARD_DIR
- string
- default pcengines/alix2d
-
-if BOARD_PCENGINES_ALIX2D
-
-config MAINBOARD_PART_NUMBER
- string
- default "ALIX.2D"
-
-endif
-
-config IRQ_SLOT_COUNT
- int
- default 7
-
-endif # BOARD_PCENGINES_ALIX2C || BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6
diff --git a/src/mainboard/pcengines/alix2d/board_info.txt b/src/mainboard/pcengines/alix2d/board_info.txt
deleted file mode 100644
index 0b63050..0000000
--- a/src/mainboard/pcengines/alix2d/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: half
-Board URL: http://pcengines.ch/alix2d0.htm
-Flashrom support: y
diff --git a/src/mainboard/pcengines/alix2d/cmos.layout b/src/mainboard/pcengines/alix2d/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/pcengines/alix2d/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb
deleted file mode 100644
index d8aa3bc..0000000
--- a/src/mainboard/pcengines/alix2d/devicetree.cb
+++ /dev/null
@@ -1,46 +0,0 @@
-chip northbridge/amd/lx
- device domain 0 on
- device pci 1.0 on end
- device pci 1.1 on end
- chip southbridge/amd/cs5536
- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
- # SIRQ Mode = Active(Quiet) mode. Save power....
- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
- # How to get these? Boot linux and do this:
- # rdmsr 0x51400025
- register "lpc_serirq_enable" = "0x00001002"
- # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
- register "lpc_serirq_polarity" = "0x0000EFFD"
- # mode is high 10 bits (determined from code)
- register "lpc_serirq_mode" = "1"
- # Don't yet know how to find this.
- register "enable_gpio_int_route" = "0x0D0C0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "0" #0: host, 1:device
- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "1"
- register "com1_address" = "0x3F8"
- register "com1_irq" = "4"
- register "com2_enable" = "1" # Wired on Alix.2D13 only
- register "com2_address" = "0x2F8"
- register "com2_irq" = "3"
- register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired)
- register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired)
- register "unwanted_vpci[2]" = "0" # End of list has a zero
- device pci f.0 on end # ISA Bridge
- device pci f.1 on end # Flash controller
- device pci f.2 on end # IDE controller
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
-
- # APIC cluster is late CPU init.
- device cpu_cluster 0 on
- chip cpu/amd/geode_lx
- device lapic 0 on end
- end
- end
-
-end
-
diff --git a/src/mainboard/pcengines/alix2d/irq_tables.c b/src/mainboard/pcengines/alix2d/irq_tables.c
deleted file mode 100644
index cdfaa88..0000000
--- a/src/mainboard/pcengines/alix2d/irq_tables.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright (C) 2007 Advanced Micro Devices, Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 10
-#define PIRQC 11
-#define PIRQD 9
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-/*
- * ALIX.2D3 interrupt wiring.
- *
- * Devices are:
- * 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33)
- * 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]
- * 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
- * 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
- * 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
- * 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03)
- * 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01)
- * 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02)
- * 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)
-
- * The only devices that interrupt are:
- *
- * What Device IRQ PIN PIN WIRED TO
- * -------------------------------------------------
- * AES 00:01.2 0a 01 A A
- * eth0 00:09.0 0b 01 A B
- * eth1 00:0a.0 0b 01 A C
- * eth2 00:0b.0 0b 01 A D
- * mpci 00:0c.0 0a 01 A A
- * mpci 00:0c.0 0b 02 B B
- * usb 00:0f.4 0b 04 D D
- * usb 00:0f.5 0b 04 D D
- *
- * The only swizzled interrupts are the ethernet controllers, where INTA is wired to
- * interrupt controller lines B, C and D.
- */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Miniport data */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* Checksum */
- {
- /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
-
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-
- /* CPU */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* On-board ethernet (Left) */
- {0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* On-board ethernet (Middle, ALIX.2D3 only) */
- {0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* On-board ethernet (Right) */
- {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* Mini PCI (slot 1) */
- {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* Mini PCI (slot 2, ALIX.2D2 only) */
- {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/pcengines/alix2d/mainboard.c b/src/mainboard/pcengines/alix2d/mainboard.c
deleted file mode 100644
index 3cd08c8..0000000
--- a/src/mainboard/pcengines/alix2d/mainboard.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "ALIX.2D ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "ALIX.2D EXIT %s\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
deleted file mode 100644
index 52c5310..0000000
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <spd.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <console/console.h>
-#include <lib.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/lxdef.h>
-#include <cpu/amd/car.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-#include "northbridge/amd/lx/raminit.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* The ALIX.2D has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void) { }
-
-#include "southbridge/amd/cs5536/early_setup.c"
-
-/* The part is a Hynix hy5du121622ctp-d43.
- *
- * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
- * Hynix
- * DDR SDRAM (5D)
- * VDD 2.5 VDDQ 2.5 (U)
- * 512M 8K REFRESH (12)
- * x16 (16)
- * 4banks (2)
- * SSTL_2 (2)
- * 4th GEN die (C)
- * Normal Power Consumption (<blank> )
- * TSOP (T)
- * Single Die (<blank>)
- * Lead Free (P)
- * DDR400 3-3-3 (D43)
- */
-/* SPD array */
-static const u8 spdbytes[] = {
- [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
- [SPD_BANK_DENSITY] = 0x40,
- [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
- [SPD_MEMORY_TYPE] = 7,
- [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
- [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
- [SPD_NUM_BANKS_PER_SDRAM] = 4,
- [SPD_PRIMARY_SDRAM_WIDTH] = 8,
- [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
- [SPD_NUM_COLUMNS] = 0xa,
- [SPD_NUM_ROWS] = 3,
- [SPD_REFRESH] = 0x3a,
- [SPD_SDRAM_CYCLE_TIME_2ND] = 60,
- [SPD_SDRAM_CYCLE_TIME_3RD] = 75,
- [SPD_tRAS] = 40,
- [SPD_tRCD] = 15,
- [SPD_tRFC] = 70,
- [SPD_tRP] = 15,
- [SPD_tRRD] = 10,
-};
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- print_debug("spd_read_byte dev ");
- print_debug_hex8(device);
-
- if (device != DIMM0) {
- print_debug(" returns 0xff\n");
- return 0xff;
- }
-
- print_debug(" addr ");
- print_debug_hex8(address);
- print_debug(" returns ");
- print_debug_hex8(spdbytes[address]);
- print_debug("\n");
-
- return spdbytes[address];
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-/** Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
- /*
- * Enable LEDs GPIO outputs to light up the leds
- * This is how the original tinyBIOS sets them after boot.
- * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
- * may be used here, but not after PCI Init.
- * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
- * leds-alix2.c driver. Coreboot dynamically assigns this space,
- * so the driver does not work anymore.
- * Good workaround: use the newer driver
- * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
- * This resets the GPIO I/O space to 0x6100.
- * This may break other things, though.
- */
- outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
- outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
- outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
-
- /* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
- outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
- outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
-}
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- static const struct mem_controller memctrl[] = {
- {.channel0 = {DIMM0}},
- };
-
- SystemPreInit();
- msr_init();
-
- cs5536_early_setup();
-
- /* NOTE: Must do this AFTER cs5536_early_setup()!
- * It is counting on some early MSR setup for the CS5536.
- */
- cs5536_setup_onchipuart(1);
- mb_gpio_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pll_reset();
-
- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
- sdram_initialize(1, memctrl);
-
- /* Switch from Cache as RAM to real RAM.
- *
- * There are two ways we could think about this.
- *
- * 1. If we are using the romstage.inc ROMCC way, the stack is
- * going to be re-setup in the code following this code. Just
- * wbinvd the stack to clear the cache tags. We don't care
- * where the stack used to be.
- *
- * 2. This file is built as a normal .c -> .o and linked in
- * etc. The stack might be used to return etc. That means we
- * care about what is in the stack. If we are smart we set
- * the CAR stack to the same location as the rest of
- * coreboot. If that is the case we can just do a wbinvd.
- * The stack will be written into real RAM that is now setup
- * and we continue like nothing happened. If the stack is
- * located somewhere other than where LB would like it, you
- * need to write some code to do a copy from cache to RAM
- *
- * We use method 1 on Norwich and on this board too.
- */
- post_code(0x02);
- print_err("POST 02\n");
- __asm__("wbinvd\n");
- print_err("Past wbinvd\n");
-
- /* We are finding the return does not work on this board. Explicitly
- * call the label that is after the call to us. This is gross, but
- * sometimes at this level it is the only way out.
- */
- done_cache_as_ram_main();
-}
diff --git a/src/mainboard/pcengines/alix6/Kconfig b/src/mainboard/pcengines/alix6/Kconfig
deleted file mode 100644
index 41b9cf4..0000000
--- a/src/mainboard/pcengines/alix6/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if BOARD_PCENGINES_ALIX6
-
-# Dummy for abuild
-
-config MAINBOARD_PART_NUMBER
- string
- default "ALIX.6"
-
-endif
diff --git a/src/mainboard/pcengines/alix6/board_info.txt b/src/mainboard/pcengines/alix6/board_info.txt
deleted file mode 100644
index db8bbb2..0000000
--- a/src/mainboard/pcengines/alix6/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: half
-Board URL: http://pcengines.ch/alix6f2.htm
-Flashrom support: y
-Clone of: pcengines/alix2d
-
diff --git a/src/mainboard/sun/Kconfig b/src/mainboard/sun/Kconfig
new file mode 100644
index 0000000..6356717
--- /dev/null
+++ b/src/mainboard/sun/Kconfig
@@ -0,0 +1,17 @@
+if VENDOR_SUN
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_SUN_ULTRA40
+ bool "Ultra 40"
+
+endchoice
+
+source "src/mainboard/sun/ultra40/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Sun"
+
+endif # VENDOR_SUN
diff --git a/src/mainboard/sun/ultra40/Kconfig b/src/mainboard/sun/ultra40/Kconfig
new file mode 100644
index 0000000..5d390d7
--- /dev/null
+++ b/src/mainboard/sun/ultra40/Kconfig
@@ -0,0 +1,66 @@
+if BOARD_SUN_ULTRA40
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_SOCKET_940
+ select NORTHBRIDGE_AMD_AMDK8
+ select SOUTHBRIDGE_NVIDIA_CK804
+ select SUPERIO_SMSC_LPC47M10X
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select BOARD_ROMSIZE_KB_1024
+ select CK804_USE_NIC
+ select CK804_USE_ACI
+ select QRANK_DIMM_SUPPORT
+ select K8_ALLOCATE_IO_RANGE
+
+config MAINBOARD_DIR
+ string
+ default sun/ultra40
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xcf000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x01000
+
+config APIC_ID_OFFSET
+ hex
+ default 0x10
+
+config CK804_NUM
+ int
+ default 2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Ultra 40"
+
+config MAX_CPUS
+ int
+ default 4
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 2
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x20
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+endif # BOARD_SUN_ULTRA40
diff --git a/src/mainboard/sun/ultra40/board_info.txt b/src/mainboard/sun/ultra40/board_info.txt
new file mode 100644
index 0000000..76b41dc
--- /dev/null
+++ b/src/mainboard/sun/ultra40/board_info.txt
@@ -0,0 +1,2 @@
+Category: desktop
+Board URL: http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html
diff --git a/src/mainboard/sun/ultra40/cmos.layout b/src/mainboard/sun/ultra40/cmos.layout
new file mode 100644
index 0000000..d8e2eee
--- /dev/null
+++ b/src/mainboard/sun/ultra40/cmos.layout
@@ -0,0 +1,96 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 DDR400
+8 1 DDR333
+8 2 DDR266
+8 3 DDR200
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/sun/ultra40/devicetree.cb b/src/mainboard/sun/ultra40/devicetree.cb
new file mode 100644
index 0000000..9f9bb67
--- /dev/null
+++ b/src/mainboard/sun/ultra40/devicetree.cb
@@ -0,0 +1,151 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device cpu_cluster 0 on # (L)APIC cluster
+ chip cpu/amd/socket_940 # CPU socket
+ device lapic 0 on end # Local APIC of the CPU
+ end
+ end
+ device domain 0 on # PCI domain
+ subsystemid 0x108e 0x0040 inherit
+ chip northbridge/amd/amdk8 # Northbridge / RAM controller
+ device pci 18.0 on end
+ device pci 18.0 on # Link 0 == LDT 0
+ chip southbridge/nvidia/ck804 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/smsc/lpc47m10x # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 off # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 off # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic # DIMM 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic # DIMM 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic # DIMM 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic # DIMM 1-1-1
+ device i2c 57 on end
+ end
+ end
+ device pci 1.1 on # SM 1
+ # PCI device SMBus address will
+ # depend on addon PCI device, do
+ # we need to scan_smbus_bus?
+ # chip drivers/generic/generic # PCIXA slot 1
+ # device i2c 50 on end
+ # end
+ # chip drivers/generic/generic # PCIXB slot 1
+ # device i2c 51 on end
+ # end
+ # chip drivers/generic/generic # PCIXB slot 2
+ # device i2c 52 on end
+ # end
+ # chip drivers/generic/generic # PCI slot 1
+ # device i2c 53 on end
+ # end
+ # chip drivers/generic/generic # Master CK804 PCI-E
+ # device i2c 54 on end
+ # end
+ # chip drivers/generic/generic # Slave CK804 PCI-E
+ # device i2c 55 on end
+ # end
+ chip drivers/generic/generic # MAC EEPROM
+ device i2c 51 on end
+ end
+ end
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 off end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ # 1: SMBus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_smbus" = "3"
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end
+ device pci 18.0 on end # Link 2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ chip northbridge/amd/amdk8 # Northbridge / RAM controller
+ device pci 19.0 on end # Link 0
+ device pci 19.0 on # Link 1 == LDT 1
+ chip southbridge/nvidia/ck804 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on end # LPC
+ device pci 1.1 off end # SM
+ device pci 2.0 off end # USB 1.1
+ device pci 2.1 off end # USB 2
+ device pci 4.0 off end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 off end # IDE
+ device pci 7.0 off end # SATA 1
+ device pci 8.0 off end # SATA 0
+ device pci 9.0 off end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 off end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ # 1: SMBus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_smbus" = "3"
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+end
diff --git a/src/mainboard/sun/ultra40/get_bus_conf.c b/src/mainboard/sun/ultra40/get_bus_conf.c
new file mode 100644
index 0000000..f57719a
--- /dev/null
+++ b/src/mainboard/sun/ultra40/get_bus_conf.c
@@ -0,0 +1,279 @@
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS
+#include <cpu/amd/multicore.h>
+#endif
+#include <stdlib.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+//busnum is default
+unsigned char bus_ck804_0; //1
+unsigned char bus_ck804_1; //2
+unsigned char bus_ck804_2; //3
+unsigned char bus_ck804_3; //4
+unsigned char bus_ck804_4; //5
+unsigned char bus_ck804_5; //6
+unsigned char bus_8131_0; //7
+unsigned char bus_8131_1; //8
+unsigned char bus_8131_2; //9
+unsigned char bus_ck804b_0; //a
+unsigned char bus_ck804b_1; //b
+unsigned char bus_ck804b_2; //c
+unsigned char bus_ck804b_3; //d
+unsigned char bus_ck804b_4; //e
+unsigned char bus_ck804b_5; //f
+unsigned apicid_ck804;
+unsigned apicid_8131_1;
+unsigned apicid_8131_2;
+unsigned apicid_ck804b;
+
+unsigned sblk;
+unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ 0x0000ff0,
+ 0x0000ff0,
+ 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0
+};
+
+unsigned hc_possible_num;
+unsigned sbdn;
+unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+ 0x20202020,
+ 0x20202020,
+ 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+};
+
+unsigned sbdn3;
+unsigned sbdnb;
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+
+ unsigned apicid_base;
+
+ device_t dev;
+
+ if (get_bus_conf_done == 1)
+ return; //do it only once
+
+ get_bus_conf_done = 1;
+
+ hc_possible_num = ARRAY_SIZE(pci1234);
+
+ get_sblk_pci1234();
+
+ sbdn = (hcdn[0] & 0xff); // first byte of first chain
+
+ sbdn3 = (hcdn[1] & 0xff);
+
+ sbdnb = (hcdn[2] & 0xff); // first byte of second chain
+
+// bus_ck804_0 = node_link_to_bus(0, sblk);
+ bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
+
+ /* CK804 */
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0));
+ if (dev) {
+ bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if 0
+ bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804_2++;
+#else
+ bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804_5++;
+#endif
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",
+ sbdn + 0x09);
+
+ bus_ck804_1 = 2;
+#if 0
+ bus_ck804_2 = 3;
+#else
+ bus_ck804_5 = 3;
+#endif
+
+ }
+#if 0
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b, 0));
+ if (dev) {
+ bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804_3++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",
+ sbdn + 0x0b);
+
+ bus_ck804_3 = bus_ck804_2 + 1;
+ }
+
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c, 0));
+ if (dev) {
+ bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804_4++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",
+ sbdn + 0x0c);
+
+ bus_ck804_4 = bus_ck804_3 + 1;
+ }
+
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0));
+ if (dev) {
+ bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804_5++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",
+ sbdn + 0x0d);
+
+ bus_ck804_5 = bus_ck804_4 + 1;
+ }
+#endif
+
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0));
+ if (dev) {
+ bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",
+ sbdn + 0x0e);
+ }
+
+ bus_8131_0 = (pci1234[1] >> 16) & 0xff;
+ /* 8131-1 */
+ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0));
+ if (dev) {
+ bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_8131_2++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI %02x:01.0, using defaults\n",
+ bus_8131_0);
+
+ bus_8131_1 = bus_8131_0 + 1;
+ bus_8131_2 = bus_8131_0 + 2;
+ }
+ /* 8131-2 */
+ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0));
+ if (dev) {
+ bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI %02x:02.0, using defaults\n",
+ bus_8131_0);
+
+ bus_8131_2 = bus_8131_1 + 1;
+ }
+
+ /* CK804b */
+
+ if (pci1234[2] & 0xf) { //if the second cpu is installed
+ bus_ck804b_0 = (pci1234[2] >> 16) & 0xff;
+#if 0
+ dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09, 0));
+ if (dev) {
+ bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804b_2 =
+ pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804b_2++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
+ bus_ck804b_0, sbdnb + 0x09);
+
+ bus_ck804b_1 = bus_ck804b_0 + 1;
+ bus_ck804b_2 = bus_ck804b_0 + 2;
+ }
+
+ dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b, 0));
+ if (dev) {
+ bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804b_3 =
+ pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804b_3++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
+ bus_ck804b_0, sbdnb + 0x0b);
+
+ bus_ck804b_2 = bus_ck804b_0 + 1;
+ bus_ck804b_3 = bus_ck804b_0 + 2;
+ }
+
+ dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c, 0));
+ if (dev) {
+ bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804b_4 =
+ pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804b_4++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
+ bus_ck804b_0, sbdnb + 0x0c);
+
+ bus_ck804b_4 = bus_ck804b_3 + 1;
+ }
+ dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d, 0));
+ if (dev) {
+ bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804b_5 =
+ pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804b_5++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
+ bus_ck804b_0, sbdnb + 0x0d);
+
+ bus_ck804b_5 = bus_ck804b_4 + 1;
+ }
+#endif
+
+ dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e, 0));
+ if (dev) {
+ bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
+ bus_ck804b_0, sbdnb + 0x0e);
+#if 1
+ bus_ck804b_5 = bus_ck804b_4 + 1;
+#endif
+
+ }
+ }
+
+/*I/O APICs: APIC ID Version State Address*/
+#if CONFIG_LOGICAL_CPUS
+ apicid_base = get_apicid_base(4);
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+ apicid_ck804 = apicid_base + 0;
+ apicid_8131_1 = apicid_base + 1;
+ apicid_8131_2 = apicid_base + 2;
+ apicid_ck804b = apicid_base + 3;
+
+}
diff --git a/src/mainboard/sun/ultra40/irq_tables.c b/src/mainboard/sun/ultra40/irq_tables.c
new file mode 100644
index 0000000..a0e21e4
--- /dev/null
+++ b/src/mainboard/sun/ultra40/irq_tables.c
@@ -0,0 +1,181 @@
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+ Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+ uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+ uint8_t slot, uint8_t rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+extern unsigned char bus_ck804_0; //1
+extern unsigned char bus_ck804_1; //2
+extern unsigned char bus_ck804_2; //3
+extern unsigned char bus_ck804_3; //4
+extern unsigned char bus_ck804_4; //5
+extern unsigned char bus_ck804_5; //6
+extern unsigned char bus_8131_0; //7
+extern unsigned char bus_8131_1; //8
+extern unsigned char bus_8131_2; //9
+extern unsigned char bus_ck804b_0;//a
+extern unsigned char bus_ck804b_1;//b
+extern unsigned char bus_ck804b_2;//c
+extern unsigned char bus_ck804b_3;//d
+extern unsigned char bus_ck804b_4;//e
+extern unsigned char bus_ck804b_5;//f
+
+extern unsigned pci1234[];
+
+extern unsigned sbdn;
+extern unsigned hcdn[];
+extern unsigned sbdn3;
+extern unsigned sbdnb;
+
+
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ unsigned slot_num;
+ uint8_t *v;
+
+ uint8_t sum=0;
+ int i;
+
+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (uint8_t *)(addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_ck804_0;
+ pirq->rtr_devfn = ((sbdn+9)<<3)|0;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x10de;
+ pirq->rtr_device = 0x005c;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *) ( &pirq->checksum + 1);
+ slot_num = 0;
+//pci bridge
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+//pcix bridge
+ write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+
+ if(pci1234[2] & 0xf) {
+ //second pci beidge
+ write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
+ pirq_info++; slot_num++;
+ }
+#if 0
+//smbus
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//usb
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//audio
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+//sata
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+//sata
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+//nic
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//Slot1 PCIE x16
+ write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
+ pirq_info++; slot_num++;
+
+//firewire
+ write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//Slot2 pci
+ write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
+ pirq_info++; slot_num++;
+//nic
+ write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+//Slot3 PCIE x16
+ write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
+ pirq_info++; slot_num++;
+
+//Slot4 PCIX
+ write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
+ pirq_info++; slot_num++;
+
+//Slot5 PCIX
+ write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
+ pirq_info++; slot_num++;
+
+//onboard scsi
+ write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//Slot6 PCIX
+ write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
+ pirq_info++; slot_num++;
+#endif
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "done.\n");
+
+ return (unsigned long) pirq_info;
+
+}
diff --git a/src/mainboard/sun/ultra40/mptable.c b/src/mainboard/sun/ultra40/mptable.c
new file mode 100644
index 0000000..1ba1dcf
--- /dev/null
+++ b/src/mainboard/sun/ultra40/mptable.c
@@ -0,0 +1,197 @@
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+extern unsigned char bus_ck804_0; //1
+extern unsigned char bus_ck804_1; //2
+extern unsigned char bus_ck804_2; //3
+extern unsigned char bus_ck804_3; //4
+extern unsigned char bus_ck804_4; //5
+extern unsigned char bus_ck804_5; //6
+extern unsigned char bus_8131_0; //7
+extern unsigned char bus_8131_1; //8
+extern unsigned char bus_8131_2; //9
+extern unsigned char bus_ck804b_0;//a
+extern unsigned char bus_ck804b_1;//b
+extern unsigned char bus_ck804b_2;//c
+extern unsigned char bus_ck804b_3;//d
+extern unsigned char bus_ck804b_4;//e
+extern unsigned char bus_ck804b_5;//f
+extern unsigned apicid_ck804;
+extern unsigned apicid_8131_1;
+extern unsigned apicid_8131_2;
+extern unsigned apicid_ck804b;
+
+extern unsigned pci1234[];
+
+extern unsigned sbdn;
+extern unsigned hcdn[];
+extern unsigned sbdn3;
+extern unsigned sbdnb;
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int i, bus_isa;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+/*I/O APICs: APIC ID Version State Address*/
+ {
+ device_t dev;
+ struct resource *res;
+ uint32_t dword;
+
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_1);
+ if (res) {
+ smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ }
+
+ /* Initialize interrupt mapping*/
+
+ dword = 0x0120d218;
+ pci_write_config32(dev, 0x7c, dword);
+
+ dword = 0x12008a00;
+ pci_write_config32(dev, 0x80, dword);
+
+ dword = 0x00080d7d;
+ pci_write_config32(dev, 0x84, dword);
+
+ }
+
+ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ }
+ }
+ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ }
+ }
+
+ if(pci1234[2] & 0xf) {
+ dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_1);
+ if (res) {
+ smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
+ }
+
+ dword = 0x0000d218;
+ pci_write_config32(dev, 0x7c, dword);
+
+ dword = 0x00000000;
+ pci_write_config32(dev, 0x80, dword);
+
+ dword = 0x00000d00;
+ pci_write_config32(dev, 0x84, dword);
+
+ }
+ }
+
+ }
+
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
+
+// Onboard ck804 smbus
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
+// 10
+
+// Onboard ck804 USB 1.1
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
+
+// Onboard ck804 USB 2
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
+
+// Onboard ck804 Audio
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
+
+// Onboard ck804 SATA 0
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
+
+// Onboard ck804 SATA 1
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
+
+// Onboard ck804 NIC
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
+
+//Slot 1 PCIE x16
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
+ }
+
+//Onboard Firewire
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
+
+//Slot 2 PCI 32
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
+ }
+
+ if(pci1234[2] & 0xf) {
+//Onboard ck804b NIC
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
+
+//Slot 3 PCIE x16
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
+ }
+ }
+
+//Channel B of 8131
+
+//Slot 4 PCI-X 100/66
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
+ }
+
+//Slot 5 PCIX 100/66
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
+ }
+
+//OnBoard LSI SCSI
+ for(i=0;i<2;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
+ }
+
+//Channel A of 8131
+
+//Slot 6 PCIX 133/100/66
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
+ }
+
+/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ mptable_lintsrc(mc, bus_isa);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/sun/ultra40/resourcemap.c b/src/mainboard/sun/ultra40/resourcemap.c
new file mode 100644
index 0000000..964be50
--- /dev/null
+++ b/src/mainboard/sun/ultra40/resourcemap.c
@@ -0,0 +1,265 @@
+/*
+ * needs a different resource map
+ *
+ */
+
+static void setup_ultra40_resource_map(void)
+{
+ static const unsigned int register_values[] = {
+ /* Careful set limit registers before base registers which contain the enables */
+ /* DRAM Limit i Registers
+ * F1:0x44 i = 0
+ * F1:0x4C i = 1
+ * F1:0x54 i = 2
+ * F1:0x5C i = 3
+ * F1:0x64 i = 4
+ * F1:0x6C i = 5
+ * F1:0x74 i = 6
+ * F1:0x7C i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 3] Reserved
+ * [10: 8] Interleave select
+ * specifies the values of A[14:12] to use with interleave enable.
+ * [15:11] Reserved
+ * [31:16] DRAM Limit Address i Bits 39-24
+ * This field defines the upper address bits of a 40 bit address
+ * that define the end of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+ PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+ PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+ PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+ PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+ PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+ PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+
+ /* DRAM Base i Registers
+ * F1:0x40 i = 0
+ * F1:0x48 i = 1
+ * F1:0x50 i = 2
+ * F1:0x58 i = 3
+ * F1:0x60 i = 4
+ * F1:0x68 i = 5
+ * F1:0x70 i = 6
+ * F1:0x78 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 7: 2] Reserved
+ * [10: 8] Interleave Enable
+ * 000 = No interleave
+ * 001 = Interleave on A[12] (2 nodes)
+ * 010 = reserved
+ * 011 = Interleave on A[12] and A[14] (4 nodes)
+ * 100 = reserved
+ * 101 = reserved
+ * 110 = reserved
+ * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+ * [15:11] Reserved
+ * [13:16] DRAM Base Address i Bits 39-24
+ * This field defines the upper address bits of a 40-bit address
+ * that define the start of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+ /* Memory-Mapped I/O Limit i Registers
+ * F1:0x84 i = 0
+ * F1:0x8C i = 1
+ * F1:0x94 i = 2
+ * F1:0x9C i = 3
+ * F1:0xA4 i = 4
+ * F1:0xAC i = 5
+ * F1:0xB4 i = 6
+ * F1:0xBC i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = Reserved
+ * [ 6: 6] Reserved
+ * [ 7: 7] Non-Posted
+ * 0 = CPU writes may be posted
+ * 1 = CPU writes must be non-posted
+ * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+ * This field defines the upp adddress bits of a 40-bit address that
+ * defines the end of a memory-mapped I/O region n
+ */
+ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+ /* Memory-Mapped I/O Base i Registers
+ * F1:0x80 i = 0
+ * F1:0x88 i = 1
+ * F1:0x90 i = 2
+ * F1:0x98 i = 3
+ * F1:0xA0 i = 4
+ * F1:0xA8 i = 5
+ * F1:0xB0 i = 6
+ * F1:0xB8 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Cpu Disable
+ * 0 = Cpu can use this I/O range
+ * 1 = Cpu requests do not use this I/O range
+ * [ 3: 3] Lock
+ * 0 = base/limit registers i are read/write
+ * 1 = base/limit registers i are read-only
+ * [ 7: 4] Reserved
+ * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+ * This field defines the upper address bits of a 40bit address
+ * that defines the start of memory-mapped I/O region i
+ */
+ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+ /* PCI I/O Limit i Registers
+ * F1:0xC4 i = 0
+ * F1:0xCC i = 1
+ * F1:0xD4 i = 2
+ * F1:0xDC i = 3
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = reserved
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Limit Address i
+ * This field defines the end of PCI I/O region n
+ * [31:25] Reserved
+ */
+ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
+ PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+ /* PCI I/O Base i Registers
+ * F1:0xC0 i = 0
+ * F1:0xC8 i = 1
+ * F1:0xD0 i = 2
+ * F1:0xD8 i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 3: 2] Reserved
+ * [ 4: 4] VGA Enable
+ * 0 = VGA matches Disabled
+ * 1 = matches all address < 64K and where A[9:0] is in the
+ * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+ * [ 5: 5] ISA Enable
+ * 0 = ISA matches Disabled
+ * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+ * from matching agains this base/limit pair
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Base i
+ * This field defines the start of PCI I/O region n
+ * [31:25] Reserved
+ */
+ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+ PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
+ PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+ /* Config Base and Limit i Registers
+ * F1:0xE0 i = 0
+ * F1:0xE4 i = 1
+ * F1:0xE8 i = 2
+ * F1:0xEC i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Device Number Compare Enable
+ * 0 = The ranges are based on bus number
+ * 1 = The ranges are ranges of devices on bus 0
+ * [ 3: 3] Reserved
+ * [ 6: 4] Destination Node
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 7] Reserved
+ * [ 9: 8] Destination Link
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 - Reserved
+ * [15:10] Reserved
+ * [23:16] Bus Number Base i
+ * This field defines the lowest bus number in configuration region i
+ * [31:24] Bus Number Limit i
+ * This field defines the highest bus number in configuration region i
+ */
+ PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103,
+ PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113,
+ PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xec), 0x0000, 0x00000000,
+ };
+
+ int max;
+ max = ARRAY_SIZE(register_values);
+ setup_resource_map(register_values, max);
+}
diff --git a/src/mainboard/sun/ultra40/romstage.c b/src/mainboard/sun/ultra40/romstage.c
new file mode 100644
index 0000000..7c112da
--- /dev/null
+++ b/src/mainboard/sun/ultra40/romstage.c
@@ -0,0 +1,152 @@
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <lib.h>
+#include <spd.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/nvidia/ck804/early_smbus.h"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "lib/delay.c"
+#include "cpu/x86/lapic.h"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/smsc/lpc47b397/early_serial.c"
+#include "cpu/x86/bist.h"
+#include "superio/smsc/lpc47b397/early_gpio.c"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
+#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
+#define SUPERIO_GPIO_IO_BASE 0x400
+
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+
+#ifdef ENABLE_ONBOARD_SCSI
+static void sio_gpio_setup(void)
+{
+ unsigned value;
+
+ /*Enable onboard scsi*/
+ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
+ value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
+ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
+}
+#endif
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl) { }
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "lib/generic_sdram.c"
+#include "resourcemap.c"
+#include "cpu/amd/dualcore/dualcore.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+
+//set GPIO to input mode
+#define CK804_MB_SETUP \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
+
+#include "southbridge/nvidia/ck804/early_setup_car.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+static void sio_setup(void)
+{
+ unsigned value;
+ uint32_t dword;
+ uint8_t byte;
+
+ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
+
+ byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
+ byte |= 0x20;
+ pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
+
+ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
+ dword |= (1<<29)|(1<<0);
+ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+
+ lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
+
+ value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
+ value &= 0xbf;
+ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const uint16_t spd_addr [] = {
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
+ };
+
+ int needs_reset;
+ unsigned bsp_apicid = 0, nodes;
+ struct mem_controller ctrl[8];
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ enumerate_ht_chain();
+ sio_setup();
+ }
+
+ if (bist == 0)
+ bsp_apicid = init_cpus(cpu_init_detectedx);
+
+ lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ setup_ultra40_resource_map();
+
+ needs_reset = setup_coherent_ht_domain();
+
+ wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS
+ // It is said that we should start core1 after all core0 launched
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
+#endif
+
+ needs_reset |= ht_setup_chains_x();
+ needs_reset |= ck804_early_setup_x();
+ if (needs_reset) {
+ print_info("ht reset -\n");
+ soft_reset();
+ }
+
+ allow_all_aps_stop(bsp_apicid);
+
+ nodes = get_nodes();
+ //It's the time to set ctrl now;
+ fill_mem_ctrl(nodes, ctrl, spd_addr);
+
+ enable_smbus();
+
+ sdram_initialize(nodes, ctrl);
+
+ post_cache_as_ram();
+}
diff --git a/src/mainboard/sunw/Kconfig b/src/mainboard/sunw/Kconfig
deleted file mode 100644
index 0ee7f2e..0000000
--- a/src/mainboard/sunw/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if VENDOR_SUNW
-
-choice
- prompt "Mainboard model"
-
-config BOARD_SUNW_ULTRA40
- bool "Ultra 40"
-
-endchoice
-
-source "src/mainboard/sunw/ultra40/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Sun"
-
-endif # VENDOR_SUNW
diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig
deleted file mode 100644
index 3fb5591..0000000
--- a/src/mainboard/sunw/ultra40/Kconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-if BOARD_SUNW_ULTRA40
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select SUPERIO_SMSC_LPC47M10X
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_1024
- select CK804_USE_NIC
- select CK804_USE_ACI
- select QRANK_DIMM_SUPPORT
- select K8_ALLOCATE_IO_RANGE
-
-config MAINBOARD_DIR
- string
- default sunw/ultra40
-
-config DCACHE_RAM_BASE
- hex
- default 0xcf000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x01000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config CK804_NUM
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "Ultra 40"
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config SB_HT_CHAIN_ON_BUS0
- int
- default 2
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_SUNW_ULTRA40
diff --git a/src/mainboard/sunw/ultra40/board_info.txt b/src/mainboard/sunw/ultra40/board_info.txt
deleted file mode 100644
index 76b41dc..0000000
--- a/src/mainboard/sunw/ultra40/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: desktop
-Board URL: http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html
diff --git a/src/mainboard/sunw/ultra40/cmos.layout b/src/mainboard/sunw/ultra40/cmos.layout
deleted file mode 100644
index d8e2eee..0000000
--- a/src/mainboard/sunw/ultra40/cmos.layout
+++ /dev/null
@@ -1,96 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb
deleted file mode 100644
index 9f9bb67..0000000
--- a/src/mainboard/sunw/ultra40/devicetree.cb
+++ /dev/null
@@ -1,151 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_940 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x108e 0x0040 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on end
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/smsc/lpc47m10x # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 off # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 1-1-1
- device i2c 57 on end
- end
- end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master CK804 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave CK804 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on end # PCI
- device pci a.0 on end # NIC
- device pci b.0 off end # PCI E 3
- device pci c.0 off end # PCI E 2
- device pci d.0 off end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.0 on end # Link 2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 19.0 on end # Link 0
- device pci 19.0 on # Link 1 == LDT 1
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on end # LPC
- device pci 1.1 off end # SM
- device pci 2.0 off end # USB 1.1
- device pci 2.1 off end # USB 2
- device pci 4.0 off end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 off end # IDE
- device pci 7.0 off end # SATA 1
- device pci 8.0 off end # SATA 0
- device pci 9.0 off end # PCI
- device pci a.0 on end # NIC
- device pci b.0 off end # PCI E 3
- device pci c.0 off end # PCI E 2
- device pci d.0 off end # PCI E 1
- device pci e.0 on end # PCI E 0
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- end
- end
-end
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
deleted file mode 100644
index f57719a..0000000
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ /dev/null
@@ -1,279 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS
-#include <cpu/amd/multicore.h>
-#endif
-#include <stdlib.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_ck804_0; //1
-unsigned char bus_ck804_1; //2
-unsigned char bus_ck804_2; //3
-unsigned char bus_ck804_3; //4
-unsigned char bus_ck804_4; //5
-unsigned char bus_ck804_5; //6
-unsigned char bus_8131_0; //7
-unsigned char bus_8131_1; //8
-unsigned char bus_8131_2; //9
-unsigned char bus_ck804b_0; //a
-unsigned char bus_ck804b_1; //b
-unsigned char bus_ck804b_2; //c
-unsigned char bus_ck804b_3; //d
-unsigned char bus_ck804b_4; //e
-unsigned char bus_ck804b_5; //f
-unsigned apicid_ck804;
-unsigned apicid_8131_1;
-unsigned apicid_8131_2;
-unsigned apicid_ck804b;
-
-unsigned sblk;
-unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0,
- 0x0000ff0,
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hc_possible_num;
-unsigned sbdn;
-unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-unsigned sbdn3;
-unsigned sbdnb;
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- device_t dev;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- hc_possible_num = ARRAY_SIZE(pci1234);
-
- get_sblk_pci1234();
-
- sbdn = (hcdn[0] & 0xff); // first byte of first chain
-
- sbdn3 = (hcdn[1] & 0xff);
-
- sbdnb = (hcdn[2] & 0xff); // first byte of second chain
-
-// bus_ck804_0 = node_link_to_bus(0, sblk);
- bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if 0
- bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_2++;
-#else
- bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_5++;
-#endif
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
-
- bus_ck804_1 = 2;
-#if 0
- bus_ck804_2 = 3;
-#else
- bus_ck804_5 = 3;
-#endif
-
- }
-#if 0
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b, 0));
- if (dev) {
- bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_3++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0b);
-
- bus_ck804_3 = bus_ck804_2 + 1;
- }
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c, 0));
- if (dev) {
- bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_4++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0c);
-
- bus_ck804_4 = bus_ck804_3 + 1;
- }
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0));
- if (dev) {
- bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_5++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0d);
-
- bus_ck804_5 = bus_ck804_4 + 1;
- }
-#endif
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0));
- if (dev) {
- bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0e);
- }
-
- bus_8131_0 = (pci1234[1] >> 16) & 0xff;
- /* 8131-1 */
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0));
- if (dev) {
- bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_8131_2++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:01.0, using defaults\n",
- bus_8131_0);
-
- bus_8131_1 = bus_8131_0 + 1;
- bus_8131_2 = bus_8131_0 + 2;
- }
- /* 8131-2 */
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0));
- if (dev) {
- bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:02.0, using defaults\n",
- bus_8131_0);
-
- bus_8131_2 = bus_8131_1 + 1;
- }
-
- /* CK804b */
-
- if (pci1234[2] & 0xf) { //if the second cpu is installed
- bus_ck804b_0 = (pci1234[2] >> 16) & 0xff;
-#if 0
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09, 0));
- if (dev) {
- bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804b_2 =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804b_2++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x09);
-
- bus_ck804b_1 = bus_ck804b_0 + 1;
- bus_ck804b_2 = bus_ck804b_0 + 2;
- }
-
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b, 0));
- if (dev) {
- bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804b_3 =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804b_3++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x0b);
-
- bus_ck804b_2 = bus_ck804b_0 + 1;
- bus_ck804b_3 = bus_ck804b_0 + 2;
- }
-
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c, 0));
- if (dev) {
- bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804b_4 =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804b_4++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x0c);
-
- bus_ck804b_4 = bus_ck804b_3 + 1;
- }
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d, 0));
- if (dev) {
- bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804b_5 =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804b_5++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x0d);
-
- bus_ck804b_5 = bus_ck804b_4 + 1;
- }
-#endif
-
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e, 0));
- if (dev) {
- bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804b_0, sbdnb + 0x0e);
-#if 1
- bus_ck804b_5 = bus_ck804b_4 + 1;
-#endif
-
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS
- apicid_base = get_apicid_base(4);
-#else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-#endif
- apicid_ck804 = apicid_base + 0;
- apicid_8131_1 = apicid_base + 1;
- apicid_8131_2 = apicid_base + 2;
- apicid_ck804b = apicid_base + 3;
-
-}
diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c
deleted file mode 100644
index a0e21e4..0000000
--- a/src/mainboard/sunw/ultra40/irq_tables.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-
- Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_ck804_0; //1
-extern unsigned char bus_ck804_1; //2
-extern unsigned char bus_ck804_2; //3
-extern unsigned char bus_ck804_3; //4
-extern unsigned char bus_ck804_4; //5
-extern unsigned char bus_ck804_5; //6
-extern unsigned char bus_8131_0; //7
-extern unsigned char bus_8131_1; //8
-extern unsigned char bus_8131_2; //9
-extern unsigned char bus_ck804b_0;//a
-extern unsigned char bus_ck804b_1;//b
-extern unsigned char bus_ck804b_2;//c
-extern unsigned char bus_ck804b_3;//d
-extern unsigned char bus_ck804b_4;//e
-extern unsigned char bus_ck804b_5;//f
-
-extern unsigned pci1234[];
-
-extern unsigned sbdn;
-extern unsigned hcdn[];
-extern unsigned sbdn3;
-extern unsigned sbdnb;
-
-
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum=0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_ck804_0;
- pirq->rtr_devfn = ((sbdn+9)<<3)|0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *) ( &pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
-//pcix bridge
- write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
-
- if(pci1234[2] & 0xf) {
- //second pci beidge
- write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
- pirq_info++; slot_num++;
- }
-#if 0
-//smbus
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//usb
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//audio
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-//nic
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//Slot1 PCIE x16
- write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
- pirq_info++; slot_num++;
-
-//firewire
- write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//Slot2 pci
- write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
- pirq_info++; slot_num++;
-//nic
- write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-//Slot3 PCIE x16
- write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
- pirq_info++; slot_num++;
-
-//Slot4 PCIX
- write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
- pirq_info++; slot_num++;
-
-//Slot5 PCIX
- write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
- pirq_info++; slot_num++;
-
-//onboard scsi
- write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//Slot6 PCIX
- write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
- pirq_info++; slot_num++;
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long) pirq_info;
-
-}
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
deleted file mode 100644
index 1ba1dcf..0000000
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ /dev/null
@@ -1,197 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804_0; //1
-extern unsigned char bus_ck804_1; //2
-extern unsigned char bus_ck804_2; //3
-extern unsigned char bus_ck804_3; //4
-extern unsigned char bus_ck804_4; //5
-extern unsigned char bus_ck804_5; //6
-extern unsigned char bus_8131_0; //7
-extern unsigned char bus_8131_1; //8
-extern unsigned char bus_8131_2; //9
-extern unsigned char bus_ck804b_0;//a
-extern unsigned char bus_ck804b_1;//b
-extern unsigned char bus_ck804b_2;//c
-extern unsigned char bus_ck804b_3;//d
-extern unsigned char bus_ck804b_4;//e
-extern unsigned char bus_ck804b_5;//f
-extern unsigned apicid_ck804;
-extern unsigned apicid_8131_1;
-extern unsigned apicid_8131_2;
-extern unsigned apicid_ck804b;
-
-extern unsigned pci1234[];
-
-extern unsigned sbdn;
-extern unsigned hcdn[];
-extern unsigned sbdn3;
-extern unsigned sbdnb;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int i, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- device_t dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
- }
-
- /* Initialize interrupt mapping*/
-
- dword = 0x0120d218;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x12008a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x00080d7d;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
- }
- }
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
- }
- }
-
- if(pci1234[2] & 0xf) {
- dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
- }
-
- dword = 0x0000d218;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x00000000;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x00000d00;
- pci_write_config32(dev, 0x84, dword);
-
- }
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
-
-// Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
-// 10
-
-// Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
-
-// Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
-
-// Onboard ck804 Audio
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
-
-// Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
-
-// Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
-
-// Onboard ck804 NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
-
-//Slot 1 PCIE x16
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
- }
-
-//Onboard Firewire
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
-
-//Slot 2 PCI 32
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
- }
-
- if(pci1234[2] & 0xf) {
-//Onboard ck804b NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
-
-//Slot 3 PCIE x16
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
- }
- }
-
-//Channel B of 8131
-
-//Slot 4 PCI-X 100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
- }
-
-//Slot 5 PCIX 100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
- }
-
-//OnBoard LSI SCSI
- for(i=0;i<2;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
- }
-
-//Channel A of 8131
-
-//Slot 6 PCIX 133/100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/sunw/ultra40/resourcemap.c b/src/mainboard/sunw/ultra40/resourcemap.c
deleted file mode 100644
index 964be50..0000000
--- a/src/mainboard/sunw/ultra40/resourcemap.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * needs a different resource map
- *
- */
-
-static void setup_ultra40_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103,
- PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113,
- PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xec), 0x0000, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
deleted file mode 100644
index 7c112da..0000000
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ /dev/null
@@ -1,152 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/early_smbus.h"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "lib/delay.c"
-#include "cpu/x86/lapic.h"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "superio/smsc/lpc47b397/early_serial.c"
-#include "cpu/x86/bist.h"
-#include "superio/smsc/lpc47b397/early_gpio.c"
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-#ifdef ENABLE_ONBOARD_SCSI
-static void sio_gpio_setup(void)
-{
- unsigned value;
-
- /*Enable onboard scsi*/
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
- value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-}
-#endif
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/early_setup_ss.h"
-
-//set GPIO to input mode
-#define CK804_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-
-#include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- unsigned value;
- uint32_t dword;
- uint8_t byte;
-
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
-
- byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<29)|(1<<0);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
- lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
-
- value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
- value &= 0xbf;
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- int needs_reset;
- unsigned bsp_apicid = 0, nodes;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
- lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_ultra40_resource_map();
-
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- print_info("ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-
- sdram_initialize(nodes, ctrl);
-
- post_cache_as_ram();
-}
diff --git a/src/mainboard/traverse/Kconfig b/src/mainboard/traverse/Kconfig
deleted file mode 100644
index bb75535..0000000
--- a/src/mainboard/traverse/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if VENDOR_TRAVERSE
-
-choice
- prompt "Mainboard model"
-
-config BOARD_TRAVERSE_GEOS
- bool "Geos"
-
-endchoice
-
-source "src/mainboard/traverse/geos/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Traverse Technologies"
-
-endif # VENDOR_TRAVERSE
diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
deleted file mode 100644
index 945ab09..0000000
--- a/src/mainboard/traverse/geos/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-if BOARD_TRAVERSE_GEOS
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_GEODE_LX
- select NORTHBRIDGE_AMD_LX
- select SOUTHBRIDGE_AMD_CS5536
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_1024
- select POWER_BUTTON_DEFAULT_DISABLE
- select PLL_MANUAL_CONFIG
- select CORE_GLIU_500_400
-
-config MAINBOARD_DIR
- string
- default traverse/geos
-
-config MAINBOARD_PART_NUMBER
- string
- default "Geos"
-
-config IRQ_SLOT_COUNT
- int
- default 6
-
-config PLLMSRlo
- hex
- default 0x00de602e
-
-endif # BOARD_TRAVERSE_GEOS
diff --git a/src/mainboard/traverse/geos/board_info.txt b/src/mainboard/traverse/geos/board_info.txt
deleted file mode 100644
index 394724a..0000000
--- a/src/mainboard/traverse/geos/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: half
-Board URL: http://www.traverse.com.au/geos11-adsl2-x86-router-appliance
-ROM package: PLCC
-ROM socketed: y
diff --git a/src/mainboard/traverse/geos/cmos.layout b/src/mainboard/traverse/geos/cmos.layout
deleted file mode 100644
index 9a189ce..0000000
--- a/src/mainboard/traverse/geos/cmos.layout
+++ /dev/null
@@ -1,73 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-440 1 e 0 dcon_present
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/traverse/geos/devicetree.cb b/src/mainboard/traverse/geos/devicetree.cb
deleted file mode 100644
index 4a2674e..0000000
--- a/src/mainboard/traverse/geos/devicetree.cb
+++ /dev/null
@@ -1,40 +0,0 @@
-chip northbridge/amd/lx
- device domain 0 on
- device pci 1.0 on end # Northbridge
- device pci 1.1 on end # Graphics
- chip southbridge/amd/cs5536
- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
- # SIRQ Mode = Active(Quiet) mode. Save power....
- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
- register "lpc_serirq_enable" = "0x00001002"
- register "lpc_serirq_polarity" = "0x0000EFFD"
- register "lpc_serirq_mode" = "1"
- register "enable_gpio_int_route" = "0x0D0C0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "0" #0: host, 1:device
- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "1"
- register "com1_address" = "0x3F8"
- register "com1_irq" = "4"
- register "com2_enable" = "0"
- register "com2_address" = "0x2F8"
- register "com2_irq" = "3"
- register "unwanted_vpci[0]" = "0" # End of list has a zero
- device pci a.0 on end # Ethernet 0
- device pci b.0 on end # Ethernet 1
- device pci c.0 on end # Xilinx
- device pci d.0 on end # Mini PCI
- device pci f.0 on end # ISA Bridge
- device pci f.2 on end # IDE Controller
- device pci f.3 on end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
- # APIC cluster is late CPU init.
- device cpu_cluster 0 on
- chip cpu/amd/geode_lx
- device lapic 0 on end
- end
- end
-end
diff --git a/src/mainboard/traverse/geos/irq_tables.c b/src/mainboard/traverse/geos/irq_tables.c
deleted file mode 100644
index 7431d24..0000000
--- a/src/mainboard/traverse/geos/irq_tables.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 10
-#define PIRQC 11
-#define PIRQD 9
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Miniport data */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
- {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */
- {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */
- {0x00, (0x0C << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x2, 0x0}, /* xilinx */
- {0x00, (0x0D << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* mini PCI */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/traverse/geos/mainboard.c b/src/mainboard/traverse/geos/mainboard.c
deleted file mode 100644
index ceb8cad..0000000
--- a/src/mainboard/traverse/geos/mainboard.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Geos ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "Geos EXIT %s\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
deleted file mode 100644
index b3358b5..0000000
--- a/src/mainboard/traverse/geos/romstage.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <console/console.h>
-#include <lib.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/lxdef.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-#include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
-#include "northbridge/amd/lx/raminit.h"
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- static const struct mem_controller memctrl[] = {
- {.channel0 = {DIMM0, DIMM1}}
- };
-
- SystemPreInit();
- msr_init();
-
- cs5536_early_setup();
-
- /* Note: must do this AFTER the early_setup! It is counting on some
- * early MSR setup for CS5536.
- */
- /* cs5536_disable_internal_uart: disable them for now, set them
- * up later...
- */
- /* If debug. real setup done in chipset init via devicetree.cb. */
- cs5536_setup_onchipuart(1);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pll_reset();
-
- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
- sdram_initialize(1, memctrl);
-
- /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
- return;
-}
diff --git a/src/mainboard/traverse_technologies/Kconfig b/src/mainboard/traverse_technologies/Kconfig
new file mode 100644
index 0000000..794b549
--- /dev/null
+++ b/src/mainboard/traverse_technologies/Kconfig
@@ -0,0 +1,17 @@
+if VENDOR_TRAVERSE_TECHNOLOGIES
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_TRAVERSE_TECHNOLOGIES_GEOS
+ bool "Geos"
+
+endchoice
+
+source "src/mainboard/traverse_technologies/geos/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Traverse Technologies"
+
+endif # VENDOR_TRAVERSE_TECHNOLOGIES
diff --git a/src/mainboard/traverse_technologies/geos/Kconfig b/src/mainboard/traverse_technologies/geos/Kconfig
new file mode 100644
index 0000000..cb90a53
--- /dev/null
+++ b/src/mainboard/traverse_technologies/geos/Kconfig
@@ -0,0 +1,32 @@
+if BOARD_TRAVERSE_TECHNOLOGIES_GEOS
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_GEODE_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_1024
+ select POWER_BUTTON_DEFAULT_DISABLE
+ select PLL_MANUAL_CONFIG
+ select CORE_GLIU_500_400
+
+config MAINBOARD_DIR
+ string
+ default traverse_technologies/geos
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Geos"
+
+config IRQ_SLOT_COUNT
+ int
+ default 6
+
+config PLLMSRlo
+ hex
+ default 0x00de602e
+
+endif # BOARD_TRAVERSE_TECHNOLOGIES_GEOS
diff --git a/src/mainboard/traverse_technologies/geos/board_info.txt b/src/mainboard/traverse_technologies/geos/board_info.txt
new file mode 100644
index 0000000..9381bc3
--- /dev/null
+++ b/src/mainboard/traverse_technologies/geos/board_info.txt
@@ -0,0 +1,4 @@
+Category: half
+Board URL: http://www.traverse_technologies.com.au/geos11-adsl2-x86-router-appliance
+ROM package: PLCC
+ROM socketed: y
diff --git a/src/mainboard/traverse_technologies/geos/cmos.layout b/src/mainboard/traverse_technologies/geos/cmos.layout
new file mode 100644
index 0000000..9a189ce
--- /dev/null
+++ b/src/mainboard/traverse_technologies/geos/cmos.layout
@@ -0,0 +1,73 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 1 e 0 dcon_present
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/traverse_technologies/geos/devicetree.cb b/src/mainboard/traverse_technologies/geos/devicetree.cb
new file mode 100644
index 0000000..4a2674e
--- /dev/null
+++ b/src/mainboard/traverse_technologies/geos/devicetree.cb
@@ -0,0 +1,40 @@
+chip northbridge/amd/lx
+ device domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ register "lpc_serirq_enable" = "0x00001002"
+ register "lpc_serirq_polarity" = "0x0000EFFD"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "1"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci a.0 on end # Ethernet 0
+ device pci b.0 on end # Ethernet 1
+ device pci c.0 on end # Xilinx
+ device pci d.0 on end # Mini PCI
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device cpu_cluster 0 on
+ chip cpu/amd/geode_lx
+ device lapic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/traverse_technologies/geos/irq_tables.c b/src/mainboard/traverse_technologies/geos/irq_tables.c
new file mode 100644
index 0000000..7431d24
--- /dev/null
+++ b/src/mainboard/traverse_technologies/geos/irq_tables.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 10
+#define PIRQC 11
+#define PIRQD 9
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Miniport data */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */
+ {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */
+ {0x00, (0x0C << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x2, 0x0}, /* xilinx */
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* mini PCI */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/traverse_technologies/geos/mainboard.c b/src/mainboard/traverse_technologies/geos/mainboard.c
new file mode 100644
index 0000000..ceb8cad
--- /dev/null
+++ b/src/mainboard/traverse_technologies/geos/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "Geos ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "Geos EXIT %s\n", __func__);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/traverse_technologies/geos/romstage.c b/src/mainboard/traverse_technologies/geos/romstage.c
new file mode 100644
index 0000000..b3358b5
--- /dev/null
+++ b/src/mainboard/traverse_technologies/geos/romstage.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <lib.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include "northbridge/amd/lx/raminit.h"
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/lx/pll_reset.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0, DIMM1}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* Note: must do this AFTER the early_setup! It is counting on some
+ * early MSR setup for CS5536.
+ */
+ /* cs5536_disable_internal_uart: disable them for now, set them
+ * up later...
+ */
+ /* If debug. real setup done in chipset init via devicetree.cb. */
+ cs5536_setup_onchipuart(1);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset();
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
+ return;
+}
diff --git a/src/mainboard/win_enterprise/Kconfig b/src/mainboard/win_enterprise/Kconfig
new file mode 100644
index 0000000..0283794
--- /dev/null
+++ b/src/mainboard/win_enterprise/Kconfig
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+if VENDOR_WIN_ENTERPRISE
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_WIN_ENTERPRISE_MB6047
+ bool "MB6047"
+
+config BOARD_WIN_ENTERPRISE_PL6064
+ bool "PL6064"
+
+endchoice
+
+source "src/mainboard/win_enterprise/mb6047/Kconfig"
+source "src/mainboard/win_enterprise/pl6064/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Win Enterprise"
+
+endif # VENDOR_WIN_ENTERPRISE
diff --git a/src/mainboard/win_enterprise/mb6047/Kconfig b/src/mainboard/win_enterprise/mb6047/Kconfig
new file mode 100644
index 0000000..a32c483
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/Kconfig
@@ -0,0 +1,68 @@
+if BOARD_WIN_ENTERPRISE_MB6047
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_SOCKET_940
+ select NORTHBRIDGE_AMD_AMDK8
+ select SOUTHBRIDGE_NVIDIA_CK804
+ select SUPERIO_WINBOND_W83627THG
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_512
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select QRANK_DIMM_SUPPORT
+ select CK804_USE_NIC
+ select CK804_USE_ACI
+ select SET_FIDVID
+
+config MAINBOARD_DIR
+ string
+ default win_enterprise/mb6047
+
+config APIC_ID_OFFSET
+ hex
+ default 0x10
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MB6047"
+
+config MAX_CPUS
+ int
+ default 2
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x20
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config CK804_PCI_E_X
+ int
+ default 0
+
+config VGA_BIOS_ID
+ string
+ default "126f,0720"
+
+config VGA_BIOS_FILE
+ string
+ default "DM22383.ROM"
+
+endif # BOARD_WIN_ENTERPRISE_MB6047
diff --git a/src/mainboard/win_enterprise/mb6047/acpi_tables.c b/src/mainboard/win_enterprise/mb6047/acpi_tables.c
new file mode 100644
index 0000000..15443ee
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/acpi_tables.c
@@ -0,0 +1,64 @@
+/*
+ * Island Aruma ACPI support
+ * written by Stefan Reinauer <stepan at openbios.org>
+ * (C) 2005 Stefan Reinauer
+ *
+ *
+ * Copyright 2005 AMD
+ * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+#include "northbridge/amd/amdk8/acpi.h"
+#include <cpu/amd/powernow.h>
+
+/* APIC */
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ device_t dev;
+ struct resource *res;
+
+ get_bus_conf();
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write NVIDIA CK804 IOAPIC. */
+ dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
+ ASSERT(dev != NULL);
+
+ res = find_resource(dev, PCI_BASE_ADDRESS_1);
+ ASSERT(res != NULL);
+
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
+ res->base, 0);
+ /* Initialize interrupt mapping if mptable.c didn't. */
+#if (!CONFIG_GENERATE_MP_TABLE)
+ pci_write_config32(dev, 0x7c, 0x0120d218);
+ pci_write_config32(dev, 0x80, 0x12008a00);
+ pci_write_config32(dev, 0x84, 0x0000007d);
+#endif
+
+ /* IRQ9 */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW);
+
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ /* acpi_create_madt_lapic_nmis returns current, not size. */
+ current = acpi_create_madt_lapic_nmis(current, 5, 1);
+
+ return current;
+}
diff --git a/src/mainboard/win_enterprise/mb6047/board_info.txt b/src/mainboard/win_enterprise/mb6047/board_info.txt
new file mode 100644
index 0000000..7680e6f
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/board_info.txt
@@ -0,0 +1 @@
+Category: half
diff --git a/src/mainboard/win_enterprise/mb6047/cmos.layout b/src/mainboard/win_enterprise/mb6047/cmos.layout
new file mode 100644
index 0000000..d8e2eee
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/cmos.layout
@@ -0,0 +1,96 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 DDR400
+8 1 DDR333
+8 2 DDR266
+8 3 DDR200
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/win_enterprise/mb6047/devicetree.cb b/src/mainboard/win_enterprise/mb6047/devicetree.cb
new file mode 100644
index 0000000..81f5aae
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/devicetree.cb
@@ -0,0 +1,120 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device cpu_cluster 0 on # (L)APIC cluster
+ chip cpu/amd/socket_940 # CPU socket
+ device lapic 0 on end # Local APIC of the CPU
+ end
+ end
+ device domain 0 on # PCI domain
+ subsystemid 0x10de 0xcb84 inherit
+ chip northbridge/amd/amdk8 # Northbridge / RAM controller
+ device pci 18.0 on # Link 0 == LDT 0
+ chip southbridge/nvidia/ck804 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627thg # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # PS/2 keyboard & mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # Consumer IR
+ device pnp 2e.7 off end # Game port, MIDI, GPIO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # Hardware monitor
+ io 0x60 = 0x290
+ irq 0x70 = 0
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ # chip drivers/generic/generic # DIMM 0-0-0
+ # device i2c 50 on end
+ # end
+ # chip drivers/generic/generic # DIMM 0-0-1
+ # device i2c 51 on end
+ # end
+ # chip drivers/generic/generic # DIMM 0-1-0
+ # device i2c 52 on end
+ # end
+ # chip drivers/generic/generic # DIMM 0-1-1
+ # device i2c 53 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-0-0
+ # device i2c 54 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-0-1
+ # device i2c 55 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-1-0
+ # device i2c 56 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-1-1
+ # device i2c 57 on end
+ # end
+ end
+ # device pci 1.1 on # SM 1
+ # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
+ # device i2c 2d on end
+ # end
+ # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
+ # device i2c 2e on end
+ # end
+ # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
+ # device i2c 2a on end
+ # end
+ # chip drivers/generic/generic # Winbond HWM 0x92
+ # device i2c 49 on end
+ # end
+ # chip drivers/generic/generic # Winbond HWM 0x94
+ # device i2c 4a on end
+ # end
+ # end
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on # PCI
+ # device pci 6.0 on end
+ end
+ device pci a.0 on end # NIC
+ device pci b.0 on end # PCI E 3
+ device pci c.0 on end # PCI E 2
+ device pci d.0 on end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "0"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ end
+ end
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on end # Link 2 == LDT 2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
diff --git a/src/mainboard/win_enterprise/mb6047/dsdt.asl b/src/mainboard/win_enterprise/mb6047/dsdt.asl
new file mode 100644
index 0000000..aa04d81
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/dsdt.asl
@@ -0,0 +1,210 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9 at btinternet.com>
+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
+{
+ #include "northbridge/amd/amdk8/util.asl"
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
+
+ Name (PICM, 0x00)
+ Method (_PIC, 1, Serialized) {
+ Store (Arg0, PICM)
+ }
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Top PCI device (CK804) */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0CF8, // Address Length
+ ,, , TypeStatic)
+ })
+ /* Methods bellow use SSDT to get actual MMIO regs
+ The IO ports are from 0xd00, optionally an VGA,
+ otherwise the info from MMIO is used.
+ \_SB.GXXX(node, link)
+ */
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ #include "southbridge/nvidia/ck804/acpi/ck804.asl"
+
+ /* PCI Routing Table */
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },
+ Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },
+ Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },
+ Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },
+ })
+
+ Device (PCIL)
+ {
+ Name (_ADR, 0x00090000)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ /* onboard SM720 VGA */
+ Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+ })
+ }
+
+ Device (PEX0)
+ {
+ Name (_ADR, 0x000e0000)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+ })
+ }
+
+ Device (PEX1)
+ {
+ Name (_ADR, 0x000d0000)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+ })
+ }
+
+ Device (PEX2)
+ {
+ Name (_ADR, 0x000c0000)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ })
+ }
+
+ Device (PEX3)
+ {
+ Name (_ADR, 0x000b0000)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+ })
+ }
+
+ Device (ISA) {
+ Name (_HID, EisaId ("PNP0A05"))
+ Name (_ADR, 0x00010000)
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/src/mainboard/win_enterprise/mb6047/get_bus_conf.c b/src/mainboard/win_enterprise/mb6047/get_bus_conf.c
new file mode 100644
index 0000000..5b96b05
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/get_bus_conf.c
@@ -0,0 +1,99 @@
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/multicore.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+//busnum is default
+unsigned char bus_ck804_0; //1
+unsigned char bus_ck804_1; //2
+unsigned char bus_ck804_2; //3
+unsigned char bus_ck804_3; //4
+unsigned char bus_ck804_4; //5
+unsigned char bus_ck804_5; //6
+unsigned apicid_ck804;
+
+unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ 0x0000000,
+};
+
+unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+ 0x20202020,
+};
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+
+ unsigned apicid_base;
+ unsigned sbdn;
+
+ device_t dev;
+ int i;
+
+ if (get_bus_conf_done == 1)
+ return; //do it only once
+
+ get_bus_conf_done = 1;
+
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
+
+ get_sblk_pci1234();
+
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+ sbdn = sysconf.sbdn;
+
+ bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
+
+ /* CK804 */
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0));
+ if (dev) {
+ bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804_4++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",
+ sbdn + 0x09);
+
+ bus_ck804_1 = 2;
+ bus_ck804_4 = 3;
+ }
+
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0));
+ if (dev) {
+ bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_ck804_5++;
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",
+ sbdn + 0x0d);
+
+ bus_ck804_5 = bus_ck804_4 + 1;
+ }
+
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0));
+ if (dev) {
+ bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk(BIOS_DEBUG,
+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",
+ sbdn + 0x0e);
+ }
+
+/*I/O APICs: APIC ID Version State Address*/
+ apicid_base = get_apicid_base(1);
+ apicid_ck804 = apicid_base + 0;
+}
diff --git a/src/mainboard/win_enterprise/mb6047/irq_tables.c b/src/mainboard/win_enterprise/mb6047/irq_tables.c
new file mode 100644
index 0000000..6fe7349
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/irq_tables.c
@@ -0,0 +1,136 @@
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+ Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+ uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+ uint8_t slot, uint8_t rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+extern unsigned char bus_ck804_0; //1
+extern unsigned char bus_ck804_1; //2
+extern unsigned char bus_ck804_2; //3
+extern unsigned char bus_ck804_3; //4
+extern unsigned char bus_ck804_4; //5
+extern unsigned char bus_ck804_5; //6
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ unsigned slot_num;
+ uint8_t *v;
+ unsigned sbdn;
+
+ uint8_t sum=0;
+ int i;
+
+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ sbdn = sysconf.sbdn;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (uint8_t *)(addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_ck804_0;
+ pirq->rtr_devfn = ((sbdn+9)<<3)|0;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x10de;
+ pirq->rtr_device = 0x005c;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *) ( &pirq->checksum + 1);
+ slot_num = 0;
+//pci bridge
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+
+#if 0
+//smbus
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//usb
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//audio
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+//sata
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+//sata
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+//nic
+ write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//Slot1 PCIE x16
+ write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
+ pirq_info++; slot_num++;
+
+//firewire
+ write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+ pirq_info++; slot_num++;
+
+//Slot2 pci
+ write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
+ pirq_info++; slot_num++;
+#endif
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "done.\n");
+
+ return (unsigned long) pirq_info;
+
+}
diff --git a/src/mainboard/win_enterprise/mb6047/mainboard.c b/src/mainboard/win_enterprise/mb6047/mainboard.c
new file mode 100644
index 0000000..9a8dd90
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/mainboard.c
@@ -0,0 +1,20 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/acpi.h>
+#include <cpu/amd/powernow.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+static void mainboard_acpi_fill_ssdt_generator(void) {
+ amd_generate_powernow(0, 0, 0);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/win_enterprise/mb6047/mptable.c b/src/mainboard/win_enterprise/mb6047/mptable.c
new file mode 100644
index 0000000..26e79ca
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/mptable.c
@@ -0,0 +1,104 @@
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+extern unsigned char bus_ck804_0; //1
+extern unsigned char bus_ck804_1; //2
+extern unsigned char bus_ck804_2; //3
+extern unsigned char bus_ck804_3; //4
+extern unsigned char bus_ck804_4; //5
+extern unsigned char bus_ck804_5; //6
+extern unsigned apicid_ck804;
+
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ unsigned sbdn;
+ int i, bus_isa;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+ sbdn = sysconf.sbdn;
+
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+/*I/O APICs: APIC ID Version State Address*/
+ {
+ device_t dev;
+ struct resource *res;
+ uint32_t dword;
+
+ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_1);
+ if (res) {
+ smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ }
+
+ /* Initialize interrupt mapping*/
+
+ dword = 0x0120d218;
+ pci_write_config32(dev, 0x7c, dword);
+
+ dword = 0x12008a00;
+ pci_write_config32(dev, 0x80, dword);
+
+ dword = 0x0000007d;
+ pci_write_config32(dev, 0x84, dword);
+ }
+
+ }
+
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
+
+// Onboard ck804 smbus
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
+
+// Onboard ck804 USB 1.1
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
+
+// Onboard ck804 USB 2
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
+
+// Onboard ck804 SATA 0
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
+
+// Onboard ck804 SATA 1
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
+
+//Slot PCIE x16
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
+ }
+
+//Slot PCIE x4
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
+ }
+
+//Onboard SM720 VGA
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x13); // 19
+
+/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ mptable_lintsrc(mc, bus_isa);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/win_enterprise/mb6047/romstage.c b/src/mainboard/win_enterprise/mb6047/romstage.c
new file mode 100644
index 0000000..a725beb
--- /dev/null
+++ b/src/mainboard/win_enterprise/mb6047/romstage.c
@@ -0,0 +1,150 @@
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <lib.h>
+#include <spd.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/nvidia/ck804/early_smbus.h"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "lib/delay.c"
+#include "cpu/x86/lapic.h"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627thg/w83627thg.h>
+#include "cpu/x86/bist.h"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+
+static void memreset_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/dualcore/dualcore.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#if CONFIG_SET_FIDVID
+#include "cpu/amd/model_fxx/fidvid.c"
+#endif
+#include "northbridge/amd/amdk8/early_ht.c"
+
+static void sio_setup(void)
+{
+ uint32_t dword;
+ uint8_t byte;
+
+ /* subject decoding*/
+ byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
+ byte |= 0x20;
+ pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
+
+ /* LPC Positive Decode 0 */
+ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
+ /* Serial 0, Serial 1 */
+ dword |= (1<<0) | (1<<1);
+ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
+
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const uint16_t spd_addr [] = {
+ DIMM0, 0, 0, 0,
+ DIMM1, 0, 0, 0,
+ };
+
+ int needs_reset;
+ unsigned bsp_apicid = 0, nodes;
+ struct mem_controller ctrl[8];
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ enumerate_ht_chain();
+ sio_setup();
+ }
+
+ if (bist == 0)
+ bsp_apicid = init_cpus(cpu_init_detectedx);
+
+// post_code(0x32);
+
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+#if 0
+ dump_pci_device(PCI_DEV(0, 0x18, 0));
+#endif
+
+ needs_reset = setup_coherent_ht_domain();
+
+ wait_all_core0_started();
+ // It is said that we should start core1 after all core0 launched
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
+
+#if CONFIG_SET_FIDVID
+ /* Check to see if processor is capable of changing FIDVID */
+ /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+ if ((cpuid_edx(0x80000007) & 0x6) == 0x6) {
+ msr_t msr;
+ /* Read FIDVID_STATUS */
+ msr = rdmsr(0xc0010042);
+ printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+ enable_fid_change();
+ init_fidvid_bsp(bsp_apicid);
+
+ msr = rdmsr(0xc0010042);
+ printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+ }
+#endif
+
+ needs_reset |= ht_setup_chains_x();
+ needs_reset |= ck804_early_setup_x();
+ if (needs_reset) {
+ printk(BIOS_INFO, "ht reset -\n");
+ soft_reset();
+ }
+
+ allow_all_aps_stop(bsp_apicid);
+
+ nodes = get_nodes();
+ //It's the time to set ctrl now;
+ fill_mem_ctrl(nodes, ctrl, spd_addr);
+
+ enable_smbus();
+#if 0
+ dump_spd_registers(&cpu[0]);
+ dump_smbus_registers();
+#endif
+
+ memreset_setup();
+ sdram_initialize(nodes, ctrl);
+
+#if 0
+ print_pci_devices();
+ dump_pci_devices();
+#endif
+
+ post_cache_as_ram();
+}
diff --git a/src/mainboard/win_enterprise/pl6064/Kconfig b/src/mainboard/win_enterprise/pl6064/Kconfig
new file mode 100644
index 0000000..a9929ae
--- /dev/null
+++ b/src/mainboard/win_enterprise/pl6064/Kconfig
@@ -0,0 +1,27 @@
+if BOARD_WIN_ENTERPRISE_PL6064
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_GEODE_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_512
+ select POWER_BUTTON_FORCE_ENABLE
+
+config MAINBOARD_DIR
+ string
+ default win_enterprise/pl6064
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PL6064"
+
+config IRQ_SLOT_COUNT
+ int
+ default 7
+
+endif # BOARD_WIN_ENTERPRISE_PL6064
diff --git a/src/mainboard/win_enterprise/pl6064/board_info.txt b/src/mainboard/win_enterprise/pl6064/board_info.txt
new file mode 100644
index 0000000..f939cf4
--- /dev/null
+++ b/src/mainboard/win_enterprise/pl6064/board_info.txt
@@ -0,0 +1,3 @@
+Board name: PL60640
+Category: desktop
+Board URL: http://www.win-ent.com/network-computing/network-systems/desktop-platforms/440-pl-60640.html
diff --git a/src/mainboard/win_enterprise/pl6064/cmos.layout b/src/mainboard/win_enterprise/pl6064/cmos.layout
new file mode 100644
index 0000000..9050c3d
--- /dev/null
+++ b/src/mainboard/win_enterprise/pl6064/cmos.layout
@@ -0,0 +1,72 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/win_enterprise/pl6064/devicetree.cb b/src/mainboard/win_enterprise/pl6064/devicetree.cb
new file mode 100644
index 0000000..f900f78
--- /dev/null
+++ b/src/mainboard/win_enterprise/pl6064/devicetree.cb
@@ -0,0 +1,81 @@
+chip northbridge/amd/lx
+ device domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x0000105a"
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "1" # 0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+
+ device pci d.0 on end # Ethernet 4
+ device pci a.0 on end # Ethernet 1
+ device pci b.0 on end # Ethernet 2
+ device pci c.0 on end # Ethernet 3
+ device pci e.0 on end # Slot1
+ device pci f.0 on # ISA Bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a on # ACPI
+ irq 0x70 = 9
+ end
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci f.2 on end # IDE Controller
+ device pci f.3 off end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device cpu_cluster 0 on
+ chip cpu/amd/geode_lx
+ device lapic 0 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/win_enterprise/pl6064/irq_tables.c b/src/mainboard/win_enterprise/pl6064/irq_tables.c
new file mode 100644
index 0000000..db9dfdc
--- /dev/null
+++ b/src/mainboard/win_enterprise/pl6064/irq_tables.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Win Enterprises, Inc (anishp at win-ent.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 10
+#define PIRQC 5
+#define PIRQD 10
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Miniport data */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
+ {0x00, (0x09 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 0*/
+ {0x00, (0x0A << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1*/
+ {0x00, (0x0B << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 2*/
+ {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 3 on 65 - shared switch on 64*/
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/win_enterprise/pl6064/mainboard.c b/src/mainboard/win_enterprise/pl6064/mainboard.c
new file mode 100644
index 0000000..a767631
--- /dev/null
+++ b/src/mainboard/win_enterprise/pl6064/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Win Enterprises, Inc. (anishp at win-ent.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the license.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 EXIT %s\n", __func__);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/win_enterprise/pl6064/romstage.c b/src/mainboard/win_enterprise/pl6064/romstage.c
new file mode 100644
index 0000000..47ea722
--- /dev/null
+++ b/src/mainboard/win_enterprise/pl6064/romstage.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Win Enterprises, Inc (anishp at win-ent.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <lib.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+#include "northbridge/amd/lx/raminit.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/lx/pll_reset.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
+
+#include <cpu/intel/romstage.h>
+void main(unsigned long bist)
+{
+
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0, DIMM1}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* Note: must do this AFTER the early_setup! It is counting on some
+ * early MSR setup for CS5536.
+ */
+ w83627hf_set_clksel_48(SERIAL_DEV);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset();
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
+}
diff --git a/src/mainboard/winent/Kconfig b/src/mainboard/winent/Kconfig
deleted file mode 100644
index 28c3360..0000000
--- a/src/mainboard/winent/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-if VENDOR_WINENT
-
-choice
- prompt "Mainboard model"
-
-config BOARD_WINENT_MB6047
- bool "MB6047"
-
-config BOARD_WINENT_PL6064
- bool "PL6064"
-
-endchoice
-
-source "src/mainboard/winent/mb6047/Kconfig"
-source "src/mainboard/winent/pl6064/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Win Enterprise"
-
-endif # VENDOR_WINENT
diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig
deleted file mode 100644
index 86b0ae0..0000000
--- a/src/mainboard/winent/mb6047/Kconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-if BOARD_WINENT_MB6047
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select SUPERIO_WINBOND_W83627THG
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select QRANK_DIMM_SUPPORT
- select CK804_USE_NIC
- select CK804_USE_ACI
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default winent/mb6047
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config SB_HT_CHAIN_ON_BUS0
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "MB6047"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config CK804_PCI_E_X
- int
- default 0
-
-config VGA_BIOS_ID
- string
- default "126f,0720"
-
-config VGA_BIOS_FILE
- string
- default "DM22383.ROM"
-
-endif # BOARD_WINENT_MB6047
diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c
deleted file mode 100644
index 15443ee..0000000
--- a/src/mainboard/winent/mb6047/acpi_tables.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Island Aruma ACPI support
- * written by Stefan Reinauer <stepan at openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
- device_t dev;
- struct resource *res;
-
- get_bus_conf();
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write NVIDIA CK804 IOAPIC. */
- dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
- ASSERT(dev != NULL);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- ASSERT(res != NULL);
-
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
- res->base, 0);
- /* Initialize interrupt mapping if mptable.c didn't. */
-#if (!CONFIG_GENERATE_MP_TABLE)
- pci_write_config32(dev, 0x7c, 0x0120d218);
- pci_write_config32(dev, 0x80, 0x12008a00);
- pci_write_config32(dev, 0x84, 0x0000007d);
-#endif
-
- /* IRQ9 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW);
-
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* acpi_create_madt_lapic_nmis returns current, not size. */
- current = acpi_create_madt_lapic_nmis(current, 5, 1);
-
- return current;
-}
diff --git a/src/mainboard/winent/mb6047/board_info.txt b/src/mainboard/winent/mb6047/board_info.txt
deleted file mode 100644
index 7680e6f..0000000
--- a/src/mainboard/winent/mb6047/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: half
diff --git a/src/mainboard/winent/mb6047/cmos.layout b/src/mainboard/winent/mb6047/cmos.layout
deleted file mode 100644
index d8e2eee..0000000
--- a/src/mainboard/winent/mb6047/cmos.layout
+++ /dev/null
@@ -1,96 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb
deleted file mode 100644
index 81f5aae..0000000
--- a/src/mainboard/winent/mb6047/devicetree.cb
+++ /dev/null
@@ -1,120 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_940 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x10de 0xcb84 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627thg # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off end # Consumer IR
- device pnp 2e.7 off end # Game port, MIDI, GPIO1
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 0
- end
- end
- end
- device pci 1.1 on # SM 0
- # chip drivers/generic/generic # DIMM 0-0-0
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # DIMM 0-0-1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-0
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # DIMM 1-0-0
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # DIMM 1-0-1
- # device i2c 55 on end
- # end
- # chip drivers/generic/generic # DIMM 1-1-0
- # device i2c 56 on end
- # end
- # chip drivers/generic/generic # DIMM 1-1-1
- # device i2c 57 on end
- # end
- end
- # device pci 1.1 on # SM 1
- # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
- # device i2c 2d on end
- # end
- # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
- # device i2c 2e on end
- # end
- # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
- # device i2c 2a on end
- # end
- # chip drivers/generic/generic # Winbond HWM 0x92
- # device i2c 49 on end
- # end
- # chip drivers/generic/generic # Winbond HWM 0x94
- # device i2c 4a on end
- # end
- # end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on # PCI
- # device pci 6.0 on end
- end
- device pci a.0 on end # NIC
- device pci b.0 on end # PCI E 3
- device pci c.0 on end # PCI E 2
- device pci d.0 on end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "0"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on end # Link 2 == LDT 2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/winent/mb6047/dsdt.asl b/src/mainboard/winent/mb6047/dsdt.asl
deleted file mode 100644
index aa04d81..0000000
--- a/src/mainboard/winent/mb6047/dsdt.asl
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9 at btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek at assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- Name (PICM, 0x00)
- Method (_PIC, 1, Serialized) {
- Store (Arg0, PICM)
- }
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- #include "southbridge/nvidia/ck804/acpi/ck804.asl"
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },
- Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },
- })
-
- Device (PCIL)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- /* onboard SM720 VGA */
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
- })
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
- })
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x000d0000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
- })
- }
-
- Device (PEX2)
- {
- Name (_ADR, 0x000c0000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
- }
-
- Device (PEX3)
- {
- Name (_ADR, 0x000b0000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
- })
- }
-
- Device (ISA) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
- }
- }
- }
-}
diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c
deleted file mode 100644
index 5b96b05..0000000
--- a/src/mainboard/winent/mb6047/get_bus_conf.c
+++ /dev/null
@@ -1,99 +0,0 @@
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_ck804_0; //1
-unsigned char bus_ck804_1; //2
-unsigned char bus_ck804_2; //3
-unsigned char bus_ck804_3; //4
-unsigned char bus_ck804_4; //5
-unsigned char bus_ck804_5; //6
-unsigned apicid_ck804;
-
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000000,
-};
-
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
- unsigned sbdn;
-
- device_t dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_4++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
-
- bus_ck804_1 = 2;
- bus_ck804_4 = 3;
- }
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d, 0));
- if (dev) {
- bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804_5++;
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0d);
-
- bus_ck804_5 = bus_ck804_4 + 1;
- }
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0));
- if (dev) {
- bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG,
- "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x0e);
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- apicid_base = get_apicid_base(1);
- apicid_ck804 = apicid_base + 0;
-}
diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c
deleted file mode 100644
index 6fe7349..0000000
--- a/src/mainboard/winent/mb6047/irq_tables.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-
- Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-extern unsigned char bus_ck804_0; //1
-extern unsigned char bus_ck804_1; //2
-extern unsigned char bus_ck804_2; //3
-extern unsigned char bus_ck804_3; //4
-extern unsigned char bus_ck804_4; //5
-extern unsigned char bus_ck804_5; //6
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
- unsigned sbdn;
-
- uint8_t sum=0;
- int i;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_ck804_0;
- pirq->rtr_devfn = ((sbdn+9)<<3)|0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *) ( &pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
-
-#if 0
-//smbus
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//usb
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//audio
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-//sata
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-//nic
- write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//Slot1 PCIE x16
- write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
- pirq_info++; slot_num++;
-
-//firewire
- write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++; slot_num++;
-
-//Slot2 pci
- write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
- pirq_info++; slot_num++;
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long) pirq_info;
-
-}
diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c
deleted file mode 100644
index 9a8dd90..0000000
--- a/src/mainboard/winent/mb6047/mainboard.c
+++ /dev/null
@@ -1,20 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/acpi.h>
-#include <cpu/amd/powernow.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void mainboard_acpi_fill_ssdt_generator(void) {
- amd_generate_powernow(0, 0, 0);
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c
deleted file mode 100644
index 26e79ca..0000000
--- a/src/mainboard/winent/mb6047/mptable.c
+++ /dev/null
@@ -1,104 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804_0; //1
-extern unsigned char bus_ck804_1; //2
-extern unsigned char bus_ck804_2; //3
-extern unsigned char bus_ck804_3; //4
-extern unsigned char bus_ck804_4; //5
-extern unsigned char bus_ck804_5; //6
-extern unsigned apicid_ck804;
-
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int i, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- device_t dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
- }
-
- /* Initialize interrupt mapping*/
-
- dword = 0x0120d218;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x12008a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x0000007d;
- pci_write_config32(dev, 0x84, dword);
- }
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
-
-// Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
-
-// Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
-
-// Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
-
-// Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
-
-// Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
-
-//Slot PCIE x16
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
- }
-
-//Slot PCIE x4
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
- }
-
-//Onboard SM720 VGA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x13); // 19
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c
deleted file mode 100644
index a725beb..0000000
--- a/src/mainboard/winent/mb6047/romstage.c
+++ /dev/null
@@ -1,150 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/early_smbus.h"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "lib/delay.c"
-#include "cpu/x86/lapic.h"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
-#include "cpu/x86/bist.h"
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-
-static void memreset_setup(void) { }
-static void memreset(int controllers, const struct mem_controller *ctrl) { }
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/early_setup_ss.h"
-#include "southbridge/nvidia/ck804/early_setup.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#if CONFIG_SET_FIDVID
-#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- /* subject decoding*/
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- /* Serial 0, Serial 1 */
- dword |= (1<<0) | (1<<1);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr [] = {
- DIMM0, 0, 0, 0,
- DIMM1, 0, 0, 0,
- };
-
- int needs_reset;
- unsigned bsp_apicid = 0, nodes;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
-// post_code(0x32);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
-
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
- // It is said that we should start core1 after all core0 launched
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-
-#if CONFIG_SET_FIDVID
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- if ((cpuid_edx(0x80000007) & 0x6) == 0x6) {
- msr_t msr;
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- init_fidvid_bsp(bsp_apicid);
-
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- }
-#endif
-
- needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-#if 0
- dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
-#endif
-
- memreset_setup();
- sdram_initialize(nodes, ctrl);
-
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-
- post_cache_as_ram();
-}
diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig
deleted file mode 100644
index 3a36f29..0000000
--- a/src/mainboard/winent/pl6064/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-if BOARD_WINENT_PL6064
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_GEODE_LX
- select NORTHBRIDGE_AMD_LX
- select SOUTHBRIDGE_AMD_CS5536
- select SUPERIO_WINBOND_W83627HF
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select UDELAY_TSC
- select BOARD_ROMSIZE_KB_512
- select POWER_BUTTON_FORCE_ENABLE
-
-config MAINBOARD_DIR
- string
- default winent/pl6064
-
-config MAINBOARD_PART_NUMBER
- string
- default "PL6064"
-
-config IRQ_SLOT_COUNT
- int
- default 7
-
-endif # BOARD_WINENT_PL6064
diff --git a/src/mainboard/winent/pl6064/board_info.txt b/src/mainboard/winent/pl6064/board_info.txt
deleted file mode 100644
index f939cf4..0000000
--- a/src/mainboard/winent/pl6064/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Board name: PL60640
-Category: desktop
-Board URL: http://www.win-ent.com/network-computing/network-systems/desktop-platforms/440-pl-60640.html
diff --git a/src/mainboard/winent/pl6064/cmos.layout b/src/mainboard/winent/pl6064/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/winent/pl6064/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb
deleted file mode 100644
index f900f78..0000000
--- a/src/mainboard/winent/pl6064/devicetree.cb
+++ /dev/null
@@ -1,81 +0,0 @@
-chip northbridge/amd/lx
- device domain 0 on
- device pci 1.0 on end # Northbridge
- device pci 1.1 on end # Graphics
- chip southbridge/amd/cs5536
- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
- # SIRQ Mode = Active(Quiet) mode. Save power....
- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
- register "lpc_serirq_enable" = "0x0000105a"
- register "lpc_serirq_polarity" = "0x0000EFA5"
- register "lpc_serirq_mode" = "1"
- register "enable_gpio_int_route" = "0x0D0C0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "1" # 0: host, 1:device
- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "0"
- register "com1_address" = "0x3F8"
- register "com1_irq" = "4"
- register "com2_enable" = "0"
- register "com2_address" = "0x2F8"
- register "com2_irq" = "3"
- register "unwanted_vpci[0]" = "0" # End of list has a zero
-
- device pci d.0 on end # Ethernet 4
- device pci a.0 on end # Ethernet 1
- device pci b.0 on end # Ethernet 2
- device pci c.0 on end # Ethernet 3
- device pci e.0 on end # Slot1
- device pci f.0 on # ISA Bridge
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
-
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
-
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off end # CIR
- device pnp 2e.7 off end # GAME_MIDI_GIPO1
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a on # ACPI
- irq 0x70 = 9
- end
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
- end
- device pci f.2 on end # IDE Controller
- device pci f.3 off end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
- # APIC cluster is late CPU init.
- device cpu_cluster 0 on
- chip cpu/amd/geode_lx
- device lapic 0 on end
- end
- end
-end
-
diff --git a/src/mainboard/winent/pl6064/irq_tables.c b/src/mainboard/winent/pl6064/irq_tables.c
deleted file mode 100644
index db9dfdc..0000000
--- a/src/mainboard/winent/pl6064/irq_tables.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Win Enterprises, Inc (anishp at win-ent.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 10
-#define PIRQC 5
-#define PIRQD 10
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Miniport data */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
- {0x00, (0x09 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 0*/
- {0x00, (0x0A << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1*/
- {0x00, (0x0B << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 2*/
- {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 3 on 65 - shared switch on 64*/
- {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/winent/pl6064/mainboard.c b/src/mainboard/winent/pl6064/mainboard.c
deleted file mode 100644
index a767631..0000000
--- a/src/mainboard/winent/pl6064/mainboard.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Win Enterprises, Inc. (anishp at win-ent.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the license.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 EXIT %s\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
deleted file mode 100644
index 47ea722..0000000
--- a/src/mainboard/winent/pl6064/romstage.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Win Enterprises, Inc (anishp at win-ent.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <console/console.h>
-#include <lib.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/lxdef.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-#include <spd.h>
-#include "southbridge/amd/cs5536/early_smbus.c"
-#include "southbridge/amd/cs5536/early_setup.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include "northbridge/amd/lx/raminit.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
-
- static const struct mem_controller memctrl[] = {
- {.channel0 = {DIMM0, DIMM1}}
- };
-
- SystemPreInit();
- msr_init();
-
- cs5536_early_setup();
-
- /* Note: must do this AFTER the early_setup! It is counting on some
- * early MSR setup for CS5536.
- */
- w83627hf_set_clksel_48(SERIAL_DEV);
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pll_reset();
-
- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
- sdram_initialize(1, memctrl);
-
- /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
-}
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