[coreboot-gerrit] Patch set updated for coreboot: c288527 bd82x6x/sata: Set SATA mode earlier

[Damien Zammit (damien@zamaudio.com)]

Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7192

-gerrit

commit c2885279ba186afa1d470b88235e7a324570ea8b
Author: Damien Zammit <damien at zamaudio.com>
Date:   Sat Oct 25 11:39:15 2014 +1100

    bd82x6x/sata: Set SATA mode earlier
    
    When the SATA mode is changed, the controller removes
    the existing pci device and hotplugs a new pci device silently.
    This patch sets the SATA mode the same as before, but does so
    at the chip_ops->enable_dev() level so that the pci ID
    for the new device can be read correctly, i.e. the new device
    is the first one detected on the bus.
    
    Note that the resources are read AFTER this anyway so this
    is a cosmetic change.
    
    Change-Id: I6cf1c43a7a6dc43a6f817d60b164f153bac37241
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
 src/southbridge/intel/bd82x6x/pch.c  |  7 +++++++
 src/southbridge/intel/bd82x6x/sata.c | 14 +++-----------
 src/southbridge/intel/bd82x6x/sata.h | 30 ++++++++++++++++++++++++++++++
 3 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 37a0b64..5e874d7 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -29,6 +29,7 @@
 #include <device/pci.h>
 #endif
 #include "pch.h"
+#include "sata.h"
 
 static int pch_revision_id = -1;
 static int pch_type = -1;
@@ -419,6 +420,12 @@ void pch_enable(device_t dev)
 		reg32 = pci_read_config32(dev, PCI_COMMAND);
 		reg32 |= PCI_COMMAND_SERR;
 		pci_write_config32(dev, PCI_COMMAND, reg32);
+
+		/* Initialise SATA mode early */
+		if (dev->path.pci.devfn == PCI_DEVFN(0x1f, 2)) {
+			printk(BIOS_DEBUG, "Set SATA mode early\n");
+			sata_enable(dev);
+		}
 	}
 }
 
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..5ea0109 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -18,15 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "pch.h"
-#include <pc80/mc146818rtc.h>
-
-typedef struct southbridge_intel_bd82x6x_config config_t;
+#include "sata.h"
 
 static inline u32 sir_read(struct device *dev, int idx)
 {
@@ -211,7 +203,7 @@ static void sata_init(struct device *dev)
 	pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
 }
 
-static void sata_enable(device_t dev)
+void sata_enable(device_t dev)
 {
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
@@ -256,7 +248,7 @@ static struct device_operations sata_ops = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= sata_init,
-	.enable			= sata_enable,
+	.enable			= 0,
 	.scan_bus		= 0,
 	.ops_pci		= &sata_pci_ops,
 };
diff --git a/src/southbridge/intel/bd82x6x/sata.h b/src/southbridge/intel/bd82x6x/sata.h
new file mode 100644
index 0000000..4cfe5c3
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/sata.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+#include <pc80/mc146818rtc.h>
+
+typedef struct southbridge_intel_bd82x6x_config config_t;
+void sata_enable(device_t dev);