[coreboot-gerrit] New patch to review for coreboot: 73819c6 NOTFORMERGE

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7195

-gerrit

commit 73819c6e381bf4533935f09038e4ddf0c17f836a
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sun Oct 26 10:19:15 2014 +1100

    NOTFORMERGE
    
    Change-Id: I84ff779d300360a8f726d7707a89a7e419f04655
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/southbridge/amd/agesa/hudson/spi.c   | 2 +-
 src/southbridge/amd/cimx/sb800/spi.c     | 2 +-
 src/southbridge/intel/common/spi.c       | 2 +-
 src/southbridge/intel/fsp_rangeley/spi.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index bbf6dd3..295c7bb 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -86,7 +86,7 @@ static void execute_command(void)
 
 void spi_init(void)
 {
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
 	spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index f38e691..66eaddf 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -53,7 +53,7 @@ static void execute_command(void)
 
 void spi_init()
 {
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
 	spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 2ea9a24..8cdbc37 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -322,7 +322,7 @@ void spi_init(void)
 	uint8_t *rcrb; /* Root Complex Register Block */
 	uint32_t rcba; /* Root Complex Base Address */
 	uint8_t bios_cntl;
-	device_t dev;
+	pci_devfn_t dev;
 	ich9_spi_regs *ich9_spi;
 	uint16_t hsfs;
 
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index 6df99fd..883eec4 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -370,7 +370,7 @@ void spi_init(void)
 {
 	int ich_version = 0;
 	uint8_t bios_cntl;
-	device_t dev;
+	pci_devfn_t dev;
 	uint32_t ids;
 	uint16_t vendor_id, device_id;