[coreboot-gerrit] Patch set updated for coreboot: 9e2235a mainboards/asrock/e350m1: Use driver for Nuvoton NCT5572D superio chip
Felix Held (felix-coreboot@felixheld.de)
gerrit at coreboot.org
Mon Oct 27 01:34:58 CET 2014
Felix Held (felix-coreboot at felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6266
-gerrit
commit 9e2235a2707fa31b677c8661aac0812db413647d
Author: Felix Held <felix-coreboot at felixheld.de>
Date: Sat Jul 19 00:21:43 2014 +0200
mainboards/asrock/e350m1: Use driver for Nuvoton NCT5572D superio chip
On the ASRock E350M1 a Nuvoton NCT5572D is used as SuperIO-chip. The coreboot
port to this board however used the driver of the Winbond W83627HF SuperIO,
which is compatible enough to get most stuff working, but which clears bit 6 in
register 0x2B. This switches the function of pin 38 of the NCT5572D from
RSTOUT1# output to GP36. The PERST# pin of the ethernet chip and the
unpopulated miniPCIe slot are connected to this pin, so they didn't get reset
during a reboot.
Using the newly added driver for the Nuvoton NCT5572D fixes this problem.
There is also a trace from the pin 37 of the SuperIO, which can be configured
as RSTOUT2#, to pin 82 of the USB3-chip with unknown function.
As with the wrong driver, PS/2 keyboard and mouse do work in SeaBIOS and GRUB
but not in Linux.
Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494
Signed-off-by: Felix Held <felix-coreboot at felixheld.de>
---
src/mainboard/asrock/e350m1/BiosCallOuts.c | 8 +++----
src/mainboard/asrock/e350m1/Kconfig | 2 +-
src/mainboard/asrock/e350m1/devicetree.cb | 36 ++++++++++++++----------------
src/mainboard/asrock/e350m1/romstage.c | 8 +++----
4 files changed, 25 insertions(+), 29 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index e88f4f9..7a4ee26 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -24,11 +24,6 @@
#include "SB800.h"
#include <stdlib.h>
-/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
- *
- * Board is known to have some issues with integrated NIC and
- * might need implementation to drive some GPIOs.
- */
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
@@ -100,6 +95,9 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+ /* this seems to be just copy-pasted from the AMD reference boards and needs
+ * some investigation
+ */
switch(MemData->ParameterListPtr->DDR3Voltage){
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 00cdaa7..2f2e58d 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -24,7 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
- select SUPERIO_WINBOND_W83627HF
+ select SUPERIO_NUVOTON_NCT5572D
select SB_SUPERIO_HWM
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index e2096c0..0690664 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -54,22 +54,15 @@ chip northbridge/amd/agesa/family14/root_complex
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x439d
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
+ device pci 14.3 on # LPC
+ chip superio/nuvoton/nct5572d
+ device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die
+ device pnp 2e.1 off end # LPT1; same as FDC
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.3 off # Com2
+ device pnp 2e.3 off # IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
@@ -81,19 +74,24 @@ chip northbridge/amd/agesa/family14/root_complex
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
+ irq 0x70 = 0
end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
+ device pnp 2e.7 off end # GIPO689
+ device pnp 2e.8 off end # WDT
+ device pnp 2e.9 off end # GPIO235
device pnp 2e.a on end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
+ io 0x62 = 0x0000 # SB-TSI currently not implemented
irq 0x70 = 5
end
+ device pnp 2e.c off end # PECI
+ device pnp 2e.d off end # SUSLED
+ device pnp 2e.e off # CIRWKUP
+ io 0x60 = 0x0000
+ irq 0x70 = 0
+ end
+ device pnp 2e.f off end # GPIO_PP_OD
end
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 5223360..47704ed 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -33,14 +33,14 @@
#include "agesawrapper.h"
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5572d/nct5572d.h>
#include "cpu/x86/lapic.h"
#include <sb_cimx.h>
#include "SBPLATFORM.h"
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -61,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init();
post_code(0x31);
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
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