[coreboot-gerrit] New patch to review for coreboot: 87eb950 rambi: switch MCLK from 19.2Mhz to 25Mhz
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Tue Oct 28 00:06:09 CET 2014
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7219
-gerrit
commit 87eb95004a9451f41401598c5f382079fbf454a0
Author: Kein Yuan <kein.yuan at intel.com>
Date: Fri Apr 4 15:15:14 2014 -0700
rambi: switch MCLK from 19.2Mhz to 25Mhz
With following settings
1.Coreboot 25Mhz
2.Maxim codec configured with MCLK=25Mhz
2.I2C 400Khz fixed
4.Including Enable/Disable SHDN bit when LRCLK starts/Stops
5.Removed PLL toggle workaround routine.
audio playing is smooth before/after S3, no noise when recording so change
MCLK from 19.2 back to 25Mhz.
BUG=chrome-os-partner:26948
BRANCH=firmware-rambi-5216
TEST=test audio play and record on Rambi, works fine.
Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6
Signed-off-by: Kein Yuan <kein.yuan at intel.com>
Reviewed-on: https://chromium-review.googlesource.com/193881
Tested-by: Shawn Nematbakhsh <shawnn at chromium.org>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn at chromium.org>
(cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
src/mainboard/google/rambi/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 5587006..27dadca 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -24,7 +24,7 @@ chip soc/intel/baytrail
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
- register "lpe_codec_clk_freq" = "19" # 19.2MHz clock
+ register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
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