[coreboot-gerrit] Patch set updated for coreboot: 2adcb2c soc: Don't hide pointers behind typedefs
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Tue Oct 28 14:54:32 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7226
-gerrit
commit 2adcb2c71817bd2ef9793fa19d3dc792e49e204a
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Tue Oct 28 23:00:45 2014 +1100
soc: Don't hide pointers behind typedefs
Change-Id: Ic7d97a6ca049366f1f3efb9343ed220c7cf0b1e0
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++---
src/soc/intel/baytrail/chip.c | 8 +++----
src/soc/intel/baytrail/cpu.c | 4 ++--
src/soc/intel/baytrail/ehci.c | 4 ++--
src/soc/intel/baytrail/emmc.c | 2 +-
src/soc/intel/baytrail/gfx.c | 14 +++++------
src/soc/intel/baytrail/hda.c | 2 +-
src/soc/intel/baytrail/lpe.c | 12 +++++-----
src/soc/intel/baytrail/lpss.c | 10 ++++----
src/soc/intel/baytrail/northcluster.c | 2 +-
src/soc/intel/baytrail/pcie.c | 14 +++++------
src/soc/intel/baytrail/pmutil.c | 8 +++----
src/soc/intel/baytrail/ramstage.c | 2 +-
src/soc/intel/baytrail/sata.c | 2 +-
src/soc/intel/baytrail/scc.c | 2 +-
src/soc/intel/baytrail/sd.c | 2 +-
src/soc/intel/baytrail/smihandler.c | 2 +-
src/soc/intel/baytrail/southcluster.c | 24 +++++++++----------
src/soc/intel/baytrail/spi.c | 2 +-
src/soc/intel/baytrail/xhci.c | 6 ++---
src/soc/intel/broadwell/acpi.c | 2 +-
src/soc/intel/broadwell/broadwell/me.h | 2 +-
src/soc/intel/broadwell/broadwell/pch.h | 2 +-
src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++--
src/soc/intel/broadwell/broadwell/xhci.h | 2 +-
src/soc/intel/broadwell/chip.c | 8 +++----
src/soc/intel/broadwell/cpu.c | 6 ++---
src/soc/intel/broadwell/ehci.c | 2 +-
src/soc/intel/broadwell/lpc.c | 18 +++++++--------
src/soc/intel/broadwell/me.c | 24 +++++++++----------
src/soc/intel/broadwell/pch.c | 6 ++---
src/soc/intel/broadwell/pcie.c | 32 +++++++++++++-------------
src/soc/intel/broadwell/romstage/uart.c | 2 +-
src/soc/intel/broadwell/sata.c | 2 +-
src/soc/intel/broadwell/smbus.c | 8 +++----
src/soc/intel/broadwell/smihandler.c | 2 +-
src/soc/intel/broadwell/smmrelocate.c | 6 ++---
src/soc/intel/broadwell/spi.c | 2 +-
src/soc/intel/broadwell/systemagent.c | 22 +++++++++---------
src/soc/intel/broadwell/xhci.c | 8 +++----
src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +-
src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++---
src/soc/intel/fsp_baytrail/chip.c | 10 ++++----
src/soc/intel/fsp_baytrail/cpu.c | 4 ++--
src/soc/intel/fsp_baytrail/northcluster.c | 8 +++----
src/soc/intel/fsp_baytrail/ramstage.c | 2 +-
src/soc/intel/fsp_baytrail/smihandler.c | 2 +-
src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++-----------
src/soc/intel/fsp_baytrail/spi.c | 2 +-
src/soc/nvidia/tegra/dc.h | 2 +-
src/soc/nvidia/tegra124/display.c | 2 +-
src/soc/nvidia/tegra124/soc.c | 8 +++----
src/soc/samsung/exynos5250/cpu.c | 10 ++++----
src/soc/samsung/exynos5420/cpu.c | 10 ++++----
54 files changed, 191 insertions(+), 191 deletions(-)
diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h
index a8b5fdc..4a7b536 100644
--- a/src/soc/intel/baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/baytrail/baytrail/ramstage.h
@@ -26,16 +26,16 @@
/* The baytrail_init_pre_device() function is called prior to device
* initialization, but it's after console and cbmem has been reinitialized. */
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
-void baytrail_init_cpus(device_t dev);
+void baytrail_init_cpus(struct device *dev);
void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
+void southcluster_enable_dev(struct device *dev);
#if CONFIG_HAVE_REFCODE_BLOB
void baytrail_run_reference_code(void);
#else
static inline void baytrail_run_reference_code(void) {}
#endif
void baytrail_init_scc(void);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c
index ce9eb49..1a478dc 100644
--- a/src/soc/intel/baytrail/chip.c
+++ b/src/soc/intel/baytrail/chip.c
@@ -26,7 +26,7 @@
#include <baytrail/ramstage.h>
#include "chip.h"
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@@ -40,7 +40,7 @@ static struct device_operations pci_domain_ops = {
.ops_pci_bus = pci_bus_default_ops,
};
-static void cpu_bus_noop(device_t dev) { }
+static void cpu_bus_noop(struct device *dev) { }
static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop,
@@ -51,7 +51,7 @@ static struct device_operations cpu_bus_ops = {
};
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
@@ -79,7 +79,7 @@ struct chip_operations soc_intel_baytrail_ops = {
.init = soc_init,
};
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 97d1f04..36cb32a 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -99,7 +99,7 @@ static void baytrail_set_pstate_coord(void)
wrmsr(MSR_POWER_MISC, power_misc);
}
-void baytrail_init_cpus(device_t dev)
+void baytrail_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
const struct pattrs *pattrs = pattrs_get();
@@ -142,7 +142,7 @@ void baytrail_init_cpus(device_t dev)
restore_default_smm_area(default_smm_area);
}
-static void baytrail_core_init(device_t cpu)
+static void baytrail_core_init(struct device *cpu)
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index 5d1a4d8..accfed2 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = {
REG_SCRIPT_END
};
-static void usb2_phy_init(device_t dev)
+static void usb2_phy_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script usb2_phy_script[] = {
@@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev)
reg_script_run(usb2_phy_script);
}
-static void ehci_init(device_t dev)
+static void ehci_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script ehci_hc_init[] = {
diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c
index f88614b..74bdb4b 100644
--- a/src/soc/intel/baytrail/emmc.c
+++ b/src/soc/intel/baytrail/emmc.c
@@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = {
REG_SCRIPT_END,
};
-static void emmc_init(device_t dev)
+static void emmc_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 4ed08c9..dbb2dc1 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -38,7 +38,7 @@
* Lock Power Context Base Register to point to a 24KB block
* of memory in GSM. Power context save data is stored here.
*/
-static void gfx_lock_pcbase(device_t dev)
+static void gfx_lock_pcbase(struct device *dev)
{
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
@@ -263,18 +263,18 @@ static const struct reg_script gfx_post_vbios_script[] = {
REG_SCRIPT_END
};
-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
{
reg_script_run_on_dev(dev, ops);
}
-static void gfx_pre_vbios_init(device_t dev)
+static void gfx_pre_vbios_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
gfx_run_script(dev, gpu_pre_vbios_script);
}
-static void gfx_pm_init(device_t dev)
+static void gfx_pm_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Power Management Init\n");
gfx_run_script(dev, gfx_init_script);
@@ -283,13 +283,13 @@ static void gfx_pm_init(device_t dev)
gfx_lock_pcbase(dev);
}
-static void gfx_post_vbios_init(device_t dev)
+static void gfx_post_vbios_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
gfx_run_script(dev, gfx_post_vbios_script);
}
-static void gfx_panel_setup(device_t dev)
+static void gfx_panel_setup(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script gfx_pipea_init[] = {
@@ -358,7 +358,7 @@ static void gfx_panel_setup(device_t dev)
}
}
-static void gfx_init(device_t dev)
+static void gfx_init(struct device *dev)
{
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
index c5de654..5733b95 100644
--- a/src/soc/intel/baytrail/hda.c
+++ b/src/soc/intel/baytrail/hda.c
@@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = {
0x20671f58,
};
-static void hda_init(device_t dev)
+static void hda_init(struct device *dev)
{
struct resource *res;
int codec_mask;
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 581f42b..b6fb7c2 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -45,7 +45,7 @@
#define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
-static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
+static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)
{
struct resource *res;
@@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
*field = res->base;
}
-static void lpe_enable_acpi_mode(device_t dev)
+static void lpe_enable_acpi_mode(struct device *dev)
{
static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev)
reg_script_run_on_dev(dev, ops);
}
-static void setup_codec_clock(device_t dev)
+static void setup_codec_clock(struct device *dev)
{
uint32_t reg;
int clk_reg;
@@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev)
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
-static void lpe_stash_firmware_info(device_t dev)
+static void lpe_stash_firmware_info(struct device *dev)
{
struct resource *res;
struct resource *mmio;
@@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev)
}
}
-static void lpe_init(device_t dev)
+static void lpe_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
@@ -161,7 +161,7 @@ static void lpe_init(device_t dev)
lpe_enable_acpi_mode(dev);
}
-static void lpe_read_resources(device_t dev)
+static void lpe_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index 3ee648a..c548370 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -33,7 +33,7 @@
#include "chip.h"
-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
reg_script_run_on_dev(dev, ops);
}
-static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
+static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)
{
struct reg_script ops[] = {
REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,
@@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
reg_script_run_on_dev(dev, ops);
}
-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
{
*iosf_reg = -1;
*nvs_index = -1;
@@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
}
}
-static void i2c_disable_resets(device_t dev)
+static void i2c_disable_resets(struct device *dev)
{
/* Release the I2C devices from reset. */
static const struct reg_script ops[] = {
@@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev)
}
}
-static void lpss_init(device_t dev)
+static void lpss_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
int iosf_reg, nvs_index;
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index b119e24..2d4f20b 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void)
return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
}
-static void nc_read_resources(device_t dev)
+static void nc_read_resources(struct device *dev)
{
unsigned long mmconf;
unsigned long bmbound;
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 4498f43..e530498 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -34,12 +34,12 @@
static int pll_en_off;
static uint32_t strpfusecfg;
-static inline int root_port_offset(device_t dev)
+static inline int root_port_offset(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn);
}
-static inline int is_first_port(device_t dev)
+static inline int is_first_port(struct device *dev)
{
return root_port_offset(dev) == PCIE_PORT1_FUNC;
}
@@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = {
REG_SCRIPT_END,
};
-static void byt_pcie_init(device_t dev)
+static void byt_pcie_init(struct device *dev)
{
struct reg_script init_script[] = {
REG_SCRIPT_NEXT(init_static_before_exit_latency),
@@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = {
REG_SCRIPT_END,
};
-static void check_port_enabled(device_t dev)
+static void check_port_enabled(struct device *dev)
{
int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
@@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev)
}
}
-static void check_device_present(device_t dev)
+static void check_device_present(struct device *dev)
{
/* Set slot implemented. */
pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);
@@ -172,7 +172,7 @@ static void check_device_present(device_t dev)
}
}
-static void byt_pcie_enable(device_t dev)
+static void byt_pcie_enable(struct device *dev)
{
if (is_first_port(dev)) {
struct soc_intel_baytrail_config *config = dev->chip_info;
@@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev)
southcluster_enable_dev(dev);
}
-static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)
+static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did)
{
uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index aee3726..b9820c1 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -28,9 +28,9 @@
#if defined(__SMM__)
-static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
+static const struct device *pcu_dev = PCI_DEV(0, PCU_DEV, 0);
-static inline device_t get_pcu_dev(void)
+static inline struct device *get_pcu_dev(void)
{
return pcu_dev;
}
@@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void)
#include <device/device.h>
#include <device/pci.h>
-static device_t pcu_dev;
-static device_t get_pcu_dev(void)
+static struct device *pcu_dev;
+static struct device *get_pcu_dev(void)
{
if (pcu_dev == NULL)
pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 9622930..10f7ff2 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -78,7 +78,7 @@ static const char *stepping_str[] = {
static void fill_in_pattrs(void)
{
- device_t dev;
+ struct device *dev;
msr_t msr;
struct pattrs *attrs = (struct pattrs *)pattrs_get();
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index 28a2f8c..3c69985 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -159,7 +159,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x98, reg32);
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
config_t *config = dev->chip_info;
u8 reg8;
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index 7efb66d..e2bd1dd 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -87,7 +87,7 @@ void baytrail_init_scc(void)
reg_script_run(scc_after_dll);
}
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c
index 97c8628..6068e61 100644
--- a/src/soc/intel/baytrail/sd.c
+++ b/src/soc/intel/baytrail/sd.c
@@ -34,7 +34,7 @@
#define CAP_OVERRIDE_HIGH 0xa4
# define USE_CAP_OVERRIDES (1 << 31)
-static void sd_init(device_t dev)
+static void sd_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 22b60c4..4dca798 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ struct device *dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 500a13d..d3d284d 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -43,12 +43,12 @@
#include "chip.h"
static inline void
-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)
{
mmio_resource(dev, i, addr >> 10, size >> 10);
}
-static void sc_add_mmio_resources(device_t dev)
+static void sc_add_mmio_resources(struct device *dev)
{
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
@@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size)
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void sc_add_io_resource(device_t dev, int base, int size, int index)
+static void sc_add_io_resource(struct device *dev, int base, int size, int index)
{
struct resource *res;
@@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void sc_add_io_resources(device_t dev)
+static void sc_add_io_resources(struct device *dev)
{
struct resource *res;
@@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev)
sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
}
-static void sc_read_resources(device_t dev)
+static void sc_read_resources(struct device *dev)
{
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -154,7 +154,7 @@ static void sc_rtc_init(void)
* or configuration. This is definitely a hack, but it helps the kernel
* along.
*/
-static void com1_configure_resume(device_t dev)
+static void com1_configure_resume(struct device *dev)
{
const uint16_t port = 0x3f8;
@@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev)
outb(3, port + UART8250_LCR);
}
-static void sc_init(device_t dev)
+static void sc_init(struct device *dev)
{
int i;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
@@ -224,7 +224,7 @@ static void sc_init(device_t dev)
*/
/* Set bit in function disble register to hide this device. */
-static void sc_disable_devfn(device_t dev)
+static void sc_disable_devfn(struct device *dev)
{
const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
@@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev)
}
}
-static inline void set_d3hot_bits(device_t dev, int offset)
+static inline void set_d3hot_bits(struct device *dev, int offset)
{
uint32_t reg8;
printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
@@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
* cannot put HDA into D3Hot. Instead perform this workaround to make some of
* the audio paths work for LPE audio. */
-static void hda_work_around(device_t dev)
+static void hda_work_around(struct device *dev)
{
unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
@@ -362,7 +362,7 @@ static void hda_work_around(device_t dev)
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
}
-static int place_device_in_d3hot(device_t dev)
+static int place_device_in_d3hot(struct device *dev)
{
unsigned offset;
@@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev)
}
/* Common PCI device function disable. */
-void southcluster_enable_dev(device_t dev)
+void southcluster_enable_dev(struct device *dev)
{
uint32_t reg32;
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 8677b61..4de3d91 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -290,7 +290,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
static ich9_spi_regs *spi_regs(void)
{
- device_t dev;
+ struct device *dev;
uint32_t sbase;
#ifdef __SMM__
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 8d076c2..3f3ed91 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = {
};
/* Warm Reset a USB3 port */
-static void xhci_reset_port_usb3(device_t dev, int port)
+static void xhci_reset_port_usb3(struct device *dev, int port)
{
struct reg_script reset_port_usb3_script[] = {
/* Issue Warm Port Rest to the port */
@@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port)
}
/* Prepare ports to be routed to EHCI or XHCI */
-static void xhci_route_all(device_t dev)
+static void xhci_route_all(struct device *dev)
{
static const struct reg_script xhci_route_all_script[] = {
/* USB3 SuperSpeed Enable */
@@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev)
}
}
-static void xhci_init(device_t dev)
+static void xhci_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script xhci_hc_init[] = {
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index f4cac7b..3259308 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package)
static int generate_C_state_entries(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
acpi_cstate_t map[3];
int *set;
diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h
index ddecaf8..f3021ee 100644
--- a/src/soc/intel/broadwell/broadwell/me.h
+++ b/src/soc/intel/broadwell/broadwell/me.h
@@ -465,7 +465,7 @@ typedef struct {
} __attribute__ ((packed)) mbp_plat_time;
typedef struct {
- u32 device_type : 2;
+ u32 struct device *ype : 2;
u32 reserved : 30;
} __attribute__ ((packed)) mbp_nfc_data;
diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h
index e677215..c58b695 100644
--- a/src/soc/intel/broadwell/broadwell/pch.h
+++ b/src/soc/intel/broadwell/broadwell/pch.h
@@ -47,6 +47,6 @@ int pch_is_wpt(void);
int pch_is_wpt_ulx(void);
u32 pch_read_soft_strap(int id);
void pch_log_state(void);
-void pch_disable_devfn(device_t dev);
+void pch_disable_devfn(struct device *dev);
#endif
diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h
index 685de14..d66e8cc 100644
--- a/src/soc/intel/broadwell/broadwell/ramstage.h
+++ b/src/soc/intel/broadwell/broadwell/ramstage.h
@@ -24,8 +24,8 @@
#include <chip.h>
void broadwell_init_pre_device(void *chip_info);
-void broadwell_init_cpus(device_t dev);
-void broadwell_pch_enable_dev(device_t dev);
+void broadwell_init_cpus(struct device *dev);
+void broadwell_pch_enable_dev(struct device *dev);
#if CONFIG_HAVE_REFCODE_BLOB
void broadwell_run_reference_code(void);
diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h
index 3f4fb4e..a5536fc 100644
--- a/src/soc/intel/broadwell/broadwell/xhci.h
+++ b/src/soc/intel/broadwell/broadwell/xhci.h
@@ -55,7 +55,7 @@
#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
#ifdef __SMM__
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
+void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ);
#endif
#endif
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index 94f7893..e2ab17c 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -24,7 +24,7 @@
#include <broadwell/ramstage.h>
#include <chip.h>
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@@ -36,7 +36,7 @@ static struct device_operations pci_domain_ops = {
.ops_pci_bus = &pci_ops_mmconf,
};
-static void cpu_bus_noop(device_t dev) { }
+static void cpu_bus_noop(struct device *dev) { }
static struct device_operations cpu_bus_ops = {
.read_resources = &cpu_bus_noop,
@@ -45,7 +45,7 @@ static struct device_operations cpu_bus_ops = {
.init = &broadwell_init_cpus,
};
-static void broadwell_enable(device_t dev)
+static void broadwell_enable(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
@@ -67,7 +67,7 @@ struct chip_operations soc_intel_broadwell_ops = {
.init = &broadwell_init_pre_device,
};
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device)
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 58f81fc..416fe3c 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -444,7 +444,7 @@ static void configure_c_states(void)
static void configure_thermal_target(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
@@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
}
/* All CPUs including BSP will run the following function. */
-static void cpu_core_init(device_t cpu)
+static void cpu_core_init(struct device *cpu)
{
/* Clear out pending MCEs */
configure_mca();
@@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = {
.id_table = cpu_table,
};
-void broadwell_init_cpus(device_t dev)
+void broadwell_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
int num_threads;
diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c
index a59d3c8..30f4acd 100644
--- a/src/soc/intel/broadwell/ehci.c
+++ b/src/soc/intel/broadwell/ehci.c
@@ -28,7 +28,7 @@
#include <broadwell/ehci.h>
#include <broadwell/pch.h>
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
u8 access_cntl;
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 4b21326..270316c 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -89,9 +89,9 @@ static void pch_enable_ioapic(struct device *dev)
* 0x80 - The PIRQ is not routed.
*/
-static void pch_pirq_init(device_t dev)
+static void pch_pirq_init(struct device *dev)
{
- device_t irq_dev;
+ struct device *irq_dev;
config_t *config = dev->chip_info;
pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
@@ -126,7 +126,7 @@ static void pch_pirq_init(device_t dev)
}
}
-static void pch_power_options(device_t dev)
+static void pch_power_options(struct device *dev)
{
u16 reg16;
const char *state;
@@ -325,7 +325,7 @@ static void pch_pm_init(struct device *dev)
RCBA32_OR(0x3a6c, 0x00000001);
}
-static void pch_cg_init(device_t dev)
+static void pch_cg_init(struct device *dev)
{
u32 reg32;
u16 reg16;
@@ -420,7 +420,7 @@ static void lpc_init(struct device *dev)
pch_set_acpi_mode();
}
-static void pch_lpc_add_mmio_resources(device_t dev)
+static void pch_lpc_add_mmio_resources(struct device *dev)
{
u32 reg;
struct resource *res;
@@ -482,7 +482,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size)
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index)
{
struct resource *res;
@@ -495,7 +495,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index)
{
/*
* Check if the register is enabled. If so and the base exceeds the
@@ -508,7 +508,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
}
}
-static void pch_lpc_add_io_resources(device_t dev)
+static void pch_lpc_add_io_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@@ -533,7 +533,7 @@ static void pch_lpc_add_io_resources(device_t dev)
pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
}
-static void pch_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(struct device *dev)
{
global_nvs_t *gnvs;
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 15bcc34..19bc754 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -58,11 +58,11 @@ static const char *me_bios_path_values[] = {
[ME_DISABLE_BIOS_PATH] = "Disable",
[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
};
-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
/* MMIO base address for MEI interface */
static u32 mei_base_address;
-void intel_me_mbp_clear(device_t dev);
+void intel_me_mbp_clear(struct device *dev);
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
mei_dump(ptr, dword, offset, "WRITE");
}
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -440,7 +440,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc,
* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
* state machine on the BIOS end doesn't match the ME's state machine.
*/
-static void intel_me_mbp_give_up(device_t dev)
+static void intel_me_mbp_give_up(struct device *dev)
{
struct mei_csr csr;
@@ -456,7 +456,7 @@ static void intel_me_mbp_give_up(device_t dev)
* mbp clear routine. This will wait for the ME to indicate that
* the MBP has been read and cleared.
*/
-void intel_me_mbp_clear(device_t dev)
+void intel_me_mbp_clear(struct device *dev)
{
int count;
struct me_hfs2 hfs2;
@@ -568,7 +568,7 @@ static int mkhi_end_of_post(void)
void intel_me_finalize(void)
{
- device_t dev = PCH_DEV_ME;
+ struct device *dev = PCH_DEV_ME;
struct me_hfs hfs;
u32 reg32;
@@ -629,7 +629,7 @@ static int me_icc_set_clock_enables(u32 mask)
}
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -699,7 +699,7 @@ static me_bios_path intel_me_path(device_t dev)
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -729,7 +729,7 @@ static int intel_mei_setup(device_t dev)
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -776,7 +776,7 @@ static int intel_me_extend_valid(device_t dev)
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
config_t *config = dev->chip_info;
me_bios_path path = intel_me_path(dev);
@@ -829,7 +829,7 @@ static void intel_me_init(device_t dev)
*/
}
-static void intel_me_enable(device_t dev)
+static void intel_me_enable(struct device *dev)
{
#if CONFIG_HAVE_ACPI_RESUME
/* Avoid talking to the device in S3 path */
@@ -882,7 +882,7 @@ struct mbp_payload {
* mbp seems to be following its own flow, let's retrieve it in a dedicated
* function.
*/
-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
{
mbp_header mbp_hdr;
u32 me2host_pending;
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index 82390a4..e681620 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id)
#ifndef __PRE_RAM__
/* Put device in D3Hot Power State */
-static void pch_enable_d3hot(device_t dev)
+static void pch_enable_d3hot(struct device *dev)
{
u32 reg32 = pci_read_config32(dev, PCH_PCS);
reg32 |= PCH_PCS_PS_D3HOT;
@@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev)
}
/* Set bit in Function Disble register to hide this device */
-void pch_disable_devfn(device_t dev)
+void pch_disable_devfn(struct device *dev)
{
switch (dev->path.pci.devfn) {
case PCH_DEVFN_ADSP: /* Audio DSP */
@@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev)
}
}
-void broadwell_pch_enable_dev(device_t dev)
+void broadwell_pch_enable_dev(struct device *dev)
{
u32 reg32;
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index a407f3c..08e4863 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -32,8 +32,8 @@
#include <broadwell/rcba.h>
#include <chip.h>
-static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
-static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
+static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or);
+static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or);
/* Low Power variant has 6 root ports. */
#define NUM_ROOT_PORTS 6
@@ -52,23 +52,23 @@ struct root_port_config {
int coalesce;
int gbe_port;
int num_ports;
- device_t ports[NUM_ROOT_PORTS];
+ struct device *ports[NUM_ROOT_PORTS];
};
static struct root_port_config rpc;
-static inline int root_port_is_first(device_t dev)
+static inline int root_port_is_first(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == 0;
}
-static inline int root_port_is_last(device_t dev)
+static inline int root_port_is_last(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
}
/* Root ports are numbered 1..N in the documentation. */
-static inline int root_port_number(device_t dev)
+static inline int root_port_number(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) + 1;
}
@@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void)
}
}
-static void root_port_init_config(device_t dev)
+static void root_port_init_config(struct device *dev)
{
int rp;
@@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev)
/* Update devicetree with new Root Port function number assignment */
static void pch_pcie_device_set_func(int index, int pci_func)
{
- device_t dev;
+ struct device *dev;
unsigned new_devfn;
dev = rpc.ports[index];
@@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void)
int enabled_ports = 0;
for (i = 0; i < rpc.num_ports; i++) {
- device_t dev;
+ struct device *dev;
int rp;
dev = rpc.ports[i];
@@ -244,7 +244,7 @@ static void root_port_commit_config(void)
pcie_enable_clock_gating();
for (i = 0; i < rpc.num_ports; i++) {
- device_t dev;
+ struct device *dev;
u32 reg32;
dev = rpc.ports[i];
@@ -297,7 +297,7 @@ static void root_port_commit_config(void)
RCBA32(RPFN) = rpc.new_rpfn;
}
-static void root_port_mark_disable(device_t dev)
+static void root_port_mark_disable(struct device *dev)
{
/* Mark device as disabled. */
dev->enabled = 0;
@@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev)
rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
}
-static void root_port_check_disable(device_t dev)
+static void root_port_check_disable(struct device *dev)
{
int rp;
@@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev)
}
}
-static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or)
+static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or)
{
u8 reg8;
@@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or)
pci_write_config8(dev, reg, reg8);
}
-static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
+static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or)
{
u32 reg32;
@@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev)
pci_write_config16(dev, 0x1e, reg16);
}
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
{
/* Add this device to the root port config structure. */
root_port_init_config(dev);
@@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev)
root_port_commit_config();
}
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device)
diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
index 8214a8a..2517fef 100644
--- a/src/soc/intel/broadwell/romstage/uart.c
+++ b/src/soc/intel/broadwell/romstage/uart.c
@@ -52,7 +52,7 @@ void pch_uart_init(void)
{
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
u32 gpiodf = 0x131f;
- device_t dev;
+ struct device *dev;
/* Put UART in byte access mode for 16550 compatibility */
switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index e8d1fbe..24a8ebe 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -221,7 +221,7 @@ static void sata_init(struct device *dev)
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c
index a1dbdfe..c214510 100644
--- a/src/soc/intel/broadwell/smbus.c
+++ b/src/soc/intel/broadwell/smbus.c
@@ -31,7 +31,7 @@
#include <broadwell/ramstage.h>
#include <broadwell/smbus.h>
-static void pch_smbus_init(device_t dev)
+static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
@@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
@@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_BASE_ADDRESS;
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 6acd07c..49cf774 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ struct device *dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index bd1fc26..9ba6a00 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
}
}
-static u32 northbridge_get_base_reg(device_t dev, int reg)
+static u32 northbridge_get_base_reg(struct device *dev, int reg)
{
u32 value;
@@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg)
return value;
}
-static void fill_in_relocation_params(device_t dev,
+static void fill_in_relocation_params(struct device *dev,
struct smm_relocation_params *params)
{
u32 tseg_size;
@@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus,
static int cpu_smm_setup(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
int num_cpus;
msr_t msr;
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 353323a..6095cf7 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -286,7 +286,7 @@ void spi_init(void)
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
- device_t dev = PCH_DEV_LPC;
+ struct device *dev = PCH_DEV_LPC;
ich9_spi_regs *ich9_spi;
pci_read_config_dword(dev, 0xf0, &rcba);
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 787a62b..c1110ab 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -37,7 +37,7 @@
#include <broadwell/ramstage.h>
#include <broadwell/systemagent.h>
-static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
u32 pciexbar_reg;
@@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
return 0;
}
-static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
+static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
u32 bar;
@@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
/* There are special BARs that actually are programmed in the MCHBAR. These
* Intel special features, but they do consume resources that need to be
* accounted for. */
-static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
u32 *len)
{
u32 bar;
@@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
struct fixed_mmio_descriptor {
unsigned int index;
u32 size;
- int (*get_resource)(device_t dev, unsigned int index,
+ int (*get_resource)(struct device *dev, unsigned int index,
u32 *base, u32 *size);
const char *description;
};
@@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = {
* Add all known fixed MMIO ranges that hang off the host bridge/memory
* controller device.
*/
-static void mc_add_fixed_mmio_resources(device_t dev)
+static void mc_add_fixed_mmio_resources(struct device *dev)
{
int i;
@@ -184,7 +184,7 @@ struct map_entry {
const char *description;
};
-static void read_map_entry(device_t dev, struct map_entry *entry,
+static void read_map_entry(struct device *dev, struct map_entry *entry,
uint64_t *result)
{
uint64_t value;
@@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
};
-static void mc_read_map_entries(device_t dev, uint64_t *values)
+static void mc_read_map_entries(struct device *dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
@@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values)
}
}
-static void mc_report_map_entries(device_t dev, uint64_t *values)
+static void mc_report_map_entries(struct device *dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
@@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values)
printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
}
-static void mc_add_dram_resources(device_t dev)
+static void mc_add_dram_resources(struct device *dev)
{
unsigned long base_k, size_k;
unsigned long touud_k;
@@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev)
chromeos_reserve_ram_oops(dev, index++);
}
-static void systemagent_read_resources(device_t dev)
+static void systemagent_read_resources(struct device *dev)
{
/* Read standard PCI resources. */
pci_dev_read_resources(dev);
@@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev)
set_power_limits(28);
}
-static void systemagent_enable(device_t dev)
+static void systemagent_enable(struct device *dev)
{
#if CONFIG_HAVE_ACPI_RESUME
struct romstage_handoff *handoff;
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 89e1139..9530422 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -27,7 +27,7 @@
#include <broadwell/xhci.h>
#ifdef __SMM__
-static u32 usb_xhci_mem_base(device_t dev)
+static u32 usb_xhci_mem_base(struct device *dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev)
return mem_base & ~0xf;
}
-static int usb_xhci_port_count_usb3(device_t dev)
+static int usb_xhci_port_count_usb3(struct device *dev)
{
/* PCH-LP has 4 SS ports */
return 4;
@@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
* b) Poll for warm reset complete
* c) Write 1 to port change status bits
*/
-static void usb_xhci_reset_usb3(device_t dev, int all)
+static void usb_xhci_reset_usb3(struct device *dev, int all)
{
u32 status, port_disabled;
int timeout, port;
@@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
}
/* Handler for XHCI controller on entry to S3/S4/S5 */
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
+void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
index d3a2377..d991d34 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h
@@ -57,7 +57,7 @@ void rangeley_early_initialization(void);
int soc_silicon_revision(void);
int soc_silicon_type(void);
int soc_silicon_supported(int type, int rev);
-void soc_enable(device_t dev);
+void soc_enable(struct device *dev);
/* debugging functions */
void print_pci_devices(void);
diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h
index 095f09c..c1114df 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h
@@ -25,10 +25,10 @@
/* The baytrail_init_pre_device() function is called prior to device
* initialization, but it's after console and cbmem has been reinitialized. */
void baytrail_init_pre_device(void);
-void baytrail_init_cpus(device_t dev);
+void baytrail_init_cpus(struct device *dev);
void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+void southcluster_enable_dev(struct device *dev);
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c
index 839e8dc..e8f8ef4 100644
--- a/src/soc/intel/fsp_baytrail/chip.c
+++ b/src/soc/intel/fsp_baytrail/chip.c
@@ -25,12 +25,12 @@
#include <drivers/intel/fsp/fsp_util.h>
#include "chip.h"
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
-static void finalize_dev (device_t dev)
+static void finalize_dev (struct device *dev)
{
/*
* Notify FSP for PostPciEnumeration.
@@ -50,7 +50,7 @@ static struct device_operations pci_domain_ops = {
.ops_pci_bus = pci_bus_default_ops,
};
-static void cpu_bus_noop(device_t dev) { }
+static void cpu_bus_noop(struct device *dev) { }
static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop,
@@ -60,7 +60,7 @@ static struct device_operations cpu_bus_ops = {
.scan_bus = NULL,
};
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
{
printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",
dev_name(dev), dev->path.type);
@@ -100,7 +100,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = {
.final = &finalize_chip,
};
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 6f1e9c4..5c6375e 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = {
REG_SCRIPT_END
};
-void baytrail_init_cpus(device_t dev)
+void baytrail_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
const struct pattrs *pattrs = pattrs_get();
@@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev)
}
}
-static void baytrail_core_init(device_t cpu)
+static void baytrail_core_init(struct device *cpu)
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c
index 838e554..010063e 100644
--- a/src/soc/intel/fsp_baytrail/northcluster.c
+++ b/src/soc/intel/fsp_baytrail/northcluster.c
@@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void)
static int get_pcie_bar(u32 *base, u32 *len)
{
- device_t dev;
+ struct device *dev;
u32 pciexbar_reg;
*base = 0;
@@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index)
return index;
}
-static void mc_add_dram_resources(device_t dev)
+static void mc_add_dram_resources(struct device *dev)
{
u32 bmbound, bsmmrrl;
int index = 0;
@@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev)
index = add_fixed_resources(dev, index);
}
-static void nc_read_resources(device_t dev)
+static void nc_read_resources(struct device *dev)
{
/* Call the normal read_resources */
pci_dev_read_resources(dev);
@@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev)
mc_add_dram_resources(dev);
}
-static void nc_enable(device_t dev)
+static void nc_enable(struct device *dev)
{
print_fsp_info();
}
diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c
index 814b16e..55abb4d 100644
--- a/src/soc/intel/fsp_baytrail/ramstage.c
+++ b/src/soc/intel/fsp_baytrail/ramstage.c
@@ -76,7 +76,7 @@ static const char *stepping_str[] = {
static void fill_in_pattrs(void)
{
- device_t dev;
+ struct device *dev;
msr_t msr;
struct pattrs *attrs = (struct pattrs *)pattrs_get();
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index 2225964..50b6ef4 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index 2216902..307b006 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -51,12 +51,12 @@
typedef struct soc_intel_fsp_baytrail_config config_t;
static inline void
-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)
{
mmio_resource(dev, i, addr >> 10, size >> 10);
}
-static void sc_add_mmio_resources(device_t dev)
+static void sc_add_mmio_resources(struct device *dev)
{
#ifndef CONFIG_VIRTUAL_ROM_SIZE
#error CONFIG_VIRTUAL_ROM_SIZE must be set.
@@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev)
*/
static void write_pci_config_irqs(void)
{
- device_t irq_dev;
- device_t targ_dev;
+ struct device *irq_dev;
+ struct device *targ_dev;
uint8_t int_line = 0;
uint8_t original_int_pin = 0;
uint8_t new_int_pin = 0;
@@ -255,7 +255,7 @@ static void write_pci_config_irqs(void)
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
}
-static void sc_pirq_init(device_t dev)
+static void sc_pirq_init(struct device *dev)
{
int i, j;
int pirq;
@@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size)
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void sc_add_io_resource(device_t dev, int base, int size, int index)
+static void sc_add_io_resource(struct device *dev, int base, int size, int index)
{
struct resource *res;
@@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index)
IORESOURCE_FIXED;
}
-static void sc_add_io_resources(device_t dev)
+static void sc_add_io_resources(struct device *dev)
{
struct resource *res;
u8 io_index = 0;
@@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev)
sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
}
-static void sc_read_resources(device_t dev)
+static void sc_read_resources(struct device *dev)
{
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -409,7 +409,7 @@ static void sc_init(struct device *dev)
*/
/* Set bit in function disable register to hide this device. */
-static void sc_disable_devfn(device_t dev)
+static void sc_disable_devfn(struct device *dev)
{
const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
@@ -505,7 +505,7 @@ static void sc_disable_devfn(device_t dev)
}
}
-static inline void set_d3hot_bits(device_t dev, int offset)
+static inline void set_d3hot_bits(struct device *dev, int offset)
{
uint32_t reg8;
printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
@@ -517,7 +517,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
* cannot put HDA into D3Hot. Instead perform this workaround to make some of
* the audio paths work for LPE audio. */
-static void hda_work_around(device_t dev)
+static void hda_work_around(struct device *dev)
{
unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
@@ -534,7 +534,7 @@ static void hda_work_around(device_t dev)
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
}
-static int place_device_in_d3hot(device_t dev)
+static int place_device_in_d3hot(struct device *dev)
{
unsigned offset;
@@ -611,7 +611,7 @@ static int place_device_in_d3hot(device_t dev)
}
/* Common PCI device function disable. */
-void southcluster_enable_dev(device_t dev)
+void southcluster_enable_dev(struct device *dev)
{
uint32_t reg32;
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 4feb502..b64e1cb 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -288,7 +288,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
static ich9_spi_regs *spi_regs(void)
{
- device_t dev;
+ struct device *dev;
uint32_t sbase;
#ifdef __SMM__
diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h
index 48ffbda..895fd89 100644
--- a/src/soc/nvidia/tegra/dc.h
+++ b/src/soc/nvidia/tegra/dc.h
@@ -567,7 +567,7 @@ struct disp_ctl_win {
u32 out_h; /* Height of output window in pixels */
};
-void display_startup(device_t dev);
+void display_startup(struct device *dev);
void dp_bringup(u32 winb_addr);
unsigned int fb_base_mb(void);
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c
index 00dfbb6..9cc0cf0 100644
--- a/src/soc/nvidia/tegra124/display.c
+++ b/src/soc/nvidia/tegra124/display.c
@@ -234,7 +234,7 @@ uint32_t fb_base_mb(void)
/* this is really aimed at the lcd panel. That said, there are two display
* devices on this part and we may someday want to extend it for other boards.
*/
-void display_startup(device_t dev)
+void display_startup(struct device *dev)
{
u32 val;
int i;
diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c
index 11a52c4..eb8002b 100644
--- a/src/soc/nvidia/tegra124/soc.c
+++ b/src/soc/nvidia/tegra124/soc.c
@@ -29,7 +29,7 @@
* Will break if we get 2. Sigh.
* We assume it's all multiples of MiB for MMUs sake.
*/
-static void soc_enable(device_t dev)
+static void soc_enable(struct device *dev)
{
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB;
@@ -39,13 +39,13 @@ static void soc_enable(device_t dev)
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
}
-static void soc_init(device_t dev)
+static void soc_init(struct device *dev)
{
display_startup(dev);
printk(BIOS_INFO, "CPU: Tegra124\n");
}
-static void soc_noop(device_t dev)
+static void soc_noop(struct device *dev)
{
}
@@ -57,7 +57,7 @@ static struct device_operations soc_ops = {
.scan_bus = 0,
};
-static void enable_tegra124_dev(device_t dev)
+static void enable_tegra124_dev(struct device *dev)
{
dev->ops = &soc_ops;
}
diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c
index b8b88d7..c4561f6 100644
--- a/src/soc/samsung/exynos5250/cpu.c
+++ b/src/soc/samsung/exynos5250/cpu.c
@@ -59,7 +59,7 @@ static void set_cpu_id(void)
* involving lots of machine and callbacks, is hard to debug and
* verify.
*/
-static void exynos_displayport_init(device_t dev, u32 lcdbase,
+static void exynos_displayport_init(struct device *dev, u32 lcdbase,
unsigned long fb_size)
{
struct soc_samsung_exynos5250_config *conf = dev->chip_info;
@@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase,
lcd_ctrl_init(fb_size, &panel, (void *)lcdbase);
}
-static void cpu_enable(device_t dev)
+static void cpu_enable(struct device *dev)
{
unsigned long fb_size = FB_SIZE_KB * KiB;
u32 lcdbase = get_fb_base_kb() * KiB;
@@ -123,13 +123,13 @@ static void cpu_enable(device_t dev)
set_cpu_id();
}
-static void cpu_init(device_t dev)
+static void cpu_init(struct device *dev)
{
printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n",
cpu_id, get_arm_clk() / (1024*1024));
}
-static void cpu_noop(device_t dev)
+static void cpu_noop(struct device *dev)
{
}
@@ -141,7 +141,7 @@ static struct device_operations cpu_ops = {
.scan_bus = 0,
};
-static void enable_exynos5250_dev(device_t dev)
+static void enable_exynos5250_dev(struct device *dev)
{
dev->ops = &cpu_ops;
}
diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c
index 506b676..b646f82 100644
--- a/src/soc/samsung/exynos5420/cpu.c
+++ b/src/soc/samsung/exynos5420/cpu.c
@@ -73,7 +73,7 @@ static void set_cpu_id(void)
* involving lots of machine and callbacks, is hard to debug and
* verify.
*/
-static void exynos_displayport_init(device_t dev, u32 lcdbase,
+static void exynos_displayport_init(struct device *dev, u32 lcdbase,
unsigned long fb_size)
{
struct soc_samsung_exynos5420_config *conf = dev->chip_info;
@@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index)
}
}
-static void cpu_enable(device_t dev)
+static void cpu_enable(struct device *dev)
{
unsigned long fb_size = FB_SIZE_KB * KiB;
u32 lcdbase = get_fb_base_kb() * KiB;
@@ -154,13 +154,13 @@ static void cpu_enable(device_t dev)
set_cpu_id();
}
-static void cpu_init(device_t dev)
+static void cpu_init(struct device *dev)
{
printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n",
cpu_id, get_arm_clk() / 1000000);
}
-static void cpu_noop(device_t dev)
+static void cpu_noop(struct device *dev)
{
}
@@ -172,7 +172,7 @@ static struct device_operations cpu_ops = {
.scan_bus = 0,
};
-static void enable_exynos5420_dev(device_t dev)
+static void enable_exynos5420_dev(struct device *dev)
{
dev->ops = &cpu_ops;
}
More information about the coreboot-gerrit
mailing list