[coreboot-gerrit] Patch set updated for coreboot: 101daeb southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147

-gerrit

commit 101daebba252d8be28bc6de2165f847697dd1317
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat Jun 28 15:36:57 2014 +1000

    southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
    
    Correct mask to select bits 4-6 inclusively as per comment and use
    bitwise operations while working with bits. Be sure to write back out
    the data on the retrain.
    
    Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
    Found-by: Clang
---
 src/southbridge/amd/rs690/cmn.c | 3 ++-
 src/southbridge/amd/rs780/cmn.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c
index 05a47b3..86a6976 100644
--- a/src/southbridge/amd/rs690/cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
@@ -285,10 +285,11 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 				/* set bit8=1, bit0-2=bit4-6 */
 				u32 tmp;
 				reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
-				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				tmp = (reg >> 4) & 0x07;	/* get bit4-6 */
 				reg &= 0xfff8;	/* clear bit0-2 */
 				reg += tmp;	/* merge */
 				reg |= 1 << 8;
+				nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
 				count++;	/* CIM said "keep in loop"?  */
 			} else {
 				res = 1;
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 497d1af..57118b8 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -326,10 +326,11 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 				/* set bit8=1, bit0-2=bit4-6 */
 				u32 tmp;
 				reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
-				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				tmp = (reg >> 4) & 0x07;	/* get bit4-6 */
 				reg &= 0xfff8;	/* clear bit0-2 */
 				reg += tmp;	/* merge */
 				reg |= 1 << 8;
+				nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
 				count++;	/* CIM said "keep in loop"?  */
 			} else {
 				res = 1;