[coreboot-gerrit] New patch to review for coreboot: 949412d intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7241

-gerrit

commit 949412d17672751def93b3c39262cc44e136011a
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Wed Oct 29 12:15:34 2014 +1100

    intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'
    
    Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/northbridge/intel/haswell/gma.c | 4 ++--
 src/soc/intel/broadwell/igd.c       | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 373f429..325edbd 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -246,7 +246,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
 	/* Enable Force Wake */
 	gtt_write(0x0a180, 1 << 5);
 	gtt_write(0x0a188, 0x00010001);
-	gtt_poll(0x130044, 1 << 0, 1 << 0);
+	gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 1 << 0);
 
 	/* GT Settings */
 	gtt_write_regs(haswell_gt_setup);
@@ -420,7 +420,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
 
 	/* Disable Force Wake */
 	gtt_write(0x0a188, 0x00010000);
-	gtt_poll(0x130044, 1 << 0, 0 << 0);
+	gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 0 << 0);
 	gtt_write(0x0a188, 0x00000001);
 }
 
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index eac9ac1..b429758 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -42,7 +42,7 @@ struct reg_script haswell_early_init_script[] = {
 	/* Enable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 1, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
 
 	/* Enable Counters */
 	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
@@ -126,7 +126,7 @@ static const struct reg_script haswell_late_init_script[] = {
 
 	/* Disable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 0, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
 
 	/* Enable power well for DP and Audio */
@@ -140,7 +140,7 @@ static const struct reg_script haswell_late_init_script[] = {
 static const struct reg_script broadwell_early_init_script[] = {
 	/* Enable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 1, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
 
 	/* Enable push bus metric control and shift */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004),
@@ -225,7 +225,7 @@ static const struct reg_script broadwell_late_init_script[] = {
 
 	/* Disable Force Wake */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
-	REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 0, GT_RETRY),
+	REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
 
 	/* Enable power well for DP and Audio */
 	REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),