[coreboot-gerrit] New patch to review for coreboot: ed4898a Include IPQ8064 SBLs code in the coreboot bootblock

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7262

-gerrit

commit ed4898aa45d19925ebf8167290c367d4903a6aca
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Mon Apr 7 18:59:53 2014 -0700

    Include IPQ8064 SBLs code in the coreboot bootblock
    
    We want the coreboot build produce an image which can be run on the
    target, even if the remaining parts of the bootprom (recovery path,
    read-write stages, gbb, etc.) are not available yet.
    
    This is achieved by including the Qualcomm SBLs blob in the bootblock.
    
    CQ-DEPEND=CL:193518
    BRANCH=None
    BUG=chrome-os-partner:27784
    TEST=manual
    
      . run the following commands inside chroot to confirm expected image
        layout (no actual code is executed on the target yet):
    
       $ emerge-storm coreboot
       $ \od -Ax -t x1 -v   /build/storm/firmware/coreboot.rom  2>/dev/null  | head -1
       000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff
       $ \od -Ax -t x1 -v   /build/storm/firmware/coreboot.rom  | grep 220000
       220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a
    
    Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/193540
    (cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200
---
 src/soc/qualcomm/ipq806x/Kconfig      |  8 ++++----
 src/soc/qualcomm/ipq806x/Makefile.inc | 23 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index 0f65990..88dbd36 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -13,11 +13,11 @@ config BOOTBLOCK_ROM_OFFSET
 
 config CBFS_HEADER_ROM_OFFSET
 	hex "offset of master CBFS header in ROM"
-	default 0x18000
+	default 0x221000
 
 config CBFS_ROM_OFFSET
 	hex "offset of CBFS data in ROM"
-	default 0x18080
+	default 0x221080
 
 config MBN_ENCAPSULATION
 	depends on USE_BLOBS
@@ -34,7 +34,7 @@ config SBL_BLOB
 	  vendor.
 
 config BOOTBLOCK_BASE
-	hex "64K bytes left for TZBSP"
-	default 0x2a010000
+	hex "256K bytes left for TZBSP"
+	default 0x2a040000
 
 endif
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 7c4b48d..80e80fb 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -7,12 +7,25 @@ romstage-y += timer.c
 ramstage-y += cbfs.c
 ramstage-y += timer.c
 
-ifeq ($(CONFIG_MBN_ENCAPSULATION),y)
+ifeq ($(CONFIG_USE_BLOBS),y)
 
-$(objcbfs)/%.bin: $(objcbfs)/%.elf
+# Generate the actual coreboot bootblock code
+$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
 	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY) -O binary $< $@.prembn
+	$(OBJCOPY) -O binary $< $@.tmp
+	@mv $@.tmp $@
+
+# Add MBN header to allow SBL3 to start coreboot bootblock
+$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
 	@printf "    ADD MBN    $(subst $(obj)/,,$(@))\n"
-	./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $@.prembn  $@.tmp
+	./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $< $@.tmp
 	@mv $@.tmp $@
-endif
\ No newline at end of file
+
+# Create a complete bootblock which will start up the system
+$(objcbfs)/bootblock.bin: ./$(call strip_quotes,$(CONFIG_SBL_BLOB)) \
+			   $(objcbfs)/bootblock.mbn
+	@printf "    CAT    $(subst $(obj)/,,$(@))\n"
+	@cat $^  >  $@.tmp
+	@mv $@.tmp $@
+
+endif