[coreboot-gerrit] New patch to review for coreboot: a070c18 inteltool: added support for Haswell ULT and Lynx Point LP
Dennis Wassenberg (dennis.wassenberg@secunet.com)
gerrit at coreboot.org
Thu Oct 30 16:43:47 CET 2014
Dennis Wassenberg (dennis.wassenberg at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7275
-gerrit
commit a070c18b66e12eee9209cc921345b53e0440287f
Author: Dennis Wassenberg <dennis.wassenberg at secunet.com>
Date: Thu Oct 30 10:30:40 2014 +0100
inteltool: added support for Haswell ULT and Lynx Point LP
The inteltool now supports Haswell ULT and Lync Point LP chipset
Signed-off-by: Dennis Wassenberg <dennis.wassenberg at secunet.com>
Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5
---
util/inteltool/gpio.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++
util/inteltool/inteltool.c | 4 +++
util/inteltool/inteltool.h | 5 ++-
util/inteltool/memory.c | 1 +
util/inteltool/pcie.c | 74 +++++++++++++++++++++++++++++++++++++-
util/inteltool/powermgt.c | 3 ++
util/inteltool/rootcmplx.c | 3 ++
7 files changed, 178 insertions(+), 2 deletions(-)
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 49c1325..f868ab5 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -18,6 +18,7 @@
*/
#include <stdio.h>
+
#include "inteltool.h"
typedef struct { uint16_t addr; uint32_t def; } gpio_default_t;
@@ -258,6 +259,58 @@ static const io_register_t pch_gpio_registers[] = {
{ 0x78, 4, "RESERVED" },
{ 0x7c, 4, "RESERVED" },
};
+
+static const io_register_t lynxpoint_lp_gpio_registers[] = {
+ { 0x00, 4, "GPIO_OWN1" }, // GPIO Ownership
+ { 0x04, 4, "GPIO_OWN2" }, // GPIO Ownership
+ { 0x08, 4, "GPIO_OWN3" }, // GPIO Ownership
+ { 0x0c, 4, "RESERVED" }, // Reserved
+ { 0x10, 2, "GPIPRIOQ2IOXAPIC" }, // GPI PIRQ[X:I] to IOxAPIC[39:24] Enable
+ { 0x12, 2, "RESERVED" }, // Reserved
+ { 0x14, 4, "RESERVED" }, // Reserved
+ { 0x18, 4, "GPO_BLINK" }, // GPIO Blink Enable
+ { 0x1c, 4, "GP_SER_BLINK" }, // GP Serial Blink
+ { 0x20, 4, "GP_SB_CMDSTS" }, // GP Serial Blink Command Status
+ { 0x24, 4, "GP_SB_DATA" }, // GP Serial Blink Data
+ { 0x28, 2, "GPI_NMI_EN" }, // GPI NMI Enable
+ { 0x2a, 2, "GPI_NMI_STS" }, // GPI NMI Status
+ { 0x2c, 4, "RESERVED" }, // Reserved
+ { 0x30, 4, "GPI_ROUT" }, // GPI Interrupt Input Route
+ { 0x34, 4, "RESERVED" }, // Reserved
+ { 0x38, 4, "RESERVED" }, // Reserved
+ { 0x3C, 4, "RESERVED" }, // Reserved
+ { 0x40, 4, "RESERVED" }, // Reserved
+ { 0x44, 4, "RESERVED" }, // Reserved
+ { 0x48, 4, "RESERVED" }, // Reserved
+ { 0x4C, 4, "RESERVED" }, // Reserved
+ { 0x50, 4, "ALT_GPI_SMI_STS" }, // Alternate GPI SMI Status
+ { 0x54, 4, "ALT_GPI_SMI_EN" }, // Alternate GPI SMI Enable
+ { 0x58, 4, "RESERVED" }, // Reserved
+ { 0x5C, 4, "RESERVED" }, // Reserved
+ { 0x60, 4, "GP_RST_SEL1" }, // GPIO Reset Select 1
+ { 0x64, 4, "GP_RST_SEL2" }, // GPIO Reset Select 2
+ { 0x68, 4, "GP_RST_SEL3" }, // GPIO Reset Select 3
+ { 0x6c, 4, "RESERVED" }, // Reserved
+ { 0x70, 4, "RESERVED" }, // Reserved
+ { 0x74, 4, "RESERVED" }, // Reserved
+ { 0x78, 4, "RESERVED" }, // Reserved
+ { 0x7c, 4, "GPIO_GC" }, // GPIO Global Configuration
+ { 0x80, 4, "GPI_IS[31:0]" }, // GPI Interrupt Status [31:0]
+ { 0x84, 4, "GPI_IS[63:32]" }, // GPI Interrupt Status [63:32]
+ { 0x88, 4, "GPI_IS[94:64]" }, // GPI Interrupt Status [94:64]
+ { 0x8C, 4, "RESERVED" }, // Reserved
+ { 0x90, 4, "GPI_IE[31:0]" }, // GPI Interrupt Enable [31:0]
+ { 0x94, 4, "GPI_IE[63:32]" }, // GPI Interrupt Enable [63:32]
+ { 0x98, 4, "GPI_IE[94:64]" }, // GPI Interrupt Enable [94:64]
+ { 0x9C, 4, "RESERVED" }, // Reserved
+/* { 0x100, 4, "GPnCONFIGA" }, // GPIO Configuration A Register (n = 0) */
+/* { 0x104, 4, "GPnCONFIGB" }, // GPIO Configuration B Register (n = 0) */
+/* { ... } GPIO size = 95 */
+/* { 0x3f0, 4, "GPnCONFIGA" }, // GPIO Configuration A Register (n = 94) */
+/* { 0x3f4, 4, "GPnCONFIGB" }, // GPIO Configuration B Register (n = 94) */
+
+};
+
/* Default values for Cougar Point desktop chipsets */
static const gpio_default_t cp_pch_desktop_defaults[] = {
{ 0x00, 0xb96ba1ff },
@@ -406,6 +459,13 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
printf("\n============= GPIOS =============\n\n");
switch (sb->device_id) {
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
+ gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+ gpio_registers = lynxpoint_lp_gpio_registers;
+ size = ARRAY_SIZE(lynxpoint_lp_gpio_registers);
+ break;
case PCI_DEVICE_ID_INTEL_Z68:
case PCI_DEVICE_ID_INTEL_P67:
case PCI_DEVICE_ID_INTEL_H67:
@@ -580,5 +640,35 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
}
}
+ switch (sb->device_id) {
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
+ for (i = 0; i < 95; i++) {
+ io_register_t tmp_gpio;
+ char gpio_name[32];
+ uint16_t tmp_addr = 0x100 + (4 * i * 2);
+
+ snprintf(gpio_name, sizeof(gpio_name), "GP%dCONFIGA", i);
+ tmp_gpio.addr = tmp_addr;
+ tmp_gpio.name = gpio_name;
+ tmp_gpio.size = 4;
+
+ if (show_all)
+ print_reg(&tmp_gpio);
+
+ snprintf(gpio_name, 32, "GP%dCONFIGB", i);
+ tmp_gpio.addr = tmp_addr + 4;
+ tmp_gpio.name = gpio_name;
+ tmp_gpio.size = 4;
+
+ if (show_all)
+ print_reg(&tmp_gpio);
+ }
+ break;
+ default:
+ break;
+ }
+
return 0;
}
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 7552dfe..5e320e2 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -79,6 +79,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C, "3rd generation (Ivy Bridge family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D, "3rd generation (Ivy Bridge family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U, "4th generation (Haswell family) Core Processor ULT" },
/* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
@@ -153,6 +154,9 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, "Lynx Point Low Power Full Featured Engineering Sample" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, "Lynx Point Low Power Premium SKU" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, "Lynx Point Low Power Base SKU" },
{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
};
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index a06c70d..612b397 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -108,7 +108,9 @@
#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d
#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e
#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f
-
+#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
+#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
+#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
@@ -159,6 +161,7 @@
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C 0x0158 /* Ivy Bridge */
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x015c /* Ivy Bridge */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */
+#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index c755de7..43f621e 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -255,6 +255,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 346d51a..9a9c1c3 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -19,7 +19,6 @@
*/
#include <stdio.h>
-#include <stdlib.h>
#include <inttypes.h>
#include "inteltool.h"
@@ -119,6 +118,63 @@ static const io_register_t sandybridge_dmi_registers[] = {
};
/*
+ * All Haswell DMI Registers per
+ *
+ * Mobile 4th Generation Intel Core TM Processor Family, Mobile Intel Pentium Processor Family,
+ * and Mobile Intel Celeron Processor Family
+ * Datasheet Volume 2
+ * 329002-002
+ */
+static const io_register_t haswell_ult_dmi_registers[] = {
+ { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
+ { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
+ { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
+ { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
+/* { 0x0E, 2, "RSVD" }, // Reserved */
+ { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
+ { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
+/* { 0x18, 2, "RSVD" }, // Reserved */
+ { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
+ { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
+ { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
+/* { 0x24, 2, "RSVD" }, // Reserved */
+ { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
+ { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability
+ { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control
+/* { 0x30, 2, "RSVD" }, // Reserved */
+ { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status
+ { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
+ { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
+/* { 0x3C, 2, "RSVD" }, // Reserved */
+ { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
+ { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */
+ { 0x44, 4, "DMIESD" }, // DMI Element Self Description
+/* { 0x48, 4, "RSVD" }, // Reserved */
+/* { 0x4C, 4, "RSVD" }, // Reserved */
+ { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
+/* { 0x54, 4, "RSVD" }, // Reserved */
+ { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
+ { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
+ { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
+/* { 0x64, 4, "RSVD" }, // Reserved */
+ { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
+/* { 0x6C, 4, "RSVD" }, // Reserved */
+/* { 0x70, 4, "RSVD" }, // Reserved */
+/* { 0x74, 4, "RSVD" }, // Reserved */
+/* { 0x78, 4, "RSVD" }, // Reserved */
+/* { 0x7C, 4, "RSVD" }, // Reserved */
+/* { 0x80, 4, "RSVD" }, // Reserved */
+/* { 0x84, 4, "RSVD" }, // Reserved */
+ { 0x88, 2, "LCTL" }, // Link Control
+ /* ... - Reserved */
+ { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status
+ { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask
+ { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status
+ { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
+/* ... - Reserved */
+};
+
+/*
* Egress Port Root Complex MMIO configuration space
*/
int print_epbar(struct pci_dev *nb)
@@ -151,6 +207,18 @@ int print_epbar(struct pci_dev *nb)
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break;
+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
+ epbar_phys = pci_read_long(nb, 0x40);
+
+ if ((epbar_phys & 0x1) == 0) {
+ printf("The PCI Express Egress Port is disabled.\n");
+ return 0;
+ } else {
+ epbar_phys &= 0xfffff000;
+ epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
+ }
+
+ break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810_DC:
case PCI_DEVICE_ID_INTEL_82810E_DC:
@@ -239,6 +307,9 @@ int print_dmibar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
dmi_registers = sandybridge_dmi_registers;
size = ARRAY_SIZE(sandybridge_dmi_registers);
+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
+ dmi_registers = haswell_ult_dmi_registers;
+ size = ARRAY_SIZE(haswell_ult_dmi_registers);
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
@@ -326,6 +397,7 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82X4X:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break;
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index 3bc4efc..773f87a 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -685,6 +685,9 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_HM76:
case PCI_DEVICE_ID_INTEL_HM75:
case PCI_DEVICE_ID_INTEL_HM70:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = pch_pm_registers;
size = ARRAY_SIZE(pch_pm_registers);
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index f1e902d..574df33 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -93,6 +93,9 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_HM76:
case PCI_DEVICE_ID_INTEL_HM75:
case PCI_DEVICE_ID_INTEL_HM70:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
+ case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
break;
case PCI_DEVICE_ID_INTEL_ICH:
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