[coreboot-gerrit] Patch set updated for coreboot: e56a233 TEST
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Thu Oct 30 18:21:10 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7198
-gerrit
commit e56a233980e97ca2075c11ec534d3ab1ffee04f8
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sun Oct 26 23:33:22 2014 +1100
TEST
Change-Id: I6f29b198569eb4834328d36ca8f69d6550ded4cf
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/cpu/amd/agesa/00730F01/model_16_init.c | 2 +-
src/cpu/amd/agesa/amd_late_init.c | 2 +-
src/cpu/amd/agesa/family10/model_10_init.c | 2 +-
src/cpu/amd/agesa/family12/model_12_init.c | 2 +-
src/cpu/amd/agesa/family14/model_14_init.c | 2 +-
src/cpu/amd/agesa/family15/model_15_init.c | 2 +-
src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +-
src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +-
src/cpu/amd/dualcore/amd_sibling.c | 6 +++---
src/cpu/amd/geode_gx1/geode_gx1_init.c | 2 +-
src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +-
src/cpu/amd/geode_lx/geode_lx_init.c | 2 +-
src/cpu/amd/model_10xxx/fidvid.c | 28 ++++++++++++++--------------
src/cpu/amd/model_10xxx/init_cpus.c | 2 +-
src/cpu/amd/model_10xxx/model_10xxx_init.c | 2 +-
src/cpu/amd/model_fxx/init_cpus.c | 2 +-
src/cpu/amd/model_fxx/model_fxx_init.c | 10 ++++++----
src/cpu/amd/quadcore/amd_sibling.c | 6 +++---
src/cpu/amd/sc520/sc520.c | 14 +++++++-------
19 files changed, 47 insertions(+), 45 deletions(-)
diff --git a/src/cpu/amd/agesa/00730F01/model_16_init.c b/src/cpu/amd/agesa/00730F01/model_16_init.c
index 8053fd1..78cfc06 100644
--- a/src/cpu/amd/agesa/00730F01/model_16_init.c
+++ b/src/cpu/amd/agesa/00730F01/model_16_init.c
@@ -37,7 +37,7 @@
#include <cpu/amd/agesa/s3_resume.h>
#endif
-static void model_16_init(device_t dev)
+static void model_16_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index cab03a3..97f5425 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -42,7 +42,7 @@ static void agesawrapper_post_device(void *unused)
AGESAWRAPPER(amdinitlate);
#if (NORTHBRIDGE_00700F00) || (NORTHBRIDGE_00730F01)
- device_t dev;
+ struct device *dev;
u32 value;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
pci_write_config32(dev, 0xF8, 0);
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
index 6fbfd1a..d00a105 100644
--- a/src/cpu/amd/agesa/family10/model_10_init.c
+++ b/src/cpu/amd/agesa/family10/model_10_init.c
@@ -34,7 +34,7 @@
#define MCI_STATUS 0x401
-static void model_10_init(device_t dev)
+static void model_10_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n");
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 635bd81..a2061e7 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -35,7 +35,7 @@
#define MCI_STATUS 0x401
-static void model_12_init(device_t dev)
+static void model_12_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 60a88c7..ca250b9 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -36,7 +36,7 @@
#define MCI_STATUS 0x401
-static void model_14_init(device_t dev)
+static void model_14_init(struct device *dev)
{
u32 i;
msr_t msr;
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
index a755e1c..c7fbd75 100644
--- a/src/cpu/amd/agesa/family15/model_15_init.c
+++ b/src/cpu/amd/agesa/family15/model_15_init.c
@@ -31,7 +31,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h>
-static void model_15_init(device_t dev)
+static void model_15_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 64c78af..b888cf2 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -35,7 +35,7 @@
#include <arch/acpi.h>
#include <cpu/amd/agesa/s3_resume.h>
-static void model_15_init(device_t dev)
+static void model_15_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index ef31f96..07b92f5 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -34,7 +34,7 @@
#include <arch/acpi.h>
#include <cpu/amd/agesa/s3_resume.h>
-static void model_16_init(device_t dev)
+static void model_16_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index d9942de..e2ad3a1 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -19,7 +19,7 @@ static int disable_siblings = !CONFIG_LOGICAL_CPUS;
static int get_max_siblings(int nodes)
{
- device_t dev;
+ struct device *dev;
int nodeid;
int siblings=0;
@@ -38,7 +38,7 @@ static int get_max_siblings(int nodes)
static void enable_apic_ext_id(int nodes)
{
- device_t dev;
+ struct device *dev;
int nodeid;
//enable APIC_EXIT_ID all the nodes
@@ -54,7 +54,7 @@ static void enable_apic_ext_id(int nodes)
unsigned get_apicid_base(unsigned ioapic_num)
{
- device_t dev;
+ struct device *dev;
int nodes;
unsigned apicid_base;
int siblings;
diff --git a/src/cpu/amd/geode_gx1/geode_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c
index 8fbf507..4f08a1c 100644
--- a/src/cpu/amd/geode_gx1/geode_gx1_init.c
+++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c
@@ -72,7 +72,7 @@ unsigned long addr;
}
#endif
-static void geode_gx1_init(device_t dev)
+static void geode_gx1_init(struct device *dev)
{
#if 0
gx1_cpu_setup();
diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c
index b8f56db..43ac808 100644
--- a/src/cpu/amd/geode_gx2/geode_gx2_init.c
+++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c
@@ -15,7 +15,7 @@ static void vsm_end_post_smi(void)
);
}
-static void geode_gx2_init(device_t dev)
+static void geode_gx2_init(struct device *dev)
{
printk(BIOS_DEBUG, "geode_gx2_init\n");
diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c
index cd931a4..1024c00 100644
--- a/src/cpu/amd/geode_lx/geode_lx_init.c
+++ b/src/cpu/amd/geode_lx/geode_lx_init.c
@@ -37,7 +37,7 @@ static void vsm_end_post_smi(void)
".byte 0x0f, 0x38\n" "pop %ax\n");
}
-static void geode_lx_init(device_t dev)
+static void geode_lx_init(struct device *dev)
{
printk(BIOS_DEBUG, "geode_lx_init\n");
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 4297c90..c0be3d0 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -134,7 +134,7 @@ static void enable_fid_change(u8 fid)
{
u32 dword;
u32 nodes;
- device_t dev;
+ struct device *dev;
int i;
nodes = get_nodes();
@@ -151,7 +151,7 @@ static void enable_fid_change(u8 fid)
}
}
-static void applyBoostFIDOffset( device_t dev ) {
+static void applyBoostFIDOffset( struct device *dev ) {
// BKDG 2.4.2.8
// revision E only, but E is apparently not supported yet, therefore untested
if ((cpuid_edx(0x80000007) & CPB_MASK)
@@ -168,7 +168,7 @@ static void applyBoostFIDOffset( device_t dev ) {
}
}
-static void enableNbPState1( device_t dev ) {
+static void enableNbPState1( struct device *dev ) {
u32 cpuRev = mctGetLogicalCPUID(0xFF);
if (cpuRev & AMD_FAM10_C3) {
u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
@@ -188,7 +188,7 @@ static void enableNbPState1( device_t dev ) {
}
}
-static u8 setPStateMaxVal( device_t dev ) {
+static u8 setPStateMaxVal( struct device *dev ) {
u8 i,maxpstate=0;
for (i = 0; i < NM_PS_REG; i++) {
msr_t msr = rdmsr(PS_REG_BASE + i);
@@ -208,7 +208,7 @@ static u8 setPStateMaxVal( device_t dev ) {
return maxpstate;
}
-static void dualPlaneOnly( device_t dev ) {
+static void dualPlaneOnly( struct device *dev ) {
// BKDG 2.4.2.7
u32 cpuRev = mctGetLogicalCPUID(0xFF);
@@ -252,7 +252,7 @@ static int vidTo100uV(u8 vid)
return voltage;
}
-static void setVSRamp(device_t dev) {
+static void setVSRamp(struct device *dev) {
/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime]
* If this field accepts 8 values between 10 and 500 us why
* does page 324 say "BIOS should set this field to 001b."
@@ -267,7 +267,7 @@ static void setVSRamp(device_t dev) {
pci_write_config32(dev, 0xd8, dword);
}
-static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
+static void recalculateVsSlamTimeSettingOnCorePre(struct device *dev)
{
u8 pviModeFlag;
u8 highVoltageVid, lowVoltageVid, bValue;
@@ -443,7 +443,7 @@ static u32 power_up_down(int node, u8 procPkg) {
}
static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
- device_t dev = NODE_PCI(node, 3);
+ struct device *dev = NODE_PCI(node, 3);
/* Program fields in Clock Power/Control register0 (F3xD4) */
@@ -467,7 +467,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
}
-static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
+static void config_power_ctrl_misc_reg(struct device *dev,u32 cpuRev, u8 procPkg) {
/* check PVI/SVI */
u32 dword = pci_read_config32(dev, 0xA0);
@@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
pci_write_config32(dev, 0xA0, dword);
}
-static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
+static void config_nb_syn_ptr_adj(struct device *dev, u32 cpuRev) {
/* Note the following settings are additional from the ported
* function setFidVidRegs()
*/
@@ -522,7 +522,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
pci_write_config32(dev, 0xdc, dword);
}
-static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
+static void config_acpi_pwr_state_ctrl_regs(struct device *dev, u32 cpuRev, u8 procPkg) {
/* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */
u32 dword;
u32 c1= 1;
@@ -582,7 +582,7 @@ static void prep_fid_change(void)
{
u32 dword;
u32 nodes;
- device_t dev;
+ struct device *dev;
int i;
/* This needs to be run before any Pstate changes are requested */
@@ -785,7 +785,7 @@ static u32 needs_NB_COF_VID_update(void)
static u32 init_fidvid_core(u32 nodeid, u32 coreid)
{
- device_t dev;
+ struct device *dev;
u32 vid_max;
u32 fid_max = 0;
u8 nb_cof_vid_update = needs_NB_COF_VID_update();
@@ -946,7 +946,7 @@ static void finalPstateChange(void)
static void init_fidvid_stage2(u32 apicid, u32 nodeid)
{
msr_t msr;
- device_t dev;
+ struct device *dev;
u32 reg1fc;
u32 dtemp;
u32 nbvid;
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 10c0c8a..f6d2bd7 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -362,7 +362,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
static u32 is_core0_started(u32 nodeid)
{
u32 htic;
- device_t device;
+ struct device *device;
device = NODE_PCI(nodeid, 0);
htic = pci_read_config32(device, HT_INIT_CONTROL);
htic &= HTIC_ColdR_Detect;
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index c6cf64a..214b416 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -38,7 +38,7 @@
#define MCI_STATUS 0x401
-static void model_10xxx_init(device_t dev)
+static void model_10xxx_init(struct device *dev)
{
u8 i;
msr_t msr;
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 12d3a95..0dacc8d 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -310,7 +310,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
static u32 is_core0_started(u32 nodeid)
{
u32 htic;
- device_t device;
+ struct device *device;
device = PCI_DEV(0, 0x18 + nodeid, 0);
htic = pci_read_config32(device, HT_INIT_CONTROL);
htic &= HTIC_INIT_Detect;
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 260e83e..24e86dc 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -51,7 +51,7 @@ int is_e0_later_in_bsp(int nodeid)
return !is_cpu_pre_e0();
}
// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 2));
if (!dev)
return 0;
@@ -73,7 +73,7 @@ int is_e0_later_in_bsp(int nodeid)
int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 3));
dword = pci_read_config32(dev, 0xfc);
return (dword & 0xfff00) == 0x40f00;
@@ -228,7 +228,9 @@ static void init_ecc_memory(unsigned node_id)
unsigned long basek;
struct mtrr_state mtrr_state;
- device_t f1_dev, f2_dev, f3_dev;
+ struct device *f1_dev;
+ struct device *f2_dev;
+ struct device *f3_dev;
int enable_scrubbing;
uint32_t dcl;
@@ -456,7 +458,7 @@ static inline void k8_errata(void)
}
-static void model_fxx_init(device_t dev)
+static void model_fxx_init(struct device *dev)
{
unsigned long i;
msr_t msr;
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index d653a85..419af78 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -30,7 +30,7 @@
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern device_t get_node_pci(u32 nodeid, u32 fn);
+extern struct device *get_node_pci(u32 nodeid, u32 fn);
#if 0
static int first_time = 1;
@@ -40,7 +40,7 @@ static int first_time = 1;
static u32 get_max_siblings(u32 nodes)
{
- device_t dev;
+ struct device *dev;
u32 nodeid;
u32 siblings=0;
@@ -60,7 +60,7 @@ static u32 get_max_siblings(u32 nodes)
static void enable_apic_ext_id(u32 nodes)
{
- device_t dev;
+ struct device *dev;
u32 nodeid;
//enable APIC_EXIT_ID all the nodes
diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index 808c33c..ac3ba4e 100644
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -18,7 +18,7 @@
* set up basic things ...
* PAR should NOT go here, as it might change with the mainboard.
*/
-static void cpu_init(device_t dev)
+static void cpu_init(struct device *dev)
{
unsigned long *l = (unsigned long *) 0xfffef088;
int i;
@@ -49,7 +49,7 @@ static void sc520_enable_resources(struct device *dev) {
}
-static void sc520_read_resources(device_t dev)
+static void sc520_read_resources(struct device *dev)
{
struct resource* res;
@@ -83,9 +83,9 @@ static const struct pci_driver cpu_driver __pci_driver = {
.device = 0x3000
};
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
- device_t mc_dev;
+ struct device *mc_dev;
uint32_t pci_tolm;
printk(BIOS_SPEW, "%s\n", __func__);
pci_tolm = find_pci_tolm(dev->link_list);
@@ -130,7 +130,7 @@ static void pci_domain_set_resources(device_t dev)
}
#if 0
-void sc520_enable_resources(device_t dev) {
+void sc520_enable_resources(struct device *dev) {
printk(BIOS_SPEW, "%s\n", __func__);
printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n");
@@ -165,12 +165,12 @@ static struct device_operations pci_domain_ops = {
};
#if 0
-static void cpu_bus_init(device_t dev)
+static void cpu_bus_init(struct device *dev)
{
printk(BIOS_SPEW, "cpu_bus_init\n");
}
-static void cpu_bus_noop(device_t dev)
+static void cpu_bus_noop(struct device *dev)
{
}
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