[coreboot-gerrit] Patch set updated for coreboot: cf15cf0 mainboard: Test romstage.c
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Thu Oct 30 21:20:54 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7280
-gerrit
commit cf15cf0ceac7b35bbd0d69104dee4bdbd9504143
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Fri Oct 31 06:57:47 2014 +1100
mainboard: Test romstage.c
Change-Id: Ibcd6d28493fc3f404462238dde0fe54c61d043d3
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/amd/thatcher/romstage.c | 2 +-
src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +-
src/mainboard/asus/a8v-e_se/romstage.c | 2 +-
src/mainboard/asus/f2a85-m/romstage.c | 2 +-
src/mainboard/asus/k8v-x/romstage.c | 2 +-
src/mainboard/asus/m2n-e/romstage.c | 2 +-
src/mainboard/asus/m2v-mx_se/romstage.c | 2 +-
src/mainboard/asus/m2v/romstage.c | 4 ++--
src/mainboard/bcom/winnetp680/romstage.c | 2 +-
src/mainboard/getac/p470/romstage.c | 8 ++++----
src/mainboard/ibase/mb899/romstage.c | 2 +-
src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +-
src/mainboard/intel/cougar_canyon2/romstage.c | 2 +-
src/mainboard/intel/emeraldlake2/romstage.c | 2 +-
src/mainboard/intel/jarrell/romstage.c | 2 +-
src/mainboard/jetway/j7f2/romstage.c | 2 +-
src/mainboard/kontron/986lcd-m/romstage.c | 6 +++---
src/mainboard/kontron/ktqm77/romstage.c | 6 +++---
src/mainboard/lenovo/t60/romstage.c | 2 +-
src/mainboard/lenovo/x60/romstage.c | 2 +-
src/mainboard/roda/rk886ex/romstage.c | 8 ++++----
src/mainboard/roda/rk9/romstage.c | 2 +-
src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 ++--
src/mainboard/supermicro/x6dai_g/romstage.c | 2 +-
src/mainboard/supermicro/x6dhe_g/romstage.c | 2 +-
src/mainboard/supermicro/x6dhe_g2/romstage.c | 2 +-
src/mainboard/supermicro/x6dhr_ig/romstage.c | 2 +-
src/mainboard/supermicro/x6dhr_ig2/romstage.c | 2 +-
src/mainboard/via/epia-cn/romstage.c | 2 +-
src/mainboard/via/epia-m/romstage.c | 6 +++---
src/mainboard/via/epia-m700/romstage.c | 8 ++++----
src/mainboard/via/epia-n/romstage.c | 4 ++--
src/mainboard/via/epia/romstage.c | 4 ++--
src/mainboard/via/vt8454c/romstage.c | 2 +-
34 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index cc97866..8ebd6b4 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -46,7 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
hudson_lpc_port80();
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index c137b14..32472ee 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -90,7 +90,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 5c78ab1..74b768e 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -90,7 +90,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index caa32ca..6126cb8 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -67,7 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
hudson_pci_port80();
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 15b8682..4b897b1 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -88,7 +88,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index d12b77c..df73222 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -72,7 +72,7 @@ static void sio_setup(void)
{
u8 byte;
u32 dword;
- device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
+ pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
/* Subject decoding */
byte = pci_read_config8(dev, 0x7b);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index adcdfc7..605c19d 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -107,7 +107,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 30ba468..74d2edc 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -91,7 +91,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
@@ -189,7 +189,7 @@ static void m2v_it8712f_gpio_init(void)
static void m2v_bus_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
printk(BIOS_SPEW, "m2v_bus_init\n");
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 898ad1a..391263b 100644
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 3dab527..da40c55 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -105,19 +105,19 @@ static void ich7_enable_lpc(void)
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0x55, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0xaa, port);
}
-static void pnp_write_register(device_t dev, int reg, int val)
+static void pnp_write_register(pnp_devfn_t dev, int reg, int val)
{
unsigned int port = dev >> 8;
outb(reg, port);
@@ -126,7 +126,7 @@ static void pnp_write_register(device_t dev, int reg, int val)
static void early_superio_config(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x4e, 0x00);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 322907b..e8931f0 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -76,7 +76,7 @@ static void ich7_enable_lpc(void)
*/
static void early_superio_config_w83627ehg(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev = DUMMY_DEV;
pnp_enter_ext_func_mode(dev);
diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c
index a83bf7e..0cb238b 100644
--- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c
+++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c
@@ -69,7 +69,7 @@ void main(unsigned long bist)
console_init();
/* Enable COM3. */
- device_t dev = PNP_DEV(0x2e, 0x0b);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 0x0b);
u16 port = dev >> 8;
outb(0x55, port);
pnp_set_logical_device(dev);
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index cc956a7..c6cf529 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -56,7 +56,7 @@ static inline void reset_system(void)
static void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 220b1d7..f9f6a85 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -47,7 +47,7 @@
static void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index f1cf4c3..29553fc 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -75,7 +75,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c
index a9c71c3..fe3f48c 100644
--- a/src/mainboard/jetway/j7f2/romstage.c
+++ b/src/mainboard/jetway/j7f2/romstage.c
@@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 2c12c5d..a28593f 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -78,14 +78,14 @@ static void ich7_enable_lpc(void)
}
/* TODO: superio code should really not be in mainboard */
-static void pnp_enter_func_mode(device_t dev)
+static void pnp_enter_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_func_mode(device_t dev)
+static void pnp_exit_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
@@ -98,7 +98,7 @@ static void pnp_exit_func_mode(device_t dev)
*/
static void early_superio_config_w83627thg(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x2e, W83627THG_SP1);
pnp_enter_func_mode(dev);
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 401314c..d1a6279 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -125,14 +125,14 @@ static void rcba_config(void)
RCBA32(FD) = reg32;
}
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
@@ -142,7 +142,7 @@ static void superio_gpio_config(void)
{
int lvds_3v = 0; // 0 (5V) or 1 (3V3)
int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled
- device_t dev = PNP_DEV(0x2e, 0x9);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 0x9);
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index f11b33e..24d4ab6 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -98,7 +98,7 @@ static void ich7_enable_lpc(void)
static void early_superio_config(void)
{
int timeout = 100000;
- device_t dev = PNP_DEV(0x2e, 3);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0xa0);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 943143a..348b5fe 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -105,7 +105,7 @@ static void ich7_enable_lpc(void)
static void early_superio_config(void)
{
int timeout = 100000;
- device_t dev = PNP_DEV(0x2e, 3);
+ pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0x06);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 7cc1a1d..0278cdf 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -93,19 +93,19 @@ static void ich7_enable_lpc(void)
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
-static inline void pnp_enter_ext_func_mode(device_t dev)
+static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0x55, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
unsigned int port = dev >> 8;
outb(0xaa, port);
}
-static void pnp_write_register(device_t dev, int reg, int val)
+static void pnp_write_register(pnp_devfn_t dev, int reg, int val)
{
unsigned int port = dev >> 8;
outb(reg, port);
@@ -114,7 +114,7 @@ static void pnp_write_register(device_t dev, int reg, int val)
static void early_superio_config(void)
{
- device_t dev;
+ pnp_devfn_t dev;
dev=PNP_DEV(0x2e, 0x00);
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index c8b75e0..89026ac 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -88,7 +88,7 @@ static void default_superio_gpio_setup(void)
GP1 GP2 GP3 GP4
fd 17 88 14
*/
- const device_t sio = PNP_DEV(0x2e, 0);
+ const pnp_devfn_t sio = PNP_DEV(0x2e, 0);
/* Enter super-io's configuration state. */
pnp_enter_conf_state(sio);
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 24ecb5d..ce348ba 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -115,14 +115,14 @@ static const u8 spd_addr[] = {
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
/* TODO: superio code should really not be in mainboard */
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index 0385cad..0998b02 100644
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -70,7 +70,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID)
die("Missing 6300ESB?");
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 405a2bc..6e90958 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -73,7 +73,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID)
die("Missing esb6300?");
diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index 48945eb..b9e0d50 100644
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -73,7 +73,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID)
die("Missing ich5r?");
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 08b0ccd..e78d511 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -72,7 +72,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index dfe0da2..5d6d89c 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -72,7 +72,7 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */
/* config LPC decode for flash memory access */
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 20f99cb..d3d5857 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -44,7 +44,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c
index 3f2a0c4..2d66bbd 100644
--- a/src/mainboard/via/epia-m/romstage.c
+++ b/src/mainboard/via/epia-m/romstage.c
@@ -25,7 +25,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8235), 0);
@@ -57,7 +57,7 @@ static void enable_mainboard_devices(void)
static void enable_shadow_ram(void)
{
- device_t dev = 0; /* no need to look up 0:0.0 */
+ pci_devfn_t dev = 0; /* no need to look up 0:0.0 */
unsigned char shadowreg;
/* dev 0 for southbridge */
shadowreg = pci_read_config8(dev, 0x63);
@@ -69,7 +69,7 @@ static void enable_shadow_ram(void)
#include <cpu/intel/romstage.h>
static void main(unsigned long bist)
{
- device_t dev;
+ pci_devfn_t dev;
/* Enable VGA; 32MB buffer. */
pci_write_config8(0, 0xe1, 0xdd);
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index b00ece1..700d13f 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -55,7 +55,7 @@
*/
static int acpi_is_wakeup_early_via_vx800(void)
{
- device_t dev;
+ pci_devfn_t dev;
u16 tmp, result;
print_debug("In acpi_is_wakeup_early_via_vx800\n");
@@ -83,7 +83,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
/* All content of this function came from the cx700 port of coreboot. */
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
#if 0
/*
* Add and close this switch, since some line cause error, some
@@ -378,8 +378,8 @@ void main(unsigned long bist)
{
u16 boot_mode;
u8 rambits, Data8, Data;
- device_t device;
- /* device_t dev; */
+ pci_devfn_t device;
+ /* pci_devfn_t dev; */
/*
* Enable multifunction for northbridge. These 4 lines (until
diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index 2ede8d8..f8ba755 100644
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -58,7 +58,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 reg;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
@@ -105,7 +105,7 @@ static void enable_shadow_ram(void)
static void main(unsigned long bist)
{
unsigned long x;
- device_t dev;
+ pci_devfn_t dev;
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c
index 1d312d7..aff85a5 100644
--- a/src/mainboard/via/epia/romstage.c
+++ b/src/mainboard/via/epia/romstage.c
@@ -24,7 +24,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* dev 0 for southbridge */
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
@@ -60,7 +60,7 @@ static void enable_mainboard_devices(void)
static void enable_shadow_ram(void)
{
- device_t dev = 0;
+ pci_devfn_t dev = 0;
unsigned char shadowreg;
shadowreg = pci_read_config8(dev, 0x63);
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index f6d58c8..97f1858 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -39,7 +39,7 @@
static void enable_mainboard_devices(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
if (dev == PCI_DEV_INVALID) {
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