[coreboot-gerrit] Patch set updated for coreboot: 83a07e8 bd82x6x, ibexpeak: consolidate expresscard hotplug

Vladimir Serbinenko (phcoder@gmail.com) gerrit at coreboot.org
Fri Oct 31 23:24:55 CET 2014


Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7296

-gerrit

commit 83a07e8e18a636abe6b09edab25c9fb973117ae6
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Tue Oct 28 23:43:20 2014 +0100

    bd82x6x,ibexpeak: consolidate expresscard hotplug
    
    Change-Id: I585dec12e17e22d829baa3f2dc7aecc174f9d3b5
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/mainboard/lenovo/t520/devicetree.cb     |  2 ++
 src/mainboard/lenovo/t520/dsdt.asl          |  1 -
 src/mainboard/lenovo/t520/mainboard.c       |  8 -------
 src/mainboard/lenovo/t530/devicetree.cb     |  2 ++
 src/mainboard/lenovo/t530/dsdt.asl          |  1 -
 src/mainboard/lenovo/t530/mainboard.c       |  8 -------
 src/mainboard/lenovo/x201/devicetree.cb     |  2 ++
 src/mainboard/lenovo/x201/dsdt.asl          |  1 -
 src/mainboard/lenovo/x201/mainboard.c       |  8 -------
 src/mainboard/lenovo/x220/devicetree.cb     |  2 ++
 src/mainboard/lenovo/x220/dsdt.asl          |  1 -
 src/mainboard/lenovo/x220/mainboard.c       |  8 -------
 src/mainboard/lenovo/x230/devicetree.cb     |  2 ++
 src/mainboard/lenovo/x230/dsdt.asl          |  1 -
 src/mainboard/lenovo/x230/mainboard.c       |  8 -------
 src/southbridge/intel/bd82x6x/acpi/pcie.asl | 21 ------------------
 src/southbridge/intel/bd82x6x/chip.h        |  2 ++
 src/southbridge/intel/bd82x6x/lpc.c         | 34 +++++++++++++++++++++++++++++
 src/southbridge/intel/bd82x6x/pcie.c        |  9 ++++++++
 src/southbridge/intel/ibexpeak/lpc.c        | 34 +++++++++++++++++++++++++++++
 20 files changed, 89 insertions(+), 66 deletions(-)

diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 486e8d2..d2a4d6b 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -67,6 +67,8 @@ chip northbridge/intel/sandybridge
 			register "c2_latency" = "101"  # c2 not supported
 			register "p_cnt_throttling_supported" = "1"
 
+			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end
 			device pci 16.2 off end
diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl
index b6b4b33..0c84bfb 100644
--- a/src/mainboard/lenovo/t520/dsdt.asl
+++ b/src/mainboard/lenovo/t520/dsdt.asl
@@ -23,7 +23,6 @@
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
 #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-#define RP04_IS_EXPRESSCARD 1
 #define EC_LENOVO_H8_ME_WORKAROUND 1
 #define HAVE_LCD_SCREEN 1
 
diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c
index 387bbe0..582ef81 100644
--- a/src/mainboard/lenovo/t520/mainboard.c
+++ b/src/mainboard/lenovo/t520/mainboard.c
@@ -53,14 +53,6 @@ static void mainboard_init(device_t dev)
 	RCBA32(0x38c0) = 0x00000007;
 
 	pc_keyboard_init();
-
-	/* Enable expresscard hotplug events.  */
-	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
-			   0xd8,
-			   pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8)
-			   | (1 << 30));
-	pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
-			   0x42, 0x142);
 }
 
 /* mainboard_enable is executed as first thing after
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index c1cbca2..c44f927 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -66,6 +66,8 @@ chip northbridge/intel/sandybridge
 			register "c2_latency" = "101"  # c2 not supported
 			register "p_cnt_throttling_supported" = "1"
 
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+
 			device pci 14.0 on end # USB 3.0 Controller
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl
index c73f795..0c84bfb 100644
--- a/src/mainboard/lenovo/t530/dsdt.asl
+++ b/src/mainboard/lenovo/t530/dsdt.asl
@@ -23,7 +23,6 @@
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
 #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-#define RP03_IS_EXPRESSCARD 1
 #define EC_LENOVO_H8_ME_WORKAROUND 1
 #define HAVE_LCD_SCREEN 1
 
diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c
index f8c9dae..14e1960 100644
--- a/src/mainboard/lenovo/t530/mainboard.c
+++ b/src/mainboard/lenovo/t530/mainboard.c
@@ -56,14 +56,6 @@ static void mainboard_init(device_t dev)
 	   connected to anything and hence we don't init it.
 	 */
 	pc_keyboard_init();
-
-	/* Enable expresscard hotplug events.  */
-	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)),
-			   0xd8,
-			   pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8)
-			   | (1 << 30));
-	pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)),
-			   0x42, 0x142);
 }
 
 // mainboard_enable is executed as first thing after
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index d467e92..117c25c 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -113,6 +113,8 @@ chip northbridge/intel/nehalem
 			register "c2_latency" = "1"
 			register "docking_supported" = "1"
 
+			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+
 			device pci 16.2 on # IDE/SATA
 				subsystemid 0x17aa 0x2161
 			end
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
index 62616a8..5265a91 100644
--- a/src/mainboard/lenovo/x201/dsdt.asl
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -23,7 +23,6 @@
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
 #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-#define RP04_IS_EXPRESSCARD 1
 #define EC_LENOVO_H8_ME_WORKAROUND 1
 #define HAVE_LCD_SCREEN 1
 
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index 5b76be2..a58d415 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -102,14 +102,6 @@ static void mainboard_init(device_t dev)
 	   connected to anything and hence we don't init it.
 	 */
 	pc_keyboard_init();
-
-	/* Enable expresscard hotplug events.  */
-	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
-			   0xd8,
-			   pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8)
-			   | (1 << 30));
-	pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
-			   0x42, 0x142);
 }
 
 static void fill_ssdt(void)
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index c3b8ad9..982e30b 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -65,6 +65,8 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x0c15e1"
 			register "gen4_dec" = "0x0c06a1"
 
+			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+
 			# Enable zero-based linear PCIe root port functions
 			register "pcie_port_coalesce" = "1"
 
diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl
index b6b4b33..0c84bfb 100644
--- a/src/mainboard/lenovo/x220/dsdt.asl
+++ b/src/mainboard/lenovo/x220/dsdt.asl
@@ -23,7 +23,6 @@
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
 #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-#define RP04_IS_EXPRESSCARD 1
 #define EC_LENOVO_H8_ME_WORKAROUND 1
 #define HAVE_LCD_SCREEN 1
 
diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c
index 00e7991..2fdc204 100644
--- a/src/mainboard/lenovo/x220/mainboard.c
+++ b/src/mainboard/lenovo/x220/mainboard.c
@@ -59,14 +59,6 @@ static void mainboard_init(device_t dev)
 	   connected to anything and hence we don't init it.
 	 */
 	pc_keyboard_init();
-
-	/* Enable expresscard hotplug events.  */
-	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
-			   0xd8,
-			   pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8)
-			   | (1 << 30));
-	pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
-			   0x42, 0x142);
 }
 
 // mainboard_enable is executed as first thing after
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index f2fed1f..5130410 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -65,6 +65,8 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x0c15e1"
 			register "gen4_dec" = "0x0c06a1"
 
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+
 			# Enable zero-based linear PCIe root port functions
 			register "pcie_port_coalesce" = "1"
 			register "c2_latency" = "101"  # c2 not supported
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
index c73f795..0c84bfb 100644
--- a/src/mainboard/lenovo/x230/dsdt.asl
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -23,7 +23,6 @@
 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
 #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
 #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-#define RP03_IS_EXPRESSCARD 1
 #define EC_LENOVO_H8_ME_WORKAROUND 1
 #define HAVE_LCD_SCREEN 1
 
diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c
index a060015..da0aa65 100644
--- a/src/mainboard/lenovo/x230/mainboard.c
+++ b/src/mainboard/lenovo/x230/mainboard.c
@@ -60,14 +60,6 @@ static void mainboard_init(device_t dev)
 	   connected to anything and hence we don't init it.
 	 */
 	pc_keyboard_init();
-
-	/* Enable expresscard hotplug events.  */
-	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)),
-			   0xd8,
-			   pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8)
-			   | (1 << 30));
-	pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)),
-			   0x42, 0x142);
 }
 
 // mainboard_enable is executed as first thing after
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
index 14ae449..934cf78 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
@@ -155,16 +155,6 @@ Device (RP03)
 	{
 		Return (IRQM (RPPN))
 	}
-#ifdef RP03_IS_EXPRESSCARD
-	Device (SLOT)
-	{
-		Name (_ADR, 0x00)
-		Method (_RMV, 0, NotSerialized)
-		{
-			Return (0x01)
-		}
-	}
-#endif
 }
 
 Device (RP04)
@@ -177,17 +167,6 @@ Device (RP04)
 	{
 		Return (IRQM (RPPN))
 	}
-
-#ifdef RP04_IS_EXPRESSCARD
-	Device (SLOT)
-	{
-		Name (_ADR, 0x00)
-		Method (_RMV, 0, NotSerialized)
-		{
-			Return (0x01)
-		}
-	}
-#endif
 }
 
 Device (RP05)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 1256129..290bb05 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -87,6 +87,8 @@ struct southbridge_intel_bd82x6x_config {
 	int p_cnt_throttling_supported;
 	int c2_latency;
 	int docking_supported;
+
+	uint8_t pcie_hotplug_map[8];
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 20f20ae..62b7096 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -839,6 +839,39 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
+static void southbridge_fill_ssdt(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	config_t *chip = dev->chip_info;
+	char scope_name[] = "\\_SB.PCI0.RP0x";
+	int port;
+
+	for (port = 0; port < 8; port++) {
+		if (chip->pcie_hotplug_map[port]) {
+			int scopelen;
+			scope_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port;
+			scopelen = acpigen_write_scope(scope_name);
+
+			/*
+			  Device (SLOT)
+			  {
+			  	Name (_ADR, 0x00)
+			  	Method (_RMV, 0, NotSerialized)
+			  	{
+			  		Return (0x01)
+			  	}
+			  }
+			*/
+			static char stream[] = {
+				0x5b, 0x82, 0x14, 0x53, 0x4c, 0x4f, 0x54, 0x08, 0x5f, 0x41, 0x44,
+				0x52, 0x00, 0x14, 0x08, 0x5f, 0x52, 0x4d, 0x56, 0x00, 0xa4, 0x01
+			};
+			scopelen += acpigen_emit_stream(stream, ARRAY_SIZE(stream));
+			acpigen_patch_len(scopelen - 1);
+		}
+	}
+}
+
 static struct pci_operations pci_ops = {
 	.set_subsystem = set_subsystem,
 };
@@ -849,6 +882,7 @@ static struct device_operations device_ops = {
 	.enable_resources	= pch_lpc_enable_resources,
 	.write_acpi_tables      = acpi_write_hpet,
 	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+	.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
 	.init			= lpc_init,
 	.enable			= pch_lpc_enable,
 	.scan_bus		= scan_static_bus,
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index fadb43f..c698b12 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -218,6 +218,7 @@ static void pci_init(struct device *dev)
 {
 	u16 reg16;
 	u32 reg32;
+	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 
 	printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
 
@@ -255,6 +256,14 @@ static void pci_init(struct device *dev)
 	reg16 = pci_read_config16(dev, 0x1e);
 	//reg16 |= 0xf900;
 	pci_write_config16(dev, 0x1e, reg16);
+
+	/* Enable expresscard hotplug events.  */
+	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+		pci_write_config32(dev, 0xd8,
+				   pci_read_config32(dev, 0xd8)
+				   | (1 << 30));
+		pci_write_config16(dev, 0x42, 0x142);
+	}
 }
 
 static void pch_pcie_enable(device_t dev)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index da609da..c7a2427 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -822,6 +822,39 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
+static void southbridge_fill_ssdt(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	config_t *chip = dev->chip_info;
+	char scope_name[] = "\\_SB.PCI0.RP0x";
+	int port;
+
+	for (port = 0; port < 8; port++) {
+		if (chip->pcie_hotplug_map[port]) {
+			int scopelen;
+			scope_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port;
+			scopelen = acpigen_write_scope(scope_name);
+
+			/*
+			  Device (SLOT)
+			  {
+			  	Name (_ADR, 0x00)
+			  	Method (_RMV, 0, NotSerialized)
+			  	{
+			  		Return (0x01)
+			  	}
+			  }
+			*/
+			static char stream[] = {
+				0x5b, 0x82, 0x14, 0x53, 0x4c, 0x4f, 0x54, 0x08, 0x5f, 0x41, 0x44,
+				0x52, 0x00, 0x14, 0x08, 0x5f, 0x52, 0x4d, 0x56, 0x00, 0xa4, 0x01
+			};
+			scopelen += acpigen_emit_stream(stream, ARRAY_SIZE(stream));
+			acpigen_patch_len(scopelen - 1);
+		}
+	}
+}
+
 static struct pci_operations pci_ops = {
 	.set_subsystem = set_subsystem,
 };
@@ -831,6 +864,7 @@ static struct device_operations device_ops = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pch_lpc_enable_resources,
 	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+	.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
 	.write_acpi_tables      = acpi_write_hpet,
 	.init			= lpc_init,
 	.enable			= pch_lpc_enable,



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